hw_ints.h 16 KB

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  1. //###########################################################################
  2. //
  3. // FILE: hw_ints.h
  4. //
  5. // TITLE: Definitions of interrupt numbers for use with interrupt.c.
  6. //
  7. //###########################################################################
  8. // $TI Release: F2837xD Support Library v3.05.00.00 $
  9. // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
  10. // $Copyright:
  11. // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
  12. //
  13. // Redistribution and use in source and binary forms, with or without
  14. // modification, are permitted provided that the following conditions
  15. // are met:
  16. //
  17. // Redistributions of source code must retain the above copyright
  18. // notice, this list of conditions and the following disclaimer.
  19. //
  20. // Redistributions in binary form must reproduce the above copyright
  21. // notice, this list of conditions and the following disclaimer in the
  22. // documentation and/or other materials provided with the
  23. // distribution.
  24. //
  25. // Neither the name of Texas Instruments Incorporated nor the names of
  26. // its contributors may be used to endorse or promote products derived
  27. // from this software without specific prior written permission.
  28. //
  29. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32. // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33. // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34. // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35. // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36. // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37. // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38. // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39. // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. // $
  41. //###########################################################################
  42. #ifndef __HW_INTS_H__
  43. #define __HW_INTS_H__
  44. //*****************************************************************************
  45. //
  46. // PIE Interrupt Numbers
  47. //
  48. // 0x00FF = PIE Table Row #
  49. // 0xFF00 = PIE Table Column #
  50. // 0xFFFF0000 = PIE Vector ID
  51. //
  52. //*****************************************************************************
  53. // Lower PIE Group 1
  54. #define INT_ADCA_CH1 0x200101 //ADC-A Interrupt 1
  55. #define INT_ADCB_CH1 0x210102 //ADC-B Interrupt 1
  56. #define INT_ADCC_CH1 0x220103 //ADC-C Interrupt 1
  57. #define INT_XINT1 0x230104 //External Interrupt 1
  58. #define INT_XINT2 0x240105 //External Interrupt 2
  59. #define INT_ADCD_CH1 0x250106 //ADC-D Interrupt 1
  60. #define INT_TINT0 0x260107 //Timer Interrupt 0
  61. #define INT_WAKEINT 0x270108 //Wakeup Interrupt
  62. // Lower PIE Group 2
  63. #define INT_PWM1TZ 0x280201 //PWM TZ Interrupt 1
  64. #define INT_PWM2TZ 0x290202 //PWM TZ Interrupt 2
  65. #define INT_PWM3TZ 0x2A0203 //PWM TZ Interrupt 3
  66. #define INT_PWM4TZ 0x2B0204 //PWM TZ Interrupt 4
  67. #define INT_PWM5TZ 0x2C0205 //PWM TZ Interrupt 5
  68. #define INT_PWM6TZ 0x2D0206 //PWM TZ Interrupt 6
  69. #define INT_PWM7TZ 0x2E0207 //PWM TZ Interrupt 7
  70. #define INT_PWM8TZ 0x2F0208 //PWM TZ Interrupt 8
  71. // Lower PIE Group 3
  72. #define INT_PWM1INT 0x300301 //PWM Interrupt 1
  73. #define INT_PWM2INT 0x310302 //PWM Interrupt 2
  74. #define INT_PWM3INT 0x320303 //PWM Interrupt 3
  75. #define INT_PWM4INT 0x330304 //PWM Interrupt 4
  76. #define INT_PWM5INT 0x340305 //PWM Interrupt 5
  77. #define INT_PWM6INT 0x350306 //PWM Interrupt 6
  78. #define INT_PWM7INT 0x360307 //PWM Interrupt 7
  79. #define INT_PWM8INT 0x370308 //PWM Interrupt 8
  80. // Lower PIE Group 4
  81. #define INT_CAP1INT 0x380401 //Capture Interrupt 1
  82. #define INT_CAP2INT 0x390402 //Capture Interrupt 2
  83. #define INT_CAP3INT 0x3A0403 //Capture Interrupt 3
  84. #define INT_CAP4INT 0x3B0404 //Capture Interrupt 4
  85. #define INT_CAP5INT 0x3C0405 //Capture Interrupt 5
  86. #define INT_CAP6INT 0x3D0406 //Capture Interrupt 6
  87. #define INT_CAP7INT 0x3E0407 //Capture Interrupt 7
  88. #define INT_CAP8INT 0x3F0408 //Capture Interrupt 8
  89. // Lower PIE Group 5
  90. #define INT_EQEP1INT 0x400501 //Quadrature Interrupt 1
  91. #define INT_EQEP2INT 0x410502 //Quadrature Interrupt 2
  92. #define INT_EQEP3INT 0x420503 //Quadrature Interrupt 3
  93. #define INT_EQEP4INT 0x430504 //Quadrature Interrupt 4
  94. #define INT_CLB1INT 0x440505 //CLB Interrupt 1
  95. #define INT_CLB2INT 0x450506 //CLB Interrupt 2
  96. #define INT_CLB3INT 0x460507 //CLB Interrupt 3
  97. #define INT_CLB4INT 0x470508 //CLB Interrupt 4
  98. // Lower PIE Group 6
  99. #define INT_SPIRXINTA 0x480601 //SPI-A Receive Interrupt
  100. #define INT_SPITXINTA 0x490602 //SPI-A Transmit Interrupt
  101. #define INT_SPIRXINTB 0x4A0603 //SPI-B Receive Interrupt
  102. #define INT_SPITXINTB 0x4B0604 //SPI-B Transmit Interrupt
  103. #define INT_MRINTA 0x4C0605 //McBSP-A Receive Interrupt
  104. #define INT_MXINTA 0x4D0606 //McBSP-A Transmit Interrupt
  105. #define INT_MRINTB 0x4E0607 //McBSP-B Receive Interrupt
  106. #define INT_MXINTB 0x4F0608 //McBSP-B Transmit Interrupt
  107. // Lower PIE Group 7
  108. #define INT_DMA1INT 0x500701 //DMA Channel 1 Interrupt
  109. #define INT_DMA2INT 0x510702 //DMA Channel 2 Interrupt
  110. #define INT_DMA3INT 0x520703 //DMA Channel 3 Interrupt
  111. #define INT_DMA4INT 0x530704 //DMA Channel 4 Interrupt
  112. #define INT_DMA5INT 0x540705 //DMA Channel 5 Interrupt
  113. #define INT_DMA6INT 0x550706 //DMA Channel 6 Interrupt
  114. // Lower PIE Group 8
  115. #define INT_I2CINT1A 0x580801 //I2C-A Basic Interrupts
  116. #define INT_I2CINT2A 0x590802 //I2C-A FIFO Interrupts
  117. #define INT_I2CINT1B 0x5A0803 //I2C-B Basic Interrupts
  118. #define INT_I2CINT2B 0x5B0804 //I2C-B FIFO Interrupts
  119. #define INT_SCICRX 0x5C0805 //SCI-C Receive Interrupt
  120. #define INT_SCICTX 0x5D0806 //SCI-C Transmit Interrupt
  121. #define INT_SCIDRX 0x5E0807 //SCI-D Receive Interrupt
  122. #define INT_SCIDTX 0x5F0808 //SCI-D Transmit Interrupt
  123. // Lower PIE Group 9
  124. #define INT_SCIRXINTA 0x600901 //SCI-A RX Interrupt
  125. #define INT_SCITXINTA 0x610902 //SCI-A TX Interrupt
  126. #define INT_SCIRXINTB 0x620903 //SCI-B RX Interrupt
  127. #define INT_SCITXINTB 0x630904 //SCI-B TX Interrupt
  128. #define INT_CANA_0 0x640905 //CANA 0 Interrupt
  129. #define INT_CANA_1 0x650906 //CANA 1 Interrupt
  130. #define INT_CANB_0 0x660907 //CANB 0 Interrupt
  131. #define INT_CANB_1 0x670908 //CANB 1 Interrupt
  132. // Lower PIE Group 10
  133. #define INT_ADCA_EVT 0x680A01 //ADCA_EVT Interrupt
  134. #define INT_ADCA_CH2 0x690A02 //ADCA_CH2 Interrupt 2
  135. #define INT_ADCA_CH3 0x6A0A03 //ADCA_CH3 Interrupt 3
  136. #define INT_ADCA_CH4 0x6B0A04 //ADCA_CH4 Interrupt 4
  137. #define INT_ADCB_EVT 0x6C0A05 //ADCB_EVT Interrupt
  138. #define INT_ADCB_CH2 0x6D0A06 //ADCB_CH2 Interrupt 2
  139. #define INT_ADCB_CH3 0x6E0A07 //ADCB_CH3 Interrupt 3
  140. #define INT_ADCB_CH4 0x6F0A08 //ADCB_CH4 Interrupt 4
  141. // Lower PIE Group 11
  142. #define INT_CLA1INT1 0x700B01 //CLA_1 Interrupt 1
  143. #define INT_CLA1INT2 0x710B02 //CLA_1 Interrupt 2
  144. #define INT_CLA1INT3 0x720B03 //CLA_1 Interrupt 3
  145. #define INT_CLA1INT4 0x730B04 //CLA_1 Interrupt 4
  146. #define INT_CLA1INT5 0x740B05 //CLA_1 Interrupt 5
  147. #define INT_CLA1INT6 0x750B06 //CLA_1 Interrupt 6
  148. #define INT_CLA1INT7 0x760B07 //CLA_1 Interrupt 7
  149. #define INT_CLA1INT8 0x770B08 //CLA_1 Interrupt 8
  150. // Lower PIE Group 12
  151. #define INT_XINT3 0x780C01 //External Interrupt 3
  152. #define INT_XINT4 0x790C02 //External Interrupt 4
  153. #define INT_XINT5 0x7A0C03 //External Interrupt 5
  154. #define INT_FMC 0x7C0C05 //FMC Interrupt
  155. #define INT_VCU 0x7D0C06 //VCU Interrupt
  156. #define INT_LVF 0x7E0C07 //Latched Overflow
  157. #define INT_LUF 0x7F0C08 //Latched Underflow
  158. // Upper PIE Group 1
  159. #define INT_IPC0INT 0x84010D //IPC Interrupt 1
  160. #define INT_IPC1INT 0x85010E //IPC Interrupt 2
  161. #define INT_IPC2INT 0x86010F //IPC Interrupt 3
  162. #define INT_IPC3INT 0x870110 //IPC Interrupt 4
  163. // Upper PIE Group 2
  164. #define INT_PWM9TZ 0x880209 //PWM TZ Interrupt 9
  165. #define INT_PWM10TZ 0x89020A //PWM TZ Interrupt 10
  166. #define INT_PWM11TZ 0x8A020B //PWM TZ Interrupt 11
  167. #define INT_PWM12TZ 0x8B020C //PWM TZ Interrupt 12
  168. // Upper PIE Group 3
  169. #define INT_PWM9INT 0x900309 //PWM Interrupt 9
  170. #define INT_PWM10INT 0x91030A //PWN Interrupt 10
  171. #define INT_PWM11INT 0x92030B //PWM Interrupt 11
  172. #define INT_PWM12INT 0x93030C //PWM Interrupt 12
  173. // Upper PIE Group 4
  174. #define INT_HRCAP1INT 0x980409 //High-Res Capture Interrupt 1
  175. #define INT_HRCAP2INT 0x99040A //High-Res Capture Interrupt 2
  176. #define INT_HRCAP3INT 0x9A040B //High-Res Capture Interrupt 3
  177. #define INT_HRCAP4INT 0x9B040C //High-Res Capture Interrupt 4
  178. #define INT_HRCAP5INT 0x9C040D //High-Res Capture Interrupt 1
  179. #define INT_HRCAP6INT 0x9D040E //High-Res Capture Interrupt 2
  180. #define INT_HRCAP7INT 0x9E040F //High-Res Capture Interrupt 3
  181. #define INT_HRCAP8INT 0x9F0410 //High-Res Capture Interrupt 4
  182. // Upper PIE Group 5
  183. #define INT_SDFM1INT 0xA00509 //SDFM Interrupt 1
  184. #define INT_SDFM2INT 0xA1050A //SDFM Interrupt 2
  185. #define INT_SDFM3INT 0xA2050B //SDFM Interrupt 3
  186. #define INT_SDFM4INT 0xA3050C //SDFM Interrupt 4
  187. #define INT_SDFM5INT 0xA4050D //SDFM Interrupt 5
  188. #define INT_SDFM6INT 0xA5050E //SDFM Interrupt 6
  189. #define INT_SDFM7INT 0xA6050F //SDFM Interrupt 7
  190. #define INT_SDFM8INT 0xA70510 //SDFM Interrupt 8
  191. // Upper PIE Group 6
  192. #define INT_SPIRXINTC 0xA80609 //SPI-A Receive Interrupt
  193. #define INT_SPITXINTC 0xA9060A //SPI-A Transmit Interrupt
  194. #define INT_SPIRXINTD 0xAA060B //SPI-B Receive Interrupt
  195. #define INT_SPITXINTD 0xAB060C //SPI-B Transmit Interrupt
  196. // Upper PIE Group 8
  197. #define INT_UPPAINT 0xBE080F //UPP-A Interrupt
  198. #define INT_UPPBINT 0xBF0810 //UPP-B Interrupt
  199. // Upper PIE Group 9
  200. #define INT_CANCINT1 0xC00909 //CANC 1 Interrupt
  201. #define INT_CANCINT2 0xC1090A //CANC 2 Interrupt
  202. #define INT_CANDINT1 0xC2090B //CAND 1 Interrupt
  203. #define INT_CANDINT2 0xC3090C //CAND 2 Interrupt
  204. #define INT_USBAINT 0xC6090F //USBA Interrupt
  205. #define INT_USBBINT 0xC70910 //USBB Interrupt
  206. // Upper PIE Group 10
  207. #define INT_ADCC_EVT 0xC80A09 //ADCC_EVT Interrupt
  208. #define INT_ADCC_CH2 0xC90A0A //ADCC_CH2 Interrupt 2
  209. #define INT_ADCC_CH3 0xCA0A0B //ADCC_CH3 Interrupt 3
  210. #define INT_ADCC_CH4 0xCB0A0C //ADCC_CH4 Interrupt 4
  211. #define INT_ADCD_EVT 0xCC0A0D //ADCD_EVT Interrupt
  212. #define INT_ADCD_CH2 0xCD0A0E //ADCD_CH2 Interrupt 2
  213. #define INT_ADCD_CH3 0xCE0A0F //ADCD_CH3 Interrupt 3
  214. #define INT_ADCD_CH4 0xCF0A10 //ADCD_CH4 Interrupt 4
  215. // Upper PIE Group 11
  216. #define INT_CLA2INT1 0xD00B09 //CLA_2 Interrupt 1
  217. #define INT_CLA2INT2 0xD10B0A //CLA_2 Interrupt 2
  218. #define INT_CLA2INT3 0xD20B0B //CLA_2 Interrupt 3
  219. #define INT_CLA2INT4 0xD30B0C //CLA_2 Interrupt 4
  220. #define INT_CLA2INT5 0xD40B0D //CLA_2 Interrupt 1
  221. #define INT_CLA2INT6 0xD50B0E //CLA_2 Interrupt 2
  222. #define INT_CLA2INT7 0xD60B0F //CLA_2 Interrupt 3
  223. #define INT_CLA2INT8 0xD70B10 //CLA_2 Interrupt 4
  224. // Upper PIE Group 12
  225. #define INT_EMIF_ERR 0xD80C09 //EMIF Error Interrupt
  226. #define INT_RAM_CORR_ERR 0xD90C0A //RAM Correctable Error Interrupt
  227. #define INT_FLASH_CORR_ERR 0xDA0C0B //Flash correctable Error Interrupt
  228. #define INT_RAM_ACC_VIO 0xDB0C0C //RAM Access Violation Interrupt
  229. #define INT_SYS_PLL_SLIP 0xDC0C0D //System PLL Slip Interrupt
  230. #define INT_AUX_PLL_SLIP 0xDD0C0E //Auxillary PLL Slip Interrupt
  231. #define INT_CLA_OF 0xDE0C0F //CLA Overflow Interrupt
  232. #define INT_CLA_UF 0xDF0C10 //CLA Underflow Interrupt
  233. //Workaround for Stellaris code
  234. #define INT_USB0 INT_USBAINT // USB 0 Controller
  235. //Workaround for other interrupts
  236. #define INT_RESET 0x000000 //Reset Interrupt
  237. #define INT_INT1 0x010000 //Not Used
  238. #define INT_INT2 0x020000 //Not Used
  239. #define INT_INT3 0x030000 //Not Used
  240. #define INT_INT4 0x040000 //Not Used
  241. #define INT_INT5 0x050000 //Not Used
  242. #define INT_INT6 0x060000 //Not Used
  243. #define INT_INT7 0x070000 //Not Used
  244. #define INT_INT8 0x080000 //Not Used
  245. #define INT_INT9 0x090000 //Not Used
  246. #define INT_INT10 0x0A0000 //Not Used
  247. #define INT_INT11 0x0B0000 //Not Used
  248. #define INT_INT12 0x0C0000 //Not Used
  249. #define INT_TINT1 0x0D0D00 //Timer Interrupt 1
  250. #define INT_TINT2 0x0E0E00 //Timer Interrupt 2
  251. #define INT_DATALOG 0x0F0F00 //CPU Data Logging Interrupt
  252. #define INT_RTOSINT 0x101000 //CPU Real Time OS Interrupt
  253. #define INT_EMUINT 0x110000 //CPU Emulation Interrupt
  254. #define INT_NMI 0x120000 //External Non-Maskable Interrupt
  255. #define INT_ILLEGAL 0x130000 //Illegal Operation
  256. #define INT_USER1 0x140000 //User-defined
  257. #define INT_USER2 0x150000 //User-defined
  258. #define INT_USER3 0x160000 //User-defined
  259. #define INT_USER4 0x170000 //User-defined
  260. #define INT_USER5 0x180000 //User-defined
  261. #define INT_USER6 0x190000 //User-defined
  262. #define INT_USER7 0x1A0000 //User-defined
  263. #define INT_USER8 0x1B0000 //User-defined
  264. #define INT_USER9 0x1C0000 //User-defined
  265. #define INT_USER10 0x1D0000 //User-defined
  266. #define INT_USER11 0x1E0000 //User-defined
  267. #define INT_USER12 0x1F0000 //User-defined
  268. #endif // __HW_INTS_H__