drv_tim.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614
  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-10 zylx first version
  9. * 2020-06-16 thread-liu Porting for stm32mp1
  10. * 2020-08-25 linyongkang Fix the timer clock frequency doubling problem
  11. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  12. * 2020-11-18 leizhixiong add STM32H7 series support
  13. */
  14. #include <rtdevice.h>
  15. #include "drv_config.h"
  16. //#define DRV_DEBUG
  17. #define LOG_TAG "drv.tim"
  18. #include <drv_log.h>
  19. /* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
  20. void stm32_tim_pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
  21. {
  22. rt_uint32_t flatency = 0;
  23. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  24. RT_ASSERT(pclk1_doubler != RT_NULL);
  25. RT_ASSERT(pclk1_doubler != RT_NULL);
  26. HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
  27. *pclk1_doubler = 1;
  28. *pclk2_doubler = 1;
  29. #if defined(SOC_SERIES_STM32MP1)
  30. if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
  31. {
  32. *pclk1_doubler = 2;
  33. }
  34. if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
  35. {
  36. *pclk2_doubler = 2;
  37. }
  38. #else
  39. if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
  40. {
  41. *pclk1_doubler = 2;
  42. }
  43. #if !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0))
  44. if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
  45. {
  46. *pclk2_doubler = 2;
  47. }
  48. #endif
  49. #endif
  50. }
  51. #ifdef BSP_USING_TIM
  52. enum
  53. {
  54. #ifdef BSP_USING_TIM1
  55. TIM1_INDEX,
  56. #endif
  57. #ifdef BSP_USING_TIM2
  58. TIM2_INDEX,
  59. #endif
  60. #ifdef BSP_USING_TIM3
  61. TIM3_INDEX,
  62. #endif
  63. #ifdef BSP_USING_TIM4
  64. TIM4_INDEX,
  65. #endif
  66. #ifdef BSP_USING_TIM5
  67. TIM5_INDEX,
  68. #endif
  69. #ifdef BSP_USING_TIM6
  70. TIM6_INDEX,
  71. #endif
  72. #ifdef BSP_USING_TIM7
  73. TIM7_INDEX,
  74. #endif
  75. #ifdef BSP_USING_TIM8
  76. TIM8_INDEX,
  77. #endif
  78. #ifdef BSP_USING_TIM9
  79. TIM9_INDEX,
  80. #endif
  81. #ifdef BSP_USING_TIM10
  82. TIM10_INDEX,
  83. #endif
  84. #ifdef BSP_USING_TIM11
  85. TIM11_INDEX,
  86. #endif
  87. #ifdef BSP_USING_TIM12
  88. TIM12_INDEX,
  89. #endif
  90. #ifdef BSP_USING_TIM13
  91. TIM13_INDEX,
  92. #endif
  93. #ifdef BSP_USING_TIM14
  94. TIM14_INDEX,
  95. #endif
  96. #ifdef BSP_USING_TIM15
  97. TIM15_INDEX,
  98. #endif
  99. #ifdef BSP_USING_TIM16
  100. TIM16_INDEX,
  101. #endif
  102. #ifdef BSP_USING_TIM17
  103. TIM17_INDEX,
  104. #endif
  105. };
  106. struct stm32_hwtimer
  107. {
  108. rt_hwtimer_t time_device;
  109. TIM_HandleTypeDef tim_handle;
  110. IRQn_Type tim_irqn;
  111. char *name;
  112. };
  113. static struct stm32_hwtimer stm32_hwtimer_obj[] =
  114. {
  115. #ifdef BSP_USING_TIM1
  116. TIM1_CONFIG,
  117. #endif
  118. #ifdef BSP_USING_TIM2
  119. TIM2_CONFIG,
  120. #endif
  121. #ifdef BSP_USING_TIM3
  122. TIM3_CONFIG,
  123. #endif
  124. #ifdef BSP_USING_TIM4
  125. TIM4_CONFIG,
  126. #endif
  127. #ifdef BSP_USING_TIM5
  128. TIM5_CONFIG,
  129. #endif
  130. #ifdef BSP_USING_TIM6
  131. TIM6_CONFIG,
  132. #endif
  133. #ifdef BSP_USING_TIM7
  134. TIM7_CONFIG,
  135. #endif
  136. #ifdef BSP_USING_TIM8
  137. TIM8_CONFIG,
  138. #endif
  139. #ifdef BSP_USING_TIM9
  140. TIM9_CONFIG,
  141. #endif
  142. #ifdef BSP_USING_TIM10
  143. TIM10_CONFIG,
  144. #endif
  145. #ifdef BSP_USING_TIM11
  146. TIM11_CONFIG,
  147. #endif
  148. #ifdef BSP_USING_TIM12
  149. TIM12_CONFIG,
  150. #endif
  151. #ifdef BSP_USING_TIM13
  152. TIM13_CONFIG,
  153. #endif
  154. #ifdef BSP_USING_TIM14
  155. TIM14_CONFIG,
  156. #endif
  157. #ifdef BSP_USING_TIM15
  158. TIM15_CONFIG,
  159. #endif
  160. #ifdef BSP_USING_TIM16
  161. TIM16_CONFIG,
  162. #endif
  163. #ifdef BSP_USING_TIM17
  164. TIM17_CONFIG,
  165. #endif
  166. };
  167. static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
  168. {
  169. uint32_t prescaler_value = 0;
  170. uint32_t pclk1_doubler, pclk2_doubler;
  171. TIM_HandleTypeDef *tim = RT_NULL;
  172. struct stm32_hwtimer *tim_device = RT_NULL;
  173. RT_ASSERT(timer != RT_NULL);
  174. if (state)
  175. {
  176. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  177. tim_device = (struct stm32_hwtimer *)timer;
  178. stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  179. /* time init */
  180. /* Some series may only have APBPERIPH_BASE, don't have HAL_RCC_GetPCLK2Freq */
  181. #if defined(APBPERIPH_BASE)
  182. prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
  183. #elif defined(APB1PERIPH_BASE) || defined(APB2PERIPH_BASE)
  184. if ((rt_uint32_t)tim->Instance >= APB2PERIPH_BASE)
  185. {
  186. prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler / 10000) - 1;
  187. }
  188. else
  189. {
  190. prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
  191. }
  192. #endif
  193. tim->Init.Period = 10000 - 1;
  194. tim->Init.Prescaler = prescaler_value;
  195. tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  196. if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
  197. {
  198. tim->Init.CounterMode = TIM_COUNTERMODE_UP;
  199. }
  200. else
  201. {
  202. tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
  203. }
  204. tim->Init.RepetitionCounter = 0;
  205. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
  206. tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  207. #endif
  208. if (HAL_TIM_Base_Init(tim) != HAL_OK)
  209. {
  210. LOG_E("%s init failed", tim_device->name);
  211. return;
  212. }
  213. else
  214. {
  215. /* set the TIMx priority */
  216. HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0);
  217. /* enable the TIMx global Interrupt */
  218. HAL_NVIC_EnableIRQ(tim_device->tim_irqn);
  219. /* clear update flag */
  220. __HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE);
  221. /* enable update request source */
  222. __HAL_TIM_URS_ENABLE(tim);
  223. LOG_D("%s init success", tim_device->name);
  224. }
  225. }
  226. }
  227. static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
  228. {
  229. rt_err_t result = RT_EOK;
  230. TIM_HandleTypeDef *tim = RT_NULL;
  231. RT_ASSERT(timer != RT_NULL);
  232. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  233. /* set tim cnt */
  234. __HAL_TIM_SET_COUNTER(tim, 0);
  235. /* set tim arr */
  236. __HAL_TIM_SET_AUTORELOAD(tim, t - 1);
  237. if (opmode == HWTIMER_MODE_ONESHOT)
  238. {
  239. /* set timer to single mode */
  240. tim->Instance->CR1 |= TIM_OPMODE_SINGLE;
  241. }
  242. else
  243. {
  244. tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
  245. }
  246. /* start timer */
  247. if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
  248. {
  249. LOG_E("TIM start failed");
  250. result = -RT_ERROR;
  251. }
  252. return result;
  253. }
  254. static void timer_stop(rt_hwtimer_t *timer)
  255. {
  256. TIM_HandleTypeDef *tim = RT_NULL;
  257. RT_ASSERT(timer != RT_NULL);
  258. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  259. /* stop timer */
  260. HAL_TIM_Base_Stop_IT(tim);
  261. /* set tim cnt */
  262. __HAL_TIM_SET_COUNTER(tim, 0);
  263. }
  264. static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
  265. {
  266. TIM_HandleTypeDef *tim = RT_NULL;
  267. rt_err_t result = -RT_ERROR;
  268. uint32_t pclk1_doubler, pclk2_doubler;
  269. RT_ASSERT(timer != RT_NULL);
  270. RT_ASSERT(arg != RT_NULL);
  271. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  272. switch (cmd)
  273. {
  274. case HWTIMER_CTRL_FREQ_SET:
  275. {
  276. rt_uint32_t freq;
  277. rt_uint16_t val;
  278. /* set timer frequence */
  279. freq = *((rt_uint32_t *)arg);
  280. stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  281. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  282. if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
  283. #elif defined(SOC_SERIES_STM32L4)
  284. if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
  285. #elif defined(SOC_SERIES_STM32WB)
  286. if (tim->Instance == TIM16 || tim->Instance == TIM17)
  287. #elif defined(SOC_SERIES_STM32MP1)
  288. if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
  289. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7)
  290. if (0)
  291. #else
  292. #error "This driver has not supported this series yet!"
  293. #endif
  294. {
  295. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  296. val = HAL_RCC_GetPCLK2Freq() * pclk2_doubler / freq;
  297. #endif
  298. }
  299. else
  300. {
  301. val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq;
  302. }
  303. __HAL_TIM_SET_PRESCALER(tim, val - 1);
  304. /* Update frequency value */
  305. tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
  306. result = RT_EOK;
  307. }
  308. break;
  309. default:
  310. {
  311. result = -RT_EINVAL;
  312. }
  313. break;
  314. }
  315. return result;
  316. }
  317. static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
  318. {
  319. TIM_HandleTypeDef *tim = RT_NULL;
  320. RT_ASSERT(timer != RT_NULL);
  321. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  322. return tim->Instance->CNT;
  323. }
  324. static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
  325. static const struct rt_hwtimer_ops _ops =
  326. {
  327. .init = timer_init,
  328. .start = timer_start,
  329. .stop = timer_stop,
  330. .count_get = timer_counter_get,
  331. .control = timer_ctrl,
  332. };
  333. #ifdef BSP_USING_TIM2
  334. void TIM2_IRQHandler(void)
  335. {
  336. /* enter interrupt */
  337. rt_interrupt_enter();
  338. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle);
  339. /* leave interrupt */
  340. rt_interrupt_leave();
  341. }
  342. #endif
  343. #ifdef BSP_USING_TIM3
  344. void TIM3_IRQHandler(void)
  345. {
  346. /* enter interrupt */
  347. rt_interrupt_enter();
  348. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
  349. /* leave interrupt */
  350. rt_interrupt_leave();
  351. }
  352. #endif
  353. #ifdef BSP_USING_TIM4
  354. void TIM4_IRQHandler(void)
  355. {
  356. /* enter interrupt */
  357. rt_interrupt_enter();
  358. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
  359. /* leave interrupt */
  360. rt_interrupt_leave();
  361. }
  362. #endif
  363. #ifdef BSP_USING_TIM5
  364. void TIM5_IRQHandler(void)
  365. {
  366. /* enter interrupt */
  367. rt_interrupt_enter();
  368. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle);
  369. /* leave interrupt */
  370. rt_interrupt_leave();
  371. }
  372. #endif
  373. #ifdef BSP_USING_TIM7
  374. void TIM7_IRQHandler(void)
  375. {
  376. /* enter interrupt */
  377. rt_interrupt_enter();
  378. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM7_INDEX].tim_handle);
  379. /* leave interrupt */
  380. rt_interrupt_leave();
  381. }
  382. #endif
  383. #ifdef BSP_USING_TIM11
  384. void TIM1_TRG_COM_TIM11_IRQHandler(void)
  385. {
  386. /* enter interrupt */
  387. rt_interrupt_enter();
  388. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle);
  389. /* leave interrupt */
  390. rt_interrupt_leave();
  391. }
  392. #endif
  393. #ifdef BSP_USING_TIM13
  394. void TIM8_UP_TIM13_IRQHandler(void)
  395. {
  396. /* enter interrupt */
  397. rt_interrupt_enter();
  398. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle);
  399. /* leave interrupt */
  400. rt_interrupt_leave();
  401. }
  402. #endif
  403. #ifdef BSP_USING_TIM14
  404. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  405. void TIM8_TRG_COM_TIM14_IRQHandler(void)
  406. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
  407. void TIM14_IRQHandler(void)
  408. #endif
  409. {
  410. /* enter interrupt */
  411. rt_interrupt_enter();
  412. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle);
  413. /* leave interrupt */
  414. rt_interrupt_leave();
  415. }
  416. #endif
  417. #ifdef BSP_USING_TIM15
  418. void TIM1_BRK_TIM15_IRQHandler(void)
  419. {
  420. /* enter interrupt */
  421. rt_interrupt_enter();
  422. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle);
  423. /* leave interrupt */
  424. rt_interrupt_leave();
  425. }
  426. #endif
  427. #ifdef BSP_USING_TIM16
  428. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
  429. void TIM1_UP_TIM16_IRQHandler(void)
  430. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
  431. void TIM16_IRQHandler(void)
  432. #endif
  433. {
  434. /* enter interrupt */
  435. rt_interrupt_enter();
  436. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle);
  437. /* leave interrupt */
  438. rt_interrupt_leave();
  439. }
  440. #endif
  441. #ifdef BSP_USING_TIM17
  442. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
  443. void TIM1_TRG_COM_TIM17_IRQHandler(void)
  444. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
  445. void TIM17_IRQHandler(void)
  446. #endif
  447. {
  448. /* enter interrupt */
  449. rt_interrupt_enter();
  450. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle);
  451. /* leave interrupt */
  452. rt_interrupt_leave();
  453. }
  454. #endif
  455. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  456. {
  457. #ifdef BSP_USING_TIM2
  458. if (htim->Instance == TIM2)
  459. {
  460. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device);
  461. }
  462. #endif
  463. #ifdef BSP_USING_TIM3
  464. if (htim->Instance == TIM3)
  465. {
  466. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device);
  467. }
  468. #endif
  469. #ifdef BSP_USING_TIM4
  470. if (htim->Instance == TIM4)
  471. {
  472. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device);
  473. }
  474. #endif
  475. #ifdef BSP_USING_TIM5
  476. if (htim->Instance == TIM5)
  477. {
  478. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device);
  479. }
  480. #endif
  481. #ifdef BSP_USING_TIM7
  482. if (htim->Instance == TIM7)
  483. {
  484. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM7_INDEX].time_device);
  485. }
  486. #endif
  487. #ifdef BSP_USING_TIM11
  488. if (htim->Instance == TIM11)
  489. {
  490. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device);
  491. }
  492. #endif
  493. #ifdef BSP_USING_TIM13
  494. if (htim->Instance == TIM13)
  495. {
  496. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device);
  497. }
  498. #endif
  499. #ifdef BSP_USING_TIM14
  500. if (htim->Instance == TIM14)
  501. {
  502. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device);
  503. }
  504. #endif
  505. #ifdef BSP_USING_TIM15
  506. if (htim->Instance == TIM15)
  507. {
  508. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device);
  509. }
  510. #endif
  511. #ifdef BSP_USING_TIM16
  512. if (htim->Instance == TIM16)
  513. {
  514. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device);
  515. }
  516. #endif
  517. #ifdef BSP_USING_TIM17
  518. if (htim->Instance == TIM17)
  519. {
  520. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device);
  521. }
  522. #endif
  523. }
  524. static int stm32_hwtimer_init(void)
  525. {
  526. int i = 0;
  527. int result = RT_EOK;
  528. for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++)
  529. {
  530. stm32_hwtimer_obj[i].time_device.info = &_info;
  531. stm32_hwtimer_obj[i].time_device.ops = &_ops;
  532. if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device,
  533. stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK)
  534. {
  535. LOG_D("%s register success", stm32_hwtimer_obj[i].name);
  536. }
  537. else
  538. {
  539. LOG_E("%s register failed", stm32_hwtimer_obj[i].name);
  540. result = -RT_ERROR;
  541. }
  542. }
  543. return result;
  544. }
  545. INIT_BOARD_EXPORT(stm32_hwtimer_init);
  546. #endif /* BSP_USING_TIM */