serial.c 12 KB

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  1. /*
  2. * File : serial.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2013, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2013-07-06 Bernard the first version
  13. * 2014-01-11 RTsien add definitions of UART0 to UART5
  14. */
  15. #include <rthw.h>
  16. #include <rtthread.h>
  17. #include <rtdevice.h>
  18. #include <am33xx.h>
  19. #include <interrupt.h>
  20. #include "serial.h"
  21. #include "serial_reg.h"
  22. struct am33xx_uart
  23. {
  24. unsigned long base;
  25. int irq;
  26. };
  27. static void am33xx_uart_isr(int irqno, void* param)
  28. {
  29. rt_uint32_t iir;
  30. struct am33xx_uart* uart;
  31. struct rt_serial_device *serial;
  32. serial = (struct rt_serial_device*)param;
  33. uart = (struct am33xx_uart *)serial->parent.user_data;
  34. iir = UART_IIR_REG(uart->base);
  35. if ((iir & (0x02 << 1)) || (iir & (0x6 << 1)))
  36. {
  37. rt_hw_serial_isr(serial);
  38. }
  39. }
  40. #define NOT_IMPLEMENTED() RT_ASSERT(0)
  41. static rt_err_t am33xx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  42. {
  43. struct am33xx_uart* uart;
  44. unsigned long base;
  45. RT_ASSERT(serial != RT_NULL);
  46. uart = (struct am33xx_uart *)serial->parent.user_data;
  47. RT_ASSERT(uart);
  48. base = uart->base;
  49. #define __LCR UART_LCR_REG(base)
  50. if (cfg->data_bits == DATA_BITS_8)
  51. __LCR |= 3;
  52. else
  53. NOT_IMPLEMENTED();
  54. if (cfg->stop_bits == STOP_BITS_1)
  55. __LCR &= ~(1<<2);
  56. else
  57. __LCR |= (1<<2);
  58. if (cfg->parity == PARITY_NONE)
  59. __LCR &= ~(1<<3);
  60. else
  61. __LCR |= (1<<3);
  62. __LCR |= (1<<7);
  63. if (cfg->baud_rate == BAUD_RATE_115200)
  64. {
  65. UART_DLL_REG(base) = 26;
  66. UART_DLH_REG(base) = 0;
  67. }
  68. else
  69. {
  70. NOT_IMPLEMENTED();
  71. }
  72. __LCR &= ~(1<<7);
  73. UART_MDR1_REG(base) = 0;
  74. UART_MDR2_REG(base) = 0;
  75. #undef __LCR
  76. return RT_EOK;
  77. }
  78. static rt_err_t am33xx_control(struct rt_serial_device *serial, int cmd, void *arg)
  79. {
  80. struct am33xx_uart* uart;
  81. RT_ASSERT(serial != RT_NULL);
  82. uart = (struct am33xx_uart *)serial->parent.user_data;
  83. switch (cmd)
  84. {
  85. case RT_DEVICE_CTRL_CLR_INT:
  86. /* disable rx irq */
  87. rt_hw_interrupt_mask(uart->irq);
  88. break;
  89. case RT_DEVICE_CTRL_SET_INT:
  90. /* enable rx irq */
  91. rt_hw_interrupt_umask(uart->irq);
  92. break;
  93. }
  94. return RT_EOK;
  95. }
  96. int printkc(char c)
  97. {
  98. int base = 0xf9e09000;
  99. while (!(UART_LSR_REG(base) & 0x20));
  100. UART_THR_REG(base) = c;
  101. return 1;
  102. }
  103. static int am33xx_putc(struct rt_serial_device *serial, char c)
  104. {
  105. struct am33xx_uart* uart;
  106. RT_ASSERT(serial != RT_NULL);
  107. uart = (struct am33xx_uart *)serial->parent.user_data;
  108. while (!(UART_LSR_REG(uart->base) & 0x20));
  109. UART_THR_REG(uart->base) = c;
  110. return 1;
  111. }
  112. static int am33xx_getc(struct rt_serial_device *serial)
  113. {
  114. int ch;
  115. struct am33xx_uart* uart;
  116. RT_ASSERT(serial != RT_NULL);
  117. uart = (struct am33xx_uart *)serial->parent.user_data;
  118. ch = -1;
  119. if (UART_LSR_REG(uart->base) & 0x01)
  120. {
  121. ch = UART_RHR_REG(uart->base) & 0xff;
  122. }
  123. return ch;
  124. }
  125. static const struct rt_uart_ops am33xx_uart_ops =
  126. {
  127. am33xx_configure,
  128. am33xx_control,
  129. am33xx_putc,
  130. am33xx_getc,
  131. };
  132. /* UART device driver structure */
  133. struct serial_ringbuffer uart_int_rx[6];
  134. struct am33xx_uart uart[6] =
  135. {
  136. {UART0_BASE,UART0_INT},
  137. {UART1_BASE,UART1_INT},
  138. {UART2_BASE,UART2_INT},
  139. {UART3_BASE,UART3_INT},
  140. {UART4_BASE,UART4_INT},
  141. {UART5_BASE,UART5_INT}
  142. };
  143. struct rt_serial_device serial[6];
  144. #define write_reg(base, value) *(int*)(base) = value
  145. #define read_reg(base) *(int*)(base)
  146. #define PRM_PER_INTRANSLATION (1 << 20)
  147. #define PRM_PER_POWSTATEOFF (0)
  148. #define PRM_PER_PERMEMSTATEOFF (0)
  149. static void poweron_per_domain(void)
  150. {
  151. unsigned long prcm_base;
  152. unsigned long prm_state;
  153. prcm_base = AM33XX_PRCM_REGS;
  154. /* wait for ongoing translations */
  155. for (prm_state = PRM_PER_PWRSTST_REG(prcm_base);
  156. prm_state & PRM_PER_INTRANSLATION;
  157. prm_state = PRM_PER_PWRSTST_REG(prcm_base))
  158. ;
  159. /* check power state */
  160. if ((prm_state & 0x03) == PRM_PER_POWSTATEOFF)
  161. /* power on PER domain */
  162. PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3;
  163. /* check per mem state */
  164. if ((prm_state & 0x03) == PRM_PER_PERMEMSTATEOFF)
  165. /* power on PER domain */
  166. PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3 << 25;
  167. while (PRM_PER_PWRSTST_REG(prcm_base) & PRM_PER_INTRANSLATION)
  168. ;
  169. }
  170. static void start_uart_clk(void)
  171. {
  172. unsigned long prcm_base;
  173. prcm_base = AM33XX_PRCM_REGS;
  174. /* software forced wakeup */
  175. CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2;
  176. /* Waiting for the L4LS clock */
  177. while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
  178. ;
  179. /* enable uart1 */
  180. #ifdef RT_USING_UART1
  181. CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2;
  182. /* wait for uart1 clk */
  183. while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
  184. ;
  185. #endif
  186. #ifdef RT_USING_UART2
  187. CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2;
  188. /* wait for uart2 clk */
  189. while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
  190. ;
  191. #endif
  192. #ifdef RT_USING_UART3
  193. CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2;
  194. /* wait for uart3 clk */
  195. while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
  196. ;
  197. #endif
  198. #ifdef RT_USING_UART4
  199. CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2;
  200. /* wait for uart4 clk */
  201. while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
  202. ;
  203. #endif
  204. #ifdef RT_USING_UART5
  205. CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2;
  206. /* wait for uart5 clk */
  207. while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
  208. ;
  209. #endif
  210. /* Waiting for the L4LS UART clock */
  211. while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10)))
  212. ;
  213. }
  214. static void config_pinmux(void)
  215. {
  216. unsigned long ctlm_base;
  217. ctlm_base = AM33XX_CTLM_REGS;
  218. /* make sure the pin mux is OK for uart */
  219. #ifdef RT_USING_UART1
  220. REG32(ctlm_base + 0x800 + 0x180) = 0x20;
  221. REG32(ctlm_base + 0x800 + 0x184) = 0x00;
  222. #endif
  223. #ifdef RT_USING_UART2
  224. REG32(ctlm_base + 0x800 + 0x150) = 0x20;
  225. REG32(ctlm_base + 0x800 + 0x154) = 0x00;
  226. #endif
  227. #ifdef RT_USING_UART3
  228. REG32(ctlm_base + 0x800 + 0x164) = 0x01;
  229. #endif
  230. #ifdef RT_USING_UART4
  231. REG32(ctlm_base + 0x800 + 0x070) = 0x26;
  232. REG32(ctlm_base + 0x800 + 0x074) = 0x06;
  233. #endif
  234. #ifdef RT_USING_UART5
  235. REG32(ctlm_base + 0x800 + 0x0C4) = 0x24;
  236. REG32(ctlm_base + 0x800 + 0x0C0) = 0x04;
  237. #endif
  238. }
  239. int rt_hw_serial_init(void)
  240. {
  241. struct serial_configure config[6];
  242. poweron_per_domain();
  243. start_uart_clk();
  244. config_pinmux();
  245. #ifdef RT_USING_UART0
  246. config[0].baud_rate = BAUD_RATE_115200;
  247. config[0].bit_order = BIT_ORDER_LSB;
  248. config[0].data_bits = DATA_BITS_8;
  249. config[0].parity = PARITY_NONE;
  250. config[0].stop_bits = STOP_BITS_1;
  251. config[0].invert = NRZ_NORMAL;
  252. serial[0].ops = &am33xx_uart_ops;
  253. serial[0].int_rx = &uart_int_rx[0];
  254. serial[0].config = config[0];
  255. /* enable RX interrupt */
  256. UART_IER_REG(uart[0].base) = 0x01;
  257. /* install ISR */
  258. rt_hw_interrupt_install(uart[0].irq, am33xx_uart_isr, &serial[0], "uart0");
  259. rt_hw_interrupt_control(uart[0].irq, 0, 0);
  260. rt_hw_interrupt_mask(uart[0].irq);
  261. /* register UART0 device */
  262. rt_hw_serial_register(&serial[0], "uart0",
  263. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
  264. &uart[0]);
  265. #endif
  266. #ifdef RT_USING_UART1
  267. config[1].baud_rate = BAUD_RATE_115200;
  268. config[1].bit_order = BIT_ORDER_LSB;
  269. config[1].data_bits = DATA_BITS_8;
  270. config[1].parity = PARITY_NONE;
  271. config[1].stop_bits = STOP_BITS_1;
  272. config[1].invert = NRZ_NORMAL;
  273. serial[1].ops = &am33xx_uart_ops;
  274. serial[1].int_rx = &uart_int_rx[1];
  275. serial[1].config = config[1];
  276. /* enable RX interrupt */
  277. UART_IER_REG(uart[1].base) = 0x01;
  278. /* install ISR */
  279. rt_hw_interrupt_install(uart[1].irq, am33xx_uart_isr, &serial[1], "uart1");
  280. rt_hw_interrupt_control(uart[1].irq, 0, 0);
  281. rt_hw_interrupt_mask(uart[1].irq);
  282. /* register UART0 device */
  283. rt_hw_serial_register(&serial[1], "uart1",
  284. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
  285. &uart[1]);
  286. #endif
  287. #ifdef RT_USING_UART2
  288. config[2].baud_rate = BAUD_RATE_115200;
  289. config[2].bit_order = BIT_ORDER_LSB;
  290. config[2].data_bits = DATA_BITS_8;
  291. config[2].parity = PARITY_NONE;
  292. config[2].stop_bits = STOP_BITS_1;
  293. config[2].invert = NRZ_NORMAL;
  294. serial[2].ops = &am33xx_uart_ops;
  295. serial[2].int_rx = &uart_int_rx[2];
  296. serial[2].config = config[2];
  297. /* enable RX interrupt */
  298. UART_IER_REG(uart[2].base) = 0x01;
  299. /* install ISR */
  300. rt_hw_interrupt_install(uart[2].irq, am33xx_uart_isr, &serial[2], "uart2");
  301. rt_hw_interrupt_control(uart[2].irq, 0, 0);
  302. rt_hw_interrupt_mask(uart[2].irq);
  303. /* register UART2 device */
  304. rt_hw_serial_register(&serial[2], "uart2",
  305. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
  306. &uart[2]);
  307. #endif
  308. #ifdef RT_USING_UART3
  309. config[3].baud_rate = BAUD_RATE_115200;
  310. config[3].bit_order = BIT_ORDER_LSB;
  311. config[3].data_bits = DATA_BITS_8;
  312. config[3].parity = PARITY_NONE;
  313. config[3].stop_bits = STOP_BITS_1;
  314. config[3].invert = NRZ_NORMAL;
  315. serial[3].ops = &am33xx_uart_ops;
  316. serial[3].int_rx = &uart_int_rx[3];
  317. serial[3].config = config[3];
  318. /* enable RX interrupt */
  319. UART_IER_REG(uart[3].base) = 0x01;
  320. /* install ISR */
  321. rt_hw_interrupt_install(uart[3].irq, am33xx_uart_isr, &serial[3], "uart3");
  322. rt_hw_interrupt_control(uart[3].irq, 0, 0);
  323. rt_hw_interrupt_mask(uart[3].irq);
  324. /* register UART3 device */
  325. rt_hw_serial_register(&serial[3], "uart3",
  326. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
  327. &uart[3]);
  328. #endif
  329. #ifdef RT_USING_UART4
  330. config[4].baud_rate = BAUD_RATE_115200;
  331. config[4].bit_order = BIT_ORDER_LSB;
  332. config[4].data_bits = DATA_BITS_8;
  333. config[4].parity = PARITY_NONE;
  334. config[4].stop_bits = STOP_BITS_1;
  335. config[4].invert = NRZ_NORMAL;
  336. serial[4].ops = &am33xx_uart_ops;
  337. serial[4].int_rx = &uart_int_rx[4];
  338. serial[4].config = config[4];
  339. /* enable RX interrupt */
  340. UART_IER_REG(uart[4].base) = 0x01;
  341. /* install ISR */
  342. rt_hw_interrupt_install(uart[4].irq, am33xx_uart_isr, &serial[4], "uart4");
  343. rt_hw_interrupt_control(uart[4].irq, 0, 0);
  344. rt_hw_interrupt_mask(uart[4].irq);
  345. /* register UART4 device */
  346. rt_hw_serial_register(&serial[4], "uart4",
  347. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
  348. &uart[4]);
  349. #endif
  350. #ifdef RT_USING_UART5
  351. config[5].baud_rate = BAUD_RATE_115200;
  352. config[5].bit_order = BIT_ORDER_LSB;
  353. config[5].data_bits = DATA_BITS_8;
  354. config[5].parity = PARITY_NONE;
  355. config[5].stop_bits = STOP_BITS_1;
  356. config[5].invert = NRZ_NORMAL;
  357. serial[5].ops = &am33xx_uart_ops;
  358. serial[5].int_rx = &uart_int_rx[5];
  359. serial[5].config = config[5];
  360. /* enable RX interrupt */
  361. UART_IER_REG(uart[5].base) = 0x01;
  362. /* install ISR */
  363. rt_hw_interrupt_install(uart[5].irq, am33xx_uart_isr, &serial[5], "uart5");
  364. rt_hw_interrupt_control(uart[5].irq, 0, 0);
  365. rt_hw_interrupt_mask(uart[5].irq);
  366. /* register UART4 device */
  367. rt_hw_serial_register(&serial[5], "uart5",
  368. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
  369. &uart[5]);
  370. #endif
  371. return 0;
  372. }
  373. INIT_BOARD_EXPORT(rt_hw_serial_init);