drv_spi.c 8.7 KB

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  1. /*
  2. * Copyright (c) 2006-2020, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-06-22 bigmagic first version
  9. */
  10. #include <rtthread.h>
  11. #include <rthw.h>
  12. #include <rtdevice.h>
  13. #include "raspi4.h"
  14. #include "drv_spi.h"
  15. #ifdef RT_USING_SPI
  16. #define RPI_CORE_CLK_HZ (250000000)
  17. #define BSP_SPI_MAX_HZ (30* 1000 *1000)
  18. #define SPITIMEOUT 0x0FFF
  19. static rt_uint8_t raspi_byte_reverse_table[] =
  20. {
  21. 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
  22. 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
  23. 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
  24. 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
  25. 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
  26. 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
  27. 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
  28. 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
  29. 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
  30. 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
  31. 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
  32. 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
  33. 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
  34. 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
  35. 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
  36. 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
  37. 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
  38. 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
  39. 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
  40. 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
  41. 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
  42. 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
  43. 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
  44. 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
  45. 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
  46. 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
  47. 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
  48. 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
  49. 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
  50. 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
  51. 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
  52. 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
  53. };
  54. #if defined (BSP_USING_SPI0_BUS)
  55. #define SPI0_BUS_NAME "spi0"
  56. #define SPI0_DEVICE0_NAME "spi0.0"
  57. #define SPI0_DEVICE1_NAME "spi0.1"
  58. struct rt_spi_bus spi0_bus;
  59. #if defined (BSP_USING_SPI0_DEVICE0)
  60. static struct rt_spi_device spi0_device0;
  61. #endif
  62. #if defined (BSP_USING_SPI0_DEVICE1)
  63. static struct rt_spi_device spi0_device1;
  64. #endif
  65. #endif
  66. static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
  67. {
  68. RT_ASSERT(cfg != RT_NULL);
  69. RT_ASSERT(device != RT_NULL);
  70. rt_uint16_t divider;
  71. struct raspi_spi_device* hw_config = (struct raspi_spi_device *)(device->parent.user_data);
  72. struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config;
  73. // spi clear fifo
  74. SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
  75. if(cfg->mode & RT_SPI_CPOL)
  76. {
  77. SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPOL;
  78. }
  79. if(cfg->mode & RT_SPI_CPHA)
  80. {
  81. SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPHA;
  82. }
  83. if(cfg->mode & RT_SPI_CS_HIGH)
  84. {
  85. SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH;
  86. }
  87. //set clk
  88. if (cfg->max_hz > BSP_SPI_MAX_HZ)
  89. cfg->max_hz = BSP_SPI_MAX_HZ;
  90. divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz);
  91. divider &= 0xFFFE;
  92. SPI_REG_CLK(hwcfg->hw_base) = divider;
  93. return RT_EOK;
  94. }
  95. rt_uint8_t correct_order(rt_uint8_t b, rt_uint8_t flag)
  96. {
  97. if (flag)
  98. return raspi_byte_reverse_table[b];//reverse
  99. else
  100. return b;
  101. }
  102. static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len, rt_uint8_t flag)
  103. {
  104. rt_uint32_t TXCnt=0;
  105. rt_uint32_t RXCnt=0;
  106. /* Clear TX and RX fifos */
  107. SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
  108. /* Set TA = 1 */
  109. SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA;
  110. /* Use the FIFO's to reduce the interbyte times */
  111. while ((TXCnt < len) || (RXCnt < len))
  112. {
  113. /* TX fifo not full, so add some more bytes */
  114. while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_TX_DATA)) && (TXCnt < len))
  115. {
  116. SPI_REG_FIFO(hwcfg->hw_base) = correct_order(tbuf[TXCnt],flag);
  117. TXCnt++;
  118. }
  119. /* Rx fifo not empty, so get the next received bytes */
  120. while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_RX_DATA)) && (RXCnt < len))
  121. {
  122. rbuf[RXCnt] = correct_order(SPI_REG_FIFO(hwcfg->hw_base), flag);
  123. RXCnt++;
  124. }
  125. }
  126. /* Wait for DONE to be set */
  127. while (!(SPI_REG_CS(hwcfg->hw_base) & SPI_CS_DONE));
  128. /* Set TA = 0, and also set the barrier */
  129. SPI_REG_CS(hwcfg->hw_base) |= (0 & SPI_CS_TA);
  130. return RT_EOK;
  131. }
  132. static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
  133. {
  134. rt_err_t res;
  135. rt_uint8_t flag;
  136. RT_ASSERT(device != RT_NULL);
  137. RT_ASSERT(device->bus != RT_NULL);
  138. RT_ASSERT(device->parent.user_data != RT_NULL);
  139. RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
  140. struct rt_spi_configuration config = device->config;
  141. struct raspi_spi_device * hw_config = (struct raspi_spi_device *)device->parent.user_data;
  142. GPIO_PIN cs_pin = (GPIO_PIN)hw_config->cs_pin;
  143. struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config;
  144. if (config.mode & RT_SPI_MSB)
  145. {
  146. flag = 0;
  147. }
  148. else
  149. {
  150. flag = 1;
  151. }
  152. if (message->cs_take)
  153. {
  154. (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 1):prev_raspi_pin_write(cs_pin, 0);
  155. }
  156. res = spi_transfernb(hwcfg, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, flag);
  157. if (message->cs_release)
  158. {
  159. (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 0):prev_raspi_pin_write(cs_pin, 1);
  160. }
  161. if (res != RT_EOK)
  162. return RT_ERROR;
  163. return message->length;
  164. }
  165. rt_err_t raspi_spi_bus_attach_device(const char *bus_name, struct raspi_spi_device *device)
  166. {
  167. rt_err_t ret;
  168. RT_ASSERT(device != RT_NULL);
  169. ret = rt_spi_bus_attach_device(device->spi_device, device->device_name, bus_name, (void *)(device));
  170. return ret;
  171. }
  172. rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg)
  173. {
  174. prev_raspi_pin_mode(hwcfg->sclk_pin, hwcfg->sclk_mode);
  175. prev_raspi_pin_mode(hwcfg->miso_pin, hwcfg->miso_mode);
  176. prev_raspi_pin_mode(hwcfg->mosi_pin, hwcfg->mosi_mode);
  177. #if defined (BSP_USING_SPI0_DEVICE0)
  178. prev_raspi_pin_mode(hwcfg->ce0_pin, hwcfg->ce0_mode);
  179. #endif
  180. #if defined (BSP_USING_SPI0_DEVICE1)
  181. prev_raspi_pin_mode(hwcfg->ce1_pin, hwcfg->ce1_mode);
  182. #endif
  183. //clear rx and tx
  184. SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
  185. //enable chip select
  186. #if defined (BSP_USING_SPI0_DEVICE0)
  187. SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_0;
  188. #endif
  189. #if defined (BSP_USING_SPI0_DEVICE1)
  190. SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1;
  191. #endif
  192. #if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1)
  193. HWREG32(SPI_REG_CS(hwcfg->hw_base)) |= (SPI_CS_CHIP_SELECT_0 | SPI_CS_CHIP_SELECT_1);
  194. #endif
  195. return RT_EOK;
  196. }
  197. static struct rt_spi_ops raspi_spi_ops =
  198. {
  199. .configure = raspi_spi_configure,
  200. .xfer = raspi_spi_xfer
  201. };
  202. struct raspi_spi_hw_config raspi_spi0_hw =
  203. {
  204. .spi_num = 0,
  205. .sclk_pin = GPIO_PIN_11,
  206. .sclk_mode = ALT0,
  207. .mosi_pin = GPIO_PIN_10,
  208. .mosi_mode = ALT0,
  209. .miso_pin = GPIO_PIN_9,
  210. .miso_mode = ALT0,
  211. #if defined (BSP_USING_SPI0_DEVICE0)
  212. .ce0_pin = GPIO_PIN_8,
  213. .ce0_mode = ALT0,
  214. #endif
  215. #if defined (BSP_USING_SPI0_DEVICE1)
  216. .ce1_pin = GPIO_PIN_7,
  217. .ce1_mode = ALT0,
  218. #endif
  219. .hw_base = SPI_0_BASE,
  220. };
  221. #endif
  222. #if defined (BSP_USING_SPI0_DEVICE0)
  223. struct raspi_spi_device raspi_spi0_device0 =
  224. {
  225. .device_name = SPI0_DEVICE0_NAME,
  226. .spi_bus = &spi0_bus,
  227. .spi_device = &spi0_device0,
  228. .spi_hw_config = &raspi_spi0_hw,
  229. .cs_pin = GPIO_PIN_8,
  230. };
  231. #endif
  232. #if defined (BSP_USING_SPI0_DEVICE1)
  233. struct raspi_spi_device raspi_spi0_device1 =
  234. {
  235. .device_name = SPI0_DEVICE1_NAME,
  236. .spi_bus = &spi0_bus,
  237. .spi_device = &spi0_device1,
  238. .cs_pin = GPIO_PIN_7,
  239. };
  240. #endif
  241. int rt_hw_spi_init(void)
  242. {
  243. #if defined (BSP_USING_SPI0_BUS)
  244. raspi_spi_hw_init(&raspi_spi0_hw);
  245. rt_spi_bus_register(&spi0_bus, SPI0_BUS_NAME, &raspi_spi_ops);
  246. #if defined (BSP_USING_SPI0_DEVICE0)
  247. raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device0);
  248. #endif
  249. #if defined (BSP_USING_SPI0_DEVICE1)
  250. raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device1);
  251. #endif
  252. #endif
  253. return RT_EOK;
  254. }
  255. INIT_DEVICE_EXPORT(rt_hw_spi_init);