imx6ul.h 2.4 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-03-22 quanzhao first version
  9. */
  10. #ifndef __IMX6UL_H__
  11. #define __IMX6UL_H__
  12. #include <rthw.h>
  13. #include <rtthread.h>
  14. /* SOC-relative definitions */
  15. //#include "realview.h"
  16. #include "gic_registers.h"
  17. #include "irq_numbers.h"
  18. /* the maximum number of gic */
  19. # define ARM_GIC_MAX_NR 1
  20. /* the maximum number of interrupts */
  21. #define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT
  22. /* the maximum entries of the interrupt table */
  23. #define MAX_HANDLERS IMX_INTERRUPT_COUNT
  24. /* the basic constants needed by gic */
  25. rt_inline rt_uint32_t platform_get_gic_dist_base(void)
  26. {
  27. rt_uint32_t gic_base;
  28. asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
  29. return gic_base + kGICDBaseOffset;
  30. }
  31. rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
  32. {
  33. rt_uint32_t gic_base;
  34. asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
  35. return gic_base + kGICCBaseOffset;
  36. }
  37. #define GIC_IRQ_START 0
  38. #define GIC_ACK_INTID_MASK 0x000003ff
  39. /* the definition needed by gic.c */
  40. #define __REG32(x) (*((volatile unsigned int *)(x)))
  41. /* keep compatible with platform SDK */
  42. typedef enum {
  43. CPU_0,
  44. CPU_1,
  45. CPU_2,
  46. CPU_3,
  47. } cpuid_e;
  48. enum _gicd_sgi_filter
  49. {
  50. //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
  51. kGicSgiFilter_UseTargetList = 0,
  52. //! Forward the interrupt to all CPU interfaces except that of the processor that requested
  53. //! the interrupt.
  54. kGicSgiFilter_AllOtherCPUs = 1,
  55. //! Forward the interrupt only to the CPU interface of the processor that requested the
  56. //! interrupt.
  57. kGicSgiFilter_OnlyThisCPU = 2
  58. };
  59. typedef void (*irq_hdlr_t) (void);
  60. extern void rt_hw_interrupt_mask(int vector);
  61. extern void rt_hw_interrupt_umask(int vector);
  62. extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
  63. void *param, const char *name);
  64. rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
  65. {
  66. rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
  67. }
  68. rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
  69. {
  70. rt_hw_interrupt_umask(irq_id);
  71. }
  72. rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
  73. {
  74. rt_hw_interrupt_mask(irq_id);
  75. }
  76. #endif /* __IMX6UL_H__ */