cpuport.c 6.4 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018/10/28 Bernard The unify RISC-V porting code.
  9. * 2020/11/20 BalanceTWK Add FPU support
  10. * 2023/01/04 WangShun Adapt to CH32
  11. */
  12. #include <rthw.h>
  13. #include <rtthread.h>
  14. #include "cpuport.h"
  15. #ifndef RT_USING_SMP
  16. volatile rt_ubase_t rt_interrupt_from_thread = 0;
  17. volatile rt_ubase_t rt_interrupt_to_thread = 0;
  18. volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
  19. #endif
  20. struct rt_hw_stack_frame
  21. {
  22. rt_ubase_t epc; /* epc - epc - program counter */
  23. rt_ubase_t ra; /* x1 - ra - return address for jumps */
  24. rt_ubase_t mstatus; /* - machine status register */
  25. rt_ubase_t gp; /* x3 - gp - global pointer */
  26. rt_ubase_t tp; /* x4 - tp - thread pointer */
  27. rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
  28. rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
  29. rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
  30. rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
  31. rt_ubase_t s1; /* x9 - s1 - saved register 1 */
  32. rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
  33. rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
  34. rt_ubase_t a2; /* x12 - a2 - function argument 2 */
  35. rt_ubase_t a3; /* x13 - a3 - function argument 3 */
  36. rt_ubase_t a4; /* x14 - a4 - function argument 4 */
  37. rt_ubase_t a5; /* x15 - a5 - function argument 5 */
  38. rt_ubase_t a6; /* x16 - a6 - function argument 6 */
  39. rt_ubase_t a7; /* x17 - s7 - function argument 7 */
  40. rt_ubase_t s2; /* x18 - s2 - saved register 2 */
  41. rt_ubase_t s3; /* x19 - s3 - saved register 3 */
  42. rt_ubase_t s4; /* x20 - s4 - saved register 4 */
  43. rt_ubase_t s5; /* x21 - s5 - saved register 5 */
  44. rt_ubase_t s6; /* x22 - s6 - saved register 6 */
  45. rt_ubase_t s7; /* x23 - s7 - saved register 7 */
  46. rt_ubase_t s8; /* x24 - s8 - saved register 8 */
  47. rt_ubase_t s9; /* x25 - s9 - saved register 9 */
  48. rt_ubase_t s10; /* x26 - s10 - saved register 10 */
  49. rt_ubase_t s11; /* x27 - s11 - saved register 11 */
  50. rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
  51. rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
  52. rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
  53. rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
  54. #ifdef ARCH_RISCV_FPU
  55. rv_floatreg_t f0; /* f0 */
  56. rv_floatreg_t f1; /* f1 */
  57. rv_floatreg_t f2; /* f2 */
  58. rv_floatreg_t f3; /* f3 */
  59. rv_floatreg_t f4; /* f4 */
  60. rv_floatreg_t f5; /* f5 */
  61. rv_floatreg_t f6; /* f6 */
  62. rv_floatreg_t f7; /* f7 */
  63. rv_floatreg_t f8; /* f8 */
  64. rv_floatreg_t f9; /* f9 */
  65. rv_floatreg_t f10; /* f10 */
  66. rv_floatreg_t f11; /* f11 */
  67. rv_floatreg_t f12; /* f12 */
  68. rv_floatreg_t f13; /* f13 */
  69. rv_floatreg_t f14; /* f14 */
  70. rv_floatreg_t f15; /* f15 */
  71. rv_floatreg_t f16; /* f16 */
  72. rv_floatreg_t f17; /* f17 */
  73. rv_floatreg_t f18; /* f18 */
  74. rv_floatreg_t f19; /* f19 */
  75. rv_floatreg_t f20; /* f20 */
  76. rv_floatreg_t f21; /* f21 */
  77. rv_floatreg_t f22; /* f22 */
  78. rv_floatreg_t f23; /* f23 */
  79. rv_floatreg_t f24; /* f24 */
  80. rv_floatreg_t f25; /* f25 */
  81. rv_floatreg_t f26; /* f26 */
  82. rv_floatreg_t f27; /* f27 */
  83. rv_floatreg_t f28; /* f28 */
  84. rv_floatreg_t f29; /* f29 */
  85. rv_floatreg_t f30; /* f30 */
  86. rv_floatreg_t f31; /* f31 */
  87. #endif
  88. };
  89. /**
  90. * This function will initialize thread stack
  91. *
  92. * @param tentry the entry of thread
  93. * @param parameter the parameter of entry
  94. * @param stack_addr the beginning stack address
  95. * @param texit the function will be called when thread exit
  96. *
  97. * @return stack address
  98. */
  99. rt_uint8_t *rt_hw_stack_init(void *tentry,
  100. void *parameter,
  101. rt_uint8_t *stack_addr,
  102. void *texit)
  103. {
  104. struct rt_hw_stack_frame *frame;
  105. rt_uint8_t *stk;
  106. int i;
  107. stk = stack_addr + sizeof(rt_ubase_t);
  108. stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
  109. stk -= sizeof(struct rt_hw_stack_frame);
  110. frame = (struct rt_hw_stack_frame *)stk;
  111. for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
  112. {
  113. ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
  114. }
  115. frame->ra = (rt_ubase_t)texit;
  116. frame->a0 = (rt_ubase_t)parameter;
  117. frame->epc = (rt_ubase_t)tentry;
  118. /* force to machine mode(MPP=11) and set MPIE to 1 */
  119. #ifdef ARCH_RISCV_FPU
  120. frame->mstatus = 0x00007880;
  121. #else
  122. frame->mstatus = 0x00001880;
  123. #endif
  124. return stk;
  125. }
  126. /*
  127. * #ifdef RT_USING_SMP
  128. * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
  129. * #else
  130. * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
  131. * #endif
  132. */
  133. #ifndef RT_USING_SMP
  134. rt_weak void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)
  135. {
  136. if (rt_thread_switch_interrupt_flag == 0)
  137. rt_interrupt_from_thread = from;
  138. rt_interrupt_to_thread = to;
  139. rt_thread_switch_interrupt_flag = 1;
  140. #if defined(SOC_RISCV_FAMILY_CH32)
  141. sw_setpend();
  142. #endif
  143. return ;
  144. }
  145. #endif /* end of RT_USING_SMP */
  146. /** shutdown CPU */
  147. rt_weak void rt_hw_cpu_shutdown()
  148. {
  149. rt_base_t level;
  150. rt_kprintf("shutdown...\n");
  151. level = rt_hw_interrupt_disable();
  152. while (level)
  153. {
  154. RT_ASSERT(0);
  155. }
  156. }