gh_efuse.h 21 KB

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  1. /*!
  2. *******************************************************************************
  3. **
  4. ** \file gh_efuse.h
  5. **
  6. ** \brief EFUSE controller.
  7. **
  8. ** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
  9. **
  10. ** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
  11. ** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
  12. ** OMMISSIONS.
  13. **
  14. ** \note Do not modify this file as it is generated automatically.
  15. **
  16. ******************************************************************************/
  17. #ifndef _GH_EFUSE_H
  18. #define _GH_EFUSE_H
  19. #ifdef __LINUX__
  20. #include "reg4linux.h"
  21. #else
  22. #define FIO_ADDRESS(block,address) (address)
  23. #define FIO_MOFFSET(block,moffset) (moffset)
  24. #endif
  25. #ifndef __LINUX__
  26. #include "gtypes.h" /* global type definitions */
  27. #include "gh_lib_cfg.h" /* configuration */
  28. #endif
  29. #define GH_EFUSE_ENABLE_DEBUG_PRINT 0
  30. #ifdef __LINUX__
  31. #define GH_EFUSE_DEBUG_PRINT_FUNCTION printk
  32. #else
  33. #define GH_EFUSE_DEBUG_PRINT_FUNCTION printf
  34. #endif
  35. #ifndef __LINUX__
  36. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  37. #include <stdio.h>
  38. #endif
  39. #endif
  40. /* check configuration */
  41. #ifndef GH_INLINE_LEVEL
  42. #error "GH_INLINE_LEVEL is not defined!"
  43. #endif
  44. #if GH_INLINE_LEVEL > 2
  45. #error "GH_INLINE_LEVEL must be set 0, 1 or 2!"
  46. #endif
  47. #ifndef GH_INLINE
  48. #error "GH_INLINE is not defined!"
  49. #endif
  50. /* disable inlining for debugging */
  51. #ifdef DEBUG
  52. #undef GH_INLINE_LEVEL
  53. #define GH_INLINE_LEVEL 0
  54. #endif
  55. /*----------------------------------------------------------------------------*/
  56. /* registers */
  57. /*----------------------------------------------------------------------------*/
  58. #define REG_EFUSE_KEY FIO_ADDRESS(EFUSE,0x90001000) /* read */
  59. #define REG_EFUSE_DATA FIO_ADDRESS(EFUSE,0x90001010) /* read */
  60. #define REG_EFUSE_USER_DATA FIO_ADDRESS(EFUSE,0x90001014) /* read */
  61. #define REG_EFUSE_CTRL FIO_ADDRESS(EFUSE,0x90001100) /* read/write */
  62. #define REG_EFUSE_BOOT FIO_ADDRESS(EFUSE,0x90001104) /* read/write */
  63. /*----------------------------------------------------------------------------*/
  64. /* bit group structures */
  65. /*----------------------------------------------------------------------------*/
  66. typedef union { /* EFUSE_Data */
  67. U32 all;
  68. struct {
  69. U32 boot_mode_sel : 1;
  70. U32 engine_sel : 1;
  71. U32 user_data : 30;
  72. } bitc;
  73. } GH_EFUSE_DATA_S;
  74. typedef union { /* EFUSE_CTRL */
  75. U32 all;
  76. struct {
  77. U32 wr_progen_high_cnt : 9;
  78. U32 wr_progen_low_cnt : 6;
  79. U32 wr_addr_setup_cnt : 4;
  80. U32 rd_addr_setup_cnt : 3;
  81. U32 rd_prchg_setup_cnt : 2;
  82. U32 rd_prchg_hold_cnt : 2;
  83. U32 rd_sense_hold_cnt : 3;
  84. U32 wait_rd_addr_update_cnt : 3;
  85. } bitc;
  86. } GH_EFUSE_CTRL_S;
  87. typedef union { /* EFUSE_BOOT */
  88. U32 all;
  89. struct {
  90. U32 en : 1;
  91. U32 rd_ok : 1;
  92. U32 : 30;
  93. } bitc;
  94. } GH_EFUSE_BOOT_S;
  95. /*----------------------------------------------------------------------------*/
  96. /* mirror variables */
  97. /*----------------------------------------------------------------------------*/
  98. #ifdef __cplusplus
  99. extern "C" {
  100. #endif
  101. /*----------------------------------------------------------------------------*/
  102. /* register EFUSE_KEY (read) */
  103. /*----------------------------------------------------------------------------*/
  104. #if GH_INLINE_LEVEL == 0
  105. /*! \brief Reads the register 'EFUSE_KEY'. */
  106. U32 GH_EFUSE_get_KEY(U8 index);
  107. #else /* GH_INLINE_LEVEL == 0 */
  108. GH_INLINE U32 GH_EFUSE_get_KEY(U8 index)
  109. {
  110. U32 value = (*(volatile U32 *)(REG_EFUSE_KEY + index * FIO_MOFFSET(EFUSE,0x00000004)));
  111. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  112. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_KEY] --> 0x%08x\n",
  113. (REG_EFUSE_KEY + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
  114. #endif
  115. return value;
  116. }
  117. #endif /* GH_INLINE_LEVEL == 0 */
  118. /*----------------------------------------------------------------------------*/
  119. /* register EFUSE_Data (read) */
  120. /*----------------------------------------------------------------------------*/
  121. #if GH_INLINE_LEVEL == 0
  122. /*! \brief Reads the register 'EFUSE_Data'. */
  123. U32 GH_EFUSE_get_Data(U8 index);
  124. /*! \brief Reads the bit group 'boot_mode_sel' of register 'EFUSE_Data'. */
  125. U8 GH_EFUSE_get_Data_boot_mode_sel(U8 index);
  126. /*! \brief Reads the bit group 'engine_sel' of register 'EFUSE_Data'. */
  127. U8 GH_EFUSE_get_Data_engine_sel(U8 index);
  128. /*! \brief Reads the bit group 'User_Data' of register 'EFUSE_Data'. */
  129. U32 GH_EFUSE_get_Data_User_Data(U8 index);
  130. #else /* GH_INLINE_LEVEL == 0 */
  131. GH_INLINE U32 GH_EFUSE_get_Data(U8 index)
  132. {
  133. U32 value = (*(volatile U32 *)(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
  134. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  135. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_Data] --> 0x%08x\n",
  136. (REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
  137. #endif
  138. return value;
  139. }
  140. GH_INLINE U8 GH_EFUSE_get_Data_boot_mode_sel(U8 index)
  141. {
  142. GH_EFUSE_DATA_S tmp_value;
  143. U32 value = (*(volatile U32 *)(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
  144. tmp_value.all = value;
  145. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  146. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_Data_boot_mode_sel] --> 0x%08x\n",
  147. (REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
  148. #endif
  149. return tmp_value.bitc.boot_mode_sel;
  150. }
  151. GH_INLINE U8 GH_EFUSE_get_Data_engine_sel(U8 index)
  152. {
  153. GH_EFUSE_DATA_S tmp_value;
  154. U32 value = (*(volatile U32 *)(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
  155. tmp_value.all = value;
  156. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  157. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_Data_engine_sel] --> 0x%08x\n",
  158. (REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
  159. #endif
  160. return tmp_value.bitc.engine_sel;
  161. }
  162. GH_INLINE U32 GH_EFUSE_get_Data_User_Data(U8 index)
  163. {
  164. GH_EFUSE_DATA_S tmp_value;
  165. U32 value = (*(volatile U32 *)(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
  166. tmp_value.all = value;
  167. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  168. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_Data_User_Data] --> 0x%08x\n",
  169. (REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
  170. #endif
  171. return tmp_value.bitc.user_data;
  172. }
  173. #endif /* GH_INLINE_LEVEL == 0 */
  174. /*----------------------------------------------------------------------------*/
  175. /* register EFUSE_User_Data (read) */
  176. /*----------------------------------------------------------------------------*/
  177. #if GH_INLINE_LEVEL == 0
  178. /*! \brief Reads the register 'EFUSE_User_Data'. */
  179. U32 GH_EFUSE_get_User_Data(U8 index);
  180. #else /* GH_INLINE_LEVEL == 0 */
  181. GH_INLINE U32 GH_EFUSE_get_User_Data(U8 index)
  182. {
  183. U32 value = (*(volatile U32 *)(REG_EFUSE_USER_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
  184. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  185. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_User_Data] --> 0x%08x\n",
  186. (REG_EFUSE_USER_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
  187. #endif
  188. return value;
  189. }
  190. #endif /* GH_INLINE_LEVEL == 0 */
  191. /*----------------------------------------------------------------------------*/
  192. /* register EFUSE_CTRL (read/write) */
  193. /*----------------------------------------------------------------------------*/
  194. #if GH_INLINE_LEVEL == 0
  195. /*! \brief Writes the register 'EFUSE_CTRL'. */
  196. void GH_EFUSE_set_CTRL(U32 data);
  197. /*! \brief Reads the register 'EFUSE_CTRL'. */
  198. U32 GH_EFUSE_get_CTRL(void);
  199. /*! \brief Writes the bit group 'wr_progen_high_cnt' of register 'EFUSE_CTRL'. */
  200. void GH_EFUSE_set_CTRL_wr_progen_high_cnt(U16 data);
  201. /*! \brief Reads the bit group 'wr_progen_high_cnt' of register 'EFUSE_CTRL'. */
  202. U16 GH_EFUSE_get_CTRL_wr_progen_high_cnt(void);
  203. /*! \brief Writes the bit group 'wr_progen_low_cnt' of register 'EFUSE_CTRL'. */
  204. void GH_EFUSE_set_CTRL_wr_progen_low_cnt(U8 data);
  205. /*! \brief Reads the bit group 'wr_progen_low_cnt' of register 'EFUSE_CTRL'. */
  206. U8 GH_EFUSE_get_CTRL_wr_progen_low_cnt(void);
  207. /*! \brief Writes the bit group 'wr_addr_setup_cnt' of register 'EFUSE_CTRL'. */
  208. void GH_EFUSE_set_CTRL_wr_addr_setup_cnt(U8 data);
  209. /*! \brief Reads the bit group 'wr_addr_setup_cnt' of register 'EFUSE_CTRL'. */
  210. U8 GH_EFUSE_get_CTRL_wr_addr_setup_cnt(void);
  211. /*! \brief Writes the bit group 'rd_addr_setup_cnt' of register 'EFUSE_CTRL'. */
  212. void GH_EFUSE_set_CTRL_rd_addr_setup_cnt(U8 data);
  213. /*! \brief Reads the bit group 'rd_addr_setup_cnt' of register 'EFUSE_CTRL'. */
  214. U8 GH_EFUSE_get_CTRL_rd_addr_setup_cnt(void);
  215. /*! \brief Writes the bit group 'rd_prchg_setup_cnt' of register 'EFUSE_CTRL'. */
  216. void GH_EFUSE_set_CTRL_rd_prchg_setup_cnt(U8 data);
  217. /*! \brief Reads the bit group 'rd_prchg_setup_cnt' of register 'EFUSE_CTRL'. */
  218. U8 GH_EFUSE_get_CTRL_rd_prchg_setup_cnt(void);
  219. /*! \brief Writes the bit group 'rd_prchg_hold_cnt' of register 'EFUSE_CTRL'. */
  220. void GH_EFUSE_set_CTRL_rd_prchg_hold_cnt(U8 data);
  221. /*! \brief Reads the bit group 'rd_prchg_hold_cnt' of register 'EFUSE_CTRL'. */
  222. U8 GH_EFUSE_get_CTRL_rd_prchg_hold_cnt(void);
  223. /*! \brief Writes the bit group 'rd_sense_hold_cnt' of register 'EFUSE_CTRL'. */
  224. void GH_EFUSE_set_CTRL_rd_sense_hold_cnt(U8 data);
  225. /*! \brief Reads the bit group 'rd_sense_hold_cnt' of register 'EFUSE_CTRL'. */
  226. U8 GH_EFUSE_get_CTRL_rd_sense_hold_cnt(void);
  227. /*! \brief Writes the bit group 'Wait_rd_addr_update_cnt' of register 'EFUSE_CTRL'. */
  228. void GH_EFUSE_set_CTRL_Wait_rd_addr_update_cnt(U8 data);
  229. /*! \brief Reads the bit group 'Wait_rd_addr_update_cnt' of register 'EFUSE_CTRL'. */
  230. U8 GH_EFUSE_get_CTRL_Wait_rd_addr_update_cnt(void);
  231. #else /* GH_INLINE_LEVEL == 0 */
  232. GH_INLINE void GH_EFUSE_set_CTRL(U32 data)
  233. {
  234. *(volatile U32 *)REG_EFUSE_CTRL = data;
  235. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  236. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL] <-- 0x%08x\n",
  237. REG_EFUSE_CTRL,data,data);
  238. #endif
  239. }
  240. GH_INLINE U32 GH_EFUSE_get_CTRL(void)
  241. {
  242. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  243. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  244. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL] --> 0x%08x\n",
  245. REG_EFUSE_CTRL,value);
  246. #endif
  247. return value;
  248. }
  249. GH_INLINE void GH_EFUSE_set_CTRL_wr_progen_high_cnt(U16 data)
  250. {
  251. GH_EFUSE_CTRL_S d;
  252. d.all = *(volatile U32 *)REG_EFUSE_CTRL;
  253. d.bitc.wr_progen_high_cnt = data;
  254. *(volatile U32 *)REG_EFUSE_CTRL = d.all;
  255. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  256. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_wr_progen_high_cnt] <-- 0x%08x\n",
  257. REG_EFUSE_CTRL,d.all,d.all);
  258. #endif
  259. }
  260. GH_INLINE U16 GH_EFUSE_get_CTRL_wr_progen_high_cnt(void)
  261. {
  262. GH_EFUSE_CTRL_S tmp_value;
  263. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  264. tmp_value.all = value;
  265. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  266. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_wr_progen_high_cnt] --> 0x%08x\n",
  267. REG_EFUSE_CTRL,value);
  268. #endif
  269. return tmp_value.bitc.wr_progen_high_cnt;
  270. }
  271. GH_INLINE void GH_EFUSE_set_CTRL_wr_progen_low_cnt(U8 data)
  272. {
  273. GH_EFUSE_CTRL_S d;
  274. d.all = *(volatile U32 *)REG_EFUSE_CTRL;
  275. d.bitc.wr_progen_low_cnt = data;
  276. *(volatile U32 *)REG_EFUSE_CTRL = d.all;
  277. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  278. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_wr_progen_low_cnt] <-- 0x%08x\n",
  279. REG_EFUSE_CTRL,d.all,d.all);
  280. #endif
  281. }
  282. GH_INLINE U8 GH_EFUSE_get_CTRL_wr_progen_low_cnt(void)
  283. {
  284. GH_EFUSE_CTRL_S tmp_value;
  285. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  286. tmp_value.all = value;
  287. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  288. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_wr_progen_low_cnt] --> 0x%08x\n",
  289. REG_EFUSE_CTRL,value);
  290. #endif
  291. return tmp_value.bitc.wr_progen_low_cnt;
  292. }
  293. GH_INLINE void GH_EFUSE_set_CTRL_wr_addr_setup_cnt(U8 data)
  294. {
  295. GH_EFUSE_CTRL_S d;
  296. d.all = *(volatile U32 *)REG_EFUSE_CTRL;
  297. d.bitc.wr_addr_setup_cnt = data;
  298. *(volatile U32 *)REG_EFUSE_CTRL = d.all;
  299. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  300. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_wr_addr_setup_cnt] <-- 0x%08x\n",
  301. REG_EFUSE_CTRL,d.all,d.all);
  302. #endif
  303. }
  304. GH_INLINE U8 GH_EFUSE_get_CTRL_wr_addr_setup_cnt(void)
  305. {
  306. GH_EFUSE_CTRL_S tmp_value;
  307. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  308. tmp_value.all = value;
  309. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  310. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_wr_addr_setup_cnt] --> 0x%08x\n",
  311. REG_EFUSE_CTRL,value);
  312. #endif
  313. return tmp_value.bitc.wr_addr_setup_cnt;
  314. }
  315. GH_INLINE void GH_EFUSE_set_CTRL_rd_addr_setup_cnt(U8 data)
  316. {
  317. GH_EFUSE_CTRL_S d;
  318. d.all = *(volatile U32 *)REG_EFUSE_CTRL;
  319. d.bitc.rd_addr_setup_cnt = data;
  320. *(volatile U32 *)REG_EFUSE_CTRL = d.all;
  321. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  322. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_rd_addr_setup_cnt] <-- 0x%08x\n",
  323. REG_EFUSE_CTRL,d.all,d.all);
  324. #endif
  325. }
  326. GH_INLINE U8 GH_EFUSE_get_CTRL_rd_addr_setup_cnt(void)
  327. {
  328. GH_EFUSE_CTRL_S tmp_value;
  329. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  330. tmp_value.all = value;
  331. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  332. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_rd_addr_setup_cnt] --> 0x%08x\n",
  333. REG_EFUSE_CTRL,value);
  334. #endif
  335. return tmp_value.bitc.rd_addr_setup_cnt;
  336. }
  337. GH_INLINE void GH_EFUSE_set_CTRL_rd_prchg_setup_cnt(U8 data)
  338. {
  339. GH_EFUSE_CTRL_S d;
  340. d.all = *(volatile U32 *)REG_EFUSE_CTRL;
  341. d.bitc.rd_prchg_setup_cnt = data;
  342. *(volatile U32 *)REG_EFUSE_CTRL = d.all;
  343. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  344. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_rd_prchg_setup_cnt] <-- 0x%08x\n",
  345. REG_EFUSE_CTRL,d.all,d.all);
  346. #endif
  347. }
  348. GH_INLINE U8 GH_EFUSE_get_CTRL_rd_prchg_setup_cnt(void)
  349. {
  350. GH_EFUSE_CTRL_S tmp_value;
  351. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  352. tmp_value.all = value;
  353. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  354. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_rd_prchg_setup_cnt] --> 0x%08x\n",
  355. REG_EFUSE_CTRL,value);
  356. #endif
  357. return tmp_value.bitc.rd_prchg_setup_cnt;
  358. }
  359. GH_INLINE void GH_EFUSE_set_CTRL_rd_prchg_hold_cnt(U8 data)
  360. {
  361. GH_EFUSE_CTRL_S d;
  362. d.all = *(volatile U32 *)REG_EFUSE_CTRL;
  363. d.bitc.rd_prchg_hold_cnt = data;
  364. *(volatile U32 *)REG_EFUSE_CTRL = d.all;
  365. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  366. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_rd_prchg_hold_cnt] <-- 0x%08x\n",
  367. REG_EFUSE_CTRL,d.all,d.all);
  368. #endif
  369. }
  370. GH_INLINE U8 GH_EFUSE_get_CTRL_rd_prchg_hold_cnt(void)
  371. {
  372. GH_EFUSE_CTRL_S tmp_value;
  373. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  374. tmp_value.all = value;
  375. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  376. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_rd_prchg_hold_cnt] --> 0x%08x\n",
  377. REG_EFUSE_CTRL,value);
  378. #endif
  379. return tmp_value.bitc.rd_prchg_hold_cnt;
  380. }
  381. GH_INLINE void GH_EFUSE_set_CTRL_rd_sense_hold_cnt(U8 data)
  382. {
  383. GH_EFUSE_CTRL_S d;
  384. d.all = *(volatile U32 *)REG_EFUSE_CTRL;
  385. d.bitc.rd_sense_hold_cnt = data;
  386. *(volatile U32 *)REG_EFUSE_CTRL = d.all;
  387. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  388. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_rd_sense_hold_cnt] <-- 0x%08x\n",
  389. REG_EFUSE_CTRL,d.all,d.all);
  390. #endif
  391. }
  392. GH_INLINE U8 GH_EFUSE_get_CTRL_rd_sense_hold_cnt(void)
  393. {
  394. GH_EFUSE_CTRL_S tmp_value;
  395. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  396. tmp_value.all = value;
  397. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  398. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_rd_sense_hold_cnt] --> 0x%08x\n",
  399. REG_EFUSE_CTRL,value);
  400. #endif
  401. return tmp_value.bitc.rd_sense_hold_cnt;
  402. }
  403. GH_INLINE void GH_EFUSE_set_CTRL_Wait_rd_addr_update_cnt(U8 data)
  404. {
  405. GH_EFUSE_CTRL_S d;
  406. d.all = *(volatile U32 *)REG_EFUSE_CTRL;
  407. d.bitc.wait_rd_addr_update_cnt = data;
  408. *(volatile U32 *)REG_EFUSE_CTRL = d.all;
  409. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  410. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_Wait_rd_addr_update_cnt] <-- 0x%08x\n",
  411. REG_EFUSE_CTRL,d.all,d.all);
  412. #endif
  413. }
  414. GH_INLINE U8 GH_EFUSE_get_CTRL_Wait_rd_addr_update_cnt(void)
  415. {
  416. GH_EFUSE_CTRL_S tmp_value;
  417. U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
  418. tmp_value.all = value;
  419. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  420. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_Wait_rd_addr_update_cnt] --> 0x%08x\n",
  421. REG_EFUSE_CTRL,value);
  422. #endif
  423. return tmp_value.bitc.wait_rd_addr_update_cnt;
  424. }
  425. #endif /* GH_INLINE_LEVEL == 0 */
  426. /*----------------------------------------------------------------------------*/
  427. /* register EFUSE_BOOT (read/write) */
  428. /*----------------------------------------------------------------------------*/
  429. #if GH_INLINE_LEVEL == 0
  430. /*! \brief Writes the register 'EFUSE_BOOT'. */
  431. void GH_EFUSE_set_BOOT(U32 data);
  432. /*! \brief Reads the register 'EFUSE_BOOT'. */
  433. U32 GH_EFUSE_get_BOOT(void);
  434. /*! \brief Writes the bit group 'EN' of register 'EFUSE_BOOT'. */
  435. void GH_EFUSE_set_BOOT_EN(U8 data);
  436. /*! \brief Reads the bit group 'EN' of register 'EFUSE_BOOT'. */
  437. U8 GH_EFUSE_get_BOOT_EN(void);
  438. /*! \brief Writes the bit group 'RD_OK' of register 'EFUSE_BOOT'. */
  439. void GH_EFUSE_set_BOOT_RD_OK(U8 data);
  440. /*! \brief Reads the bit group 'RD_OK' of register 'EFUSE_BOOT'. */
  441. U8 GH_EFUSE_get_BOOT_RD_OK(void);
  442. #else /* GH_INLINE_LEVEL == 0 */
  443. GH_INLINE void GH_EFUSE_set_BOOT(U32 data)
  444. {
  445. *(volatile U32 *)REG_EFUSE_BOOT = data;
  446. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  447. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_BOOT] <-- 0x%08x\n",
  448. REG_EFUSE_BOOT,data,data);
  449. #endif
  450. }
  451. GH_INLINE U32 GH_EFUSE_get_BOOT(void)
  452. {
  453. U32 value = (*(volatile U32 *)REG_EFUSE_BOOT);
  454. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  455. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_BOOT] --> 0x%08x\n",
  456. REG_EFUSE_BOOT,value);
  457. #endif
  458. return value;
  459. }
  460. GH_INLINE void GH_EFUSE_set_BOOT_EN(U8 data)
  461. {
  462. GH_EFUSE_BOOT_S d;
  463. d.all = *(volatile U32 *)REG_EFUSE_BOOT;
  464. d.bitc.en = data;
  465. *(volatile U32 *)REG_EFUSE_BOOT = d.all;
  466. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  467. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_BOOT_EN] <-- 0x%08x\n",
  468. REG_EFUSE_BOOT,d.all,d.all);
  469. #endif
  470. }
  471. GH_INLINE U8 GH_EFUSE_get_BOOT_EN(void)
  472. {
  473. GH_EFUSE_BOOT_S tmp_value;
  474. U32 value = (*(volatile U32 *)REG_EFUSE_BOOT);
  475. tmp_value.all = value;
  476. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  477. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_BOOT_EN] --> 0x%08x\n",
  478. REG_EFUSE_BOOT,value);
  479. #endif
  480. return tmp_value.bitc.en;
  481. }
  482. GH_INLINE void GH_EFUSE_set_BOOT_RD_OK(U8 data)
  483. {
  484. GH_EFUSE_BOOT_S d;
  485. d.all = *(volatile U32 *)REG_EFUSE_BOOT;
  486. d.bitc.rd_ok = data;
  487. *(volatile U32 *)REG_EFUSE_BOOT = d.all;
  488. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  489. GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_BOOT_RD_OK] <-- 0x%08x\n",
  490. REG_EFUSE_BOOT,d.all,d.all);
  491. #endif
  492. }
  493. GH_INLINE U8 GH_EFUSE_get_BOOT_RD_OK(void)
  494. {
  495. GH_EFUSE_BOOT_S tmp_value;
  496. U32 value = (*(volatile U32 *)REG_EFUSE_BOOT);
  497. tmp_value.all = value;
  498. #if GH_EFUSE_ENABLE_DEBUG_PRINT
  499. GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_BOOT_RD_OK] --> 0x%08x\n",
  500. REG_EFUSE_BOOT,value);
  501. #endif
  502. return tmp_value.bitc.rd_ok;
  503. }
  504. #endif /* GH_INLINE_LEVEL == 0 */
  505. /*----------------------------------------------------------------------------*/
  506. /* init function */
  507. /*----------------------------------------------------------------------------*/
  508. /*! \brief Initialises the registers and mirror variables. */
  509. void GH_EFUSE_init(void);
  510. #ifdef __cplusplus
  511. }
  512. #endif
  513. #endif /* _GH_EFUSE_H */
  514. /*----------------------------------------------------------------------------*/
  515. /* end of file */
  516. /*----------------------------------------------------------------------------*/