HAL_pwr.c 8.7 KB

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  1. /**
  2. ******************************************************************************
  3. * @file HAL_pwr.c
  4. * @author AE Team
  5. * @version V1.0.0
  6. * @date 28/7/2017
  7. * @brief This file provides all the PWR firmware functions.
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * <h2><center>&copy; COPYRIGHT 2017 MindMotion</center></h2>
  19. */
  20. /* Includes ------------------------------------------------------------------*/
  21. #include "HAL_pwr.h"
  22. #include "HAL_rcc.h"
  23. /** @addtogroup StdPeriph_Driver
  24. * @{
  25. */
  26. /** @defgroup PWR
  27. * @brief PWR driver modules
  28. * @{
  29. */
  30. /** @defgroup PWR_Private_TypesDefinitions
  31. * @{
  32. */
  33. /**
  34. * @}
  35. */
  36. /** @defgroup PWR_Private_Defines
  37. * @{
  38. */
  39. /* --------- PWR registers bit address in the alias region ---------- */
  40. #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
  41. /* --- CR Register ---*/
  42. /* Alias word address of DBP bit */
  43. #define CR_OFFSET (PWR_OFFSET + 0x00)
  44. #define DBP_BitNumber 0x08
  45. #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
  46. /* Alias word address of PVDE bit */
  47. #define PVDE_BitNumber 0x04
  48. #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
  49. /* --- CSR Register ---*/
  50. /* Alias word address of EWUP bit */
  51. #define CSR_OFFSET (PWR_OFFSET + 0x04)
  52. #define EWUP_BitNumber 0x08
  53. #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
  54. /* ------------------ PWR registers bit mask ------------------------ */
  55. /* CR register bit mask */
  56. #define CR_PDDS_Set ((uint32_t)0x00000002)
  57. #define CR_DS_Mask ((uint32_t)0xFFFFFFFC)
  58. #define CR_CWUF_Set ((uint32_t)0x00000004)
  59. #define CR_PLS_Mask ((uint32_t)0xFFFFE1FF)
  60. /* --------- Cortex System Control register bit mask ---------------- */
  61. /* Cortex System Control register address */
  62. #define SCB_SysCtrl ((uint32_t)0xE000ED10)
  63. /* SLEEPDEEP bit mask */
  64. #define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004)
  65. /**
  66. * @}
  67. */
  68. /** @defgroup PWR_Private_Macros
  69. * @{
  70. */
  71. /**
  72. * @}
  73. */
  74. /** @defgroup PWR_Private_Variables
  75. * @{
  76. */
  77. /**
  78. * @}
  79. */
  80. /** @defgroup PWR_Private_FunctionPrototypes
  81. * @{
  82. */
  83. /**
  84. * @}
  85. */
  86. /** @defgroup PWR_Private_Functions
  87. * @{
  88. */
  89. /**
  90. * @brief Deinitializes the PWR peripheral registers to their default
  91. * reset values.
  92. * @param None
  93. * @retval : None
  94. */
  95. void PWR_DeInit(void)
  96. {
  97. RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
  98. RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
  99. }
  100. /**
  101. * @brief Enables or disables access to the RTC and backup registers.
  102. * @param NewState: new state of the access to the RTC and backup
  103. * registers. This parameter can be: ENABLE or DISABLE.
  104. * @retval : None
  105. */
  106. void PWR_BackupAccessCmd(FunctionalState NewState)
  107. {
  108. /* Check the parameters */
  109. assert_param(IS_FUNCTIONAL_STATE(NewState));
  110. //*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
  111. if(NewState!=DISABLE)
  112. {
  113. PWR->CR |= 0x00000100;
  114. }
  115. else
  116. {
  117. PWR->CR &= 0xfffffeff;
  118. }
  119. }
  120. /**
  121. * @brief Enables or disables the Power Voltage Detector(PVD).
  122. * @param NewState: new state of the PVD.
  123. * This parameter can be: ENABLE or DISABLE.
  124. * @retval : None
  125. */
  126. void PWR_PVDCmd(FunctionalState NewState)
  127. {
  128. /* Check the parameters */
  129. assert_param(IS_FUNCTIONAL_STATE(NewState));
  130. if(NewState==ENABLE)
  131. {
  132. PWR->CR |= 0x00000010;
  133. }
  134. else
  135. {
  136. PWR->CR &= 0xffffffef;
  137. }
  138. }
  139. /**
  140. * @brief Configures the voltage threshold detected by the Power Voltage
  141. * Detector(PVD).
  142. * @param PWR_PVDLevel: specifies the PVD detection level
  143. * This parameter can be one of the following values:
  144. * @arg PWR_PVDLevel_1V8: PVD detection level set to 2.8V
  145. * @arg PWR_PVDLevel_2V1: PVD detection level set to 2.1V
  146. * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
  147. * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
  148. * @arg PWR_PVDLevel_3V0: PVD detection level set to 3.0V
  149. * @arg PWR_PVDLevel_3V3: PVD detection level set to 3.3V
  150. * @arg PWR_PVDLevel_3V6: PVD detection level set to 3.6V
  151. * @arg PWR_PVDLevel_3V9: PVD detection level set to 3.9V
  152. * @arg PWR_PVDLevel_4V2: PVD detection level set to 4.2V
  153. * @arg PWR_PVDLevel_4V5: PVD detection level set to 4.5V
  154. * @arg PWR_PVDLevel_4V8: PVD detection level set to 4.8V
  155. * @retval : None
  156. */
  157. void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
  158. {
  159. uint32_t tmpreg = 0;
  160. /* Check the parameters */
  161. assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
  162. tmpreg = PWR->CR;
  163. /* Clear PLS[12:9] bits */
  164. tmpreg &= CR_PLS_Mask;
  165. /* Set PLS[12:9] bits according to PWR_PVDLevel value */
  166. tmpreg |= PWR_PVDLevel;
  167. /* Store the new value */
  168. PWR->CR = tmpreg;
  169. }
  170. /**
  171. * @brief Enables or disables the WakeUp Pin functionality.
  172. * @param NewState: new state of the WakeUp Pin functionality.
  173. * This parameter can be: ENABLE or DISABLE.
  174. * @retval : None
  175. */
  176. void PWR_WakeUpPinCmd(FunctionalState NewState)
  177. {
  178. /* Check the parameters */
  179. assert_param(IS_FUNCTIONAL_STATE(NewState));
  180. if(NewState!=DISABLE)
  181. {
  182. PWR->CSR |= 0x00000100;
  183. }
  184. else
  185. {
  186. PWR->CSR &= 0xfffffeff;
  187. }
  188. }
  189. /**
  190. * @brief Enters STOP mode.
  191. * @param PWR_Regulator: specifies the regulator state in STOP mode.
  192. * This parameter can be one of the following values:
  193. * @arg PWR_Regulator_ON: STOP mode with regulator ON
  194. * @arg PWR_Regulator_LowPower: STOP mode with
  195. * regulator in low power mode
  196. * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or
  197. * WFE instruction.
  198. * This parameter can be one of the following values:
  199. * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
  200. * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
  201. * @retval : None
  202. */
  203. void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
  204. {
  205. uint32_t tmpreg = 0;
  206. /* Check the parameters */
  207. assert_param(IS_PWR_REGULATOR(PWR_Regulator));
  208. assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
  209. /* Select the regulator state in STOP mode ---------------------------------*/
  210. tmpreg = PWR->CR;
  211. /* Clear PDDS and LPDS bits */
  212. tmpreg &= CR_DS_Mask;
  213. /* Set LPDS bit according to PWR_Regulator value */
  214. tmpreg |= PWR_Regulator;
  215. /* Store the new value */
  216. PWR->CR = tmpreg;
  217. /* Set SLEEPDEEP bit of Cortex System Control Register */
  218. SCB->SCR |= SysCtrl_SLEEPDEEP_Set;
  219. /* Select STOP mode entry --------------------------------------------------*/
  220. if(PWR_STOPEntry == PWR_STOPEntry_WFI)
  221. {
  222. /* Request Wait For Interrupt */
  223. __WFI();
  224. }
  225. else
  226. {
  227. /* Request Wait For Event */
  228. __WFE();
  229. }
  230. }
  231. /**
  232. * @brief Enters STANDBY mode.
  233. * @param None
  234. * @retval : None
  235. */
  236. void PWR_EnterSTANDBYMode(void)
  237. {
  238. /* Clear Wake-up flag */
  239. PWR->CR |= CR_CWUF_Set;
  240. /* Select STANDBY mode */
  241. PWR->CR |= CR_PDDS_Set;
  242. /* Set SLEEPDEEP bit of Cortex System Control Register */
  243. SCB->SCR |= SysCtrl_SLEEPDEEP_Set;
  244. /* This option is used to ensure that store operations are completed */
  245. #if defined ( __CC_ARM )
  246. __force_stores();
  247. #endif
  248. /* Request Wait For Interrupt */
  249. __WFI();
  250. }
  251. /**
  252. * @brief Checks whether the specified PWR flag is set or not.
  253. * @param PWR_FLAG: specifies the flag to check.
  254. * This parameter can be one of the following values:
  255. * @arg PWR_FLAG_WU: Wake Up flag
  256. * @arg PWR_FLAG_SB: StandBy flag
  257. * @arg PWR_FLAG_PVDO: PVD Output
  258. * @retval : The new state of PWR_FLAG (SET or RESET).
  259. */
  260. FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
  261. {
  262. FlagStatus bitstatus = RESET;
  263. /* Check the parameters */
  264. assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
  265. if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
  266. {
  267. bitstatus = SET;
  268. }
  269. else
  270. {
  271. bitstatus = RESET;
  272. }
  273. /* Return the flag status */
  274. return bitstatus;
  275. }
  276. /**
  277. * @brief Clears the PWR's pending flags.
  278. * @param PWR_FLAG: specifies the flag to clear.
  279. * This parameter can be one of the following values:
  280. * @arg PWR_FLAG_WU: Wake Up flag
  281. * @arg PWR_FLAG_SB: StandBy flag
  282. * @retval : None
  283. */
  284. void PWR_ClearFlag(uint32_t PWR_FLAG)
  285. {
  286. /* Check the parameters */
  287. assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
  288. PWR->CR |= PWR_FLAG << 2;
  289. }
  290. /**
  291. * @}
  292. */
  293. /**
  294. * @}
  295. */
  296. /**
  297. * @}
  298. */
  299. /*-------------------------(C) COPYRIGHT 2017 MindMotion ----------------------*/