drv_gpio.c 15 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-4-30 misonyo the first version.
  9. */
  10. #include <rtthread.h>
  11. #ifdef BSP_USING_GPIO
  12. #include <rthw.h>
  13. #include "drv_gpio.h"
  14. #include "board.h"
  15. #include "fsl_gpio.h"
  16. #include "fsl_iomuxc.h"
  17. #define LOG_TAG "drv.gpio"
  18. #include <drv_log.h>
  19. #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
  20. #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
  21. #endif
  22. #define __IMXRT_HDR_DEFAULT {-1, 0, RT_NULL, RT_NULL}
  23. #define PIN_INVALID_CHECK(PORT_INDEX,PIN_NUM) (PORT_INDEX > 4) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0)
  24. #if defined(SOC_IMXRT1015_SERIES)
  25. #define muxReg_base 0x401f8024
  26. #define configReg_base 0x401f8198
  27. #elif defined(SOC_IMXRT1020_SERIES)
  28. #define muxReg_base 0x401f8014
  29. #define configReg_base 0x401f8188
  30. #else /* 1050 & 1060 & 1064 series*/
  31. #define MUX_BASE 0x401f8014
  32. #define CONFIG_BASE 0x401f8204
  33. #endif
  34. #define GPIO5_MUX_BASE 0x400A8000
  35. #define GPIO5_CONFIG_BASE 0x400A8018
  36. struct pin_mask
  37. {
  38. GPIO_Type *gpio;
  39. rt_int32_t valid_mask;
  40. };
  41. const struct pin_mask mask_tab[5] =
  42. {
  43. #if defined(SOC_IMXRT1015_SERIES)
  44. {GPIO1, 0xfc00ffff}, /* GPIO1,16~25 not supported */
  45. {GPIO2, 0xffff03f8}, /* GPIO2,0~2,10~15 not supported */
  46. {GPIO3, 0x7ff0000f}, /* GPIO3,4~19 not supported */
  47. {GPIO4, 0x00000000}, /* GPIO4 not supported */
  48. {GPIO5, 0x00000001} /* GPIO5,0,2,3~31 not supported */
  49. #elif defined(SOC_IMXRT1020_SERIES)
  50. {GPIO1, 0xffffffff}, /* GPIO1 */
  51. {GPIO2, 0xffffffff}, /* GPIO2 */
  52. {GPIO3, 0xffffe3ff}, /* GPIO3,10~12 not supported */
  53. {GPIO4, 0x00000000}, /* GPIO4 not supported */
  54. {GPIO5, 0x00000007} /* GPIO5,3~31 not supported */
  55. #else /* 1050 & 1060 & 1064 series*/
  56. {GPIO1, 0xffffffff}, /* GPIO1 */
  57. {GPIO2, 0xffffffff}, /* GPIO2 */
  58. {GPIO3, 0x0fffffff}, /* GPIO3,28~31 not supported */
  59. {GPIO4, 0xffffffff}, /* GPIO4 */
  60. {GPIO5, 0x00000007} /* GPIO5,3~31 not supported */
  61. #endif
  62. };
  63. const rt_int8_t reg_offset[] =
  64. {
  65. #if defined(SOC_IMXRT1015_SERIES)
  66. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 64, 65, 66, 67, 68, 69,
  67. -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, -1, -1, -1, -1, -1, -1, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, -1, -1, -1, -1,
  68. 28, 29, 30, 31, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88,
  69. #elif defined(SOC_IMXRT1020_SERIES)
  70. 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
  71. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  72. 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
  73. #else /* 1050 & 1060 & 1064 series*/
  74. 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
  75. 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,
  76. 112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1,
  77. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  78. #endif
  79. };
  80. static const IRQn_Type irq_tab[10] =
  81. {
  82. GPIO1_Combined_0_15_IRQn,
  83. GPIO1_Combined_16_31_IRQn,
  84. GPIO2_Combined_0_15_IRQn,
  85. GPIO2_Combined_16_31_IRQn,
  86. GPIO3_Combined_0_15_IRQn,
  87. GPIO3_Combined_16_31_IRQn,
  88. GPIO4_Combined_0_15_IRQn,
  89. GPIO4_Combined_16_31_IRQn,
  90. GPIO5_Combined_0_15_IRQn,
  91. GPIO5_Combined_16_31_IRQn
  92. };
  93. static struct rt_pin_irq_hdr hdr_tab[] =
  94. {
  95. /* GPIO1 */
  96. __IMXRT_HDR_DEFAULT,
  97. __IMXRT_HDR_DEFAULT,
  98. __IMXRT_HDR_DEFAULT,
  99. __IMXRT_HDR_DEFAULT,
  100. __IMXRT_HDR_DEFAULT,
  101. __IMXRT_HDR_DEFAULT,
  102. __IMXRT_HDR_DEFAULT,
  103. __IMXRT_HDR_DEFAULT,
  104. __IMXRT_HDR_DEFAULT,
  105. __IMXRT_HDR_DEFAULT,
  106. __IMXRT_HDR_DEFAULT,
  107. __IMXRT_HDR_DEFAULT,
  108. __IMXRT_HDR_DEFAULT,
  109. __IMXRT_HDR_DEFAULT,
  110. __IMXRT_HDR_DEFAULT,
  111. __IMXRT_HDR_DEFAULT,
  112. __IMXRT_HDR_DEFAULT,
  113. __IMXRT_HDR_DEFAULT,
  114. __IMXRT_HDR_DEFAULT,
  115. __IMXRT_HDR_DEFAULT,
  116. __IMXRT_HDR_DEFAULT,
  117. __IMXRT_HDR_DEFAULT,
  118. __IMXRT_HDR_DEFAULT,
  119. __IMXRT_HDR_DEFAULT,
  120. __IMXRT_HDR_DEFAULT,
  121. __IMXRT_HDR_DEFAULT,
  122. __IMXRT_HDR_DEFAULT,
  123. __IMXRT_HDR_DEFAULT,
  124. __IMXRT_HDR_DEFAULT,
  125. __IMXRT_HDR_DEFAULT,
  126. __IMXRT_HDR_DEFAULT,
  127. __IMXRT_HDR_DEFAULT,
  128. /* GPIO2 */
  129. __IMXRT_HDR_DEFAULT,
  130. __IMXRT_HDR_DEFAULT,
  131. __IMXRT_HDR_DEFAULT,
  132. __IMXRT_HDR_DEFAULT,
  133. __IMXRT_HDR_DEFAULT,
  134. __IMXRT_HDR_DEFAULT,
  135. __IMXRT_HDR_DEFAULT,
  136. __IMXRT_HDR_DEFAULT,
  137. __IMXRT_HDR_DEFAULT,
  138. __IMXRT_HDR_DEFAULT,
  139. __IMXRT_HDR_DEFAULT,
  140. __IMXRT_HDR_DEFAULT,
  141. __IMXRT_HDR_DEFAULT,
  142. __IMXRT_HDR_DEFAULT,
  143. __IMXRT_HDR_DEFAULT,
  144. __IMXRT_HDR_DEFAULT,
  145. __IMXRT_HDR_DEFAULT,
  146. __IMXRT_HDR_DEFAULT,
  147. __IMXRT_HDR_DEFAULT,
  148. __IMXRT_HDR_DEFAULT,
  149. __IMXRT_HDR_DEFAULT,
  150. __IMXRT_HDR_DEFAULT,
  151. __IMXRT_HDR_DEFAULT,
  152. __IMXRT_HDR_DEFAULT,
  153. __IMXRT_HDR_DEFAULT,
  154. __IMXRT_HDR_DEFAULT,
  155. __IMXRT_HDR_DEFAULT,
  156. __IMXRT_HDR_DEFAULT,
  157. __IMXRT_HDR_DEFAULT,
  158. __IMXRT_HDR_DEFAULT,
  159. __IMXRT_HDR_DEFAULT,
  160. __IMXRT_HDR_DEFAULT,
  161. /* GPIO3 */
  162. __IMXRT_HDR_DEFAULT,
  163. __IMXRT_HDR_DEFAULT,
  164. __IMXRT_HDR_DEFAULT,
  165. __IMXRT_HDR_DEFAULT,
  166. __IMXRT_HDR_DEFAULT,
  167. __IMXRT_HDR_DEFAULT,
  168. __IMXRT_HDR_DEFAULT,
  169. __IMXRT_HDR_DEFAULT,
  170. __IMXRT_HDR_DEFAULT,
  171. __IMXRT_HDR_DEFAULT,
  172. __IMXRT_HDR_DEFAULT,
  173. __IMXRT_HDR_DEFAULT,
  174. __IMXRT_HDR_DEFAULT,
  175. __IMXRT_HDR_DEFAULT,
  176. __IMXRT_HDR_DEFAULT,
  177. __IMXRT_HDR_DEFAULT,
  178. __IMXRT_HDR_DEFAULT,
  179. __IMXRT_HDR_DEFAULT,
  180. __IMXRT_HDR_DEFAULT,
  181. __IMXRT_HDR_DEFAULT,
  182. __IMXRT_HDR_DEFAULT,
  183. __IMXRT_HDR_DEFAULT,
  184. __IMXRT_HDR_DEFAULT,
  185. __IMXRT_HDR_DEFAULT,
  186. __IMXRT_HDR_DEFAULT,
  187. __IMXRT_HDR_DEFAULT,
  188. __IMXRT_HDR_DEFAULT,
  189. __IMXRT_HDR_DEFAULT,
  190. __IMXRT_HDR_DEFAULT,
  191. __IMXRT_HDR_DEFAULT,
  192. __IMXRT_HDR_DEFAULT,
  193. __IMXRT_HDR_DEFAULT,
  194. /* GPIO4 */
  195. __IMXRT_HDR_DEFAULT,
  196. __IMXRT_HDR_DEFAULT,
  197. __IMXRT_HDR_DEFAULT,
  198. __IMXRT_HDR_DEFAULT,
  199. __IMXRT_HDR_DEFAULT,
  200. __IMXRT_HDR_DEFAULT,
  201. __IMXRT_HDR_DEFAULT,
  202. __IMXRT_HDR_DEFAULT,
  203. __IMXRT_HDR_DEFAULT,
  204. __IMXRT_HDR_DEFAULT,
  205. __IMXRT_HDR_DEFAULT,
  206. __IMXRT_HDR_DEFAULT,
  207. __IMXRT_HDR_DEFAULT,
  208. __IMXRT_HDR_DEFAULT,
  209. __IMXRT_HDR_DEFAULT,
  210. __IMXRT_HDR_DEFAULT,
  211. __IMXRT_HDR_DEFAULT,
  212. __IMXRT_HDR_DEFAULT,
  213. __IMXRT_HDR_DEFAULT,
  214. __IMXRT_HDR_DEFAULT,
  215. __IMXRT_HDR_DEFAULT,
  216. __IMXRT_HDR_DEFAULT,
  217. __IMXRT_HDR_DEFAULT,
  218. __IMXRT_HDR_DEFAULT,
  219. __IMXRT_HDR_DEFAULT,
  220. __IMXRT_HDR_DEFAULT,
  221. __IMXRT_HDR_DEFAULT,
  222. __IMXRT_HDR_DEFAULT,
  223. __IMXRT_HDR_DEFAULT,
  224. __IMXRT_HDR_DEFAULT,
  225. __IMXRT_HDR_DEFAULT,
  226. __IMXRT_HDR_DEFAULT,
  227. /* GPIO5 */
  228. __IMXRT_HDR_DEFAULT,
  229. __IMXRT_HDR_DEFAULT,
  230. __IMXRT_HDR_DEFAULT,
  231. };
  232. static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *base)
  233. {
  234. rt_int32_t isr_status, index;
  235. rt_int8_t i, pin_end;
  236. pin_end = pin_start + 15;
  237. isr_status = GPIO_PortGetInterruptFlags(base) & base->IMR;
  238. for (i = pin_start; i <= pin_end ; i++)
  239. {
  240. if (isr_status & (1 << i))
  241. {
  242. GPIO_PortClearInterruptFlags(base, (1 << i));
  243. index = index_offset + i;
  244. if (hdr_tab[index].hdr != RT_NULL)
  245. {
  246. hdr_tab[index].hdr(hdr_tab[index].args);
  247. }
  248. }
  249. }
  250. }
  251. /* GPIO1 index offset is 0 */
  252. void GPIO1_Combined_0_15_IRQHandler(void)
  253. {
  254. rt_interrupt_enter();
  255. imxrt_isr(0, 0, GPIO1);
  256. rt_interrupt_leave();
  257. }
  258. void GPIO1_Combined_16_31_IRQHandler(void)
  259. {
  260. rt_interrupt_enter();
  261. imxrt_isr(0, 15, GPIO1);
  262. rt_interrupt_leave();
  263. }
  264. /* GPIO2 index offset is 32 */
  265. void GPIO2_Combined_0_15_IRQHandler(void)
  266. {
  267. rt_interrupt_enter();
  268. imxrt_isr(32, 0, GPIO2);
  269. rt_interrupt_leave();
  270. }
  271. void GPIO2_Combined_16_31_IRQHandler(void)
  272. {
  273. rt_interrupt_enter();
  274. imxrt_isr(32, 15, GPIO2);
  275. rt_interrupt_leave();
  276. }
  277. /* GPIO3 index offset is 64 */
  278. void GPIO3_Combined_0_15_IRQHandler(void)
  279. {
  280. rt_interrupt_enter();
  281. imxrt_isr(64, 0, GPIO3);
  282. rt_interrupt_leave();
  283. }
  284. void GPIO3_Combined_16_31_IRQHandler(void)
  285. {
  286. rt_interrupt_enter();
  287. imxrt_isr(64, 15, GPIO3);
  288. rt_interrupt_leave();
  289. }
  290. #ifdef GPIO4
  291. /* GPIO4 index offset is 96 */
  292. void GPIO4_Combined_0_15_IRQHandler(void)
  293. {
  294. rt_interrupt_enter();
  295. imxrt_isr(96, 0, GPIO4);
  296. rt_interrupt_leave();
  297. }
  298. void GPIO4_Combined_16_31_IRQHandler(void)
  299. {
  300. rt_interrupt_enter();
  301. imxrt_isr(96, 15, GPIO4);
  302. rt_interrupt_leave();
  303. }
  304. #endif
  305. /* GPIO5 index offset is 128 */
  306. void GPIO5_Combined_0_15_IRQHandler(void)
  307. {
  308. rt_interrupt_enter();
  309. imxrt_isr(128, 0, GPIO5);
  310. rt_interrupt_leave();
  311. }
  312. static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
  313. {
  314. gpio_pin_config_t gpio;
  315. rt_uint32_t config_value = 0;
  316. rt_int8_t port, pin_num;
  317. port = pin >> 5;
  318. pin_num = pin & 31;
  319. if (PIN_INVALID_CHECK(port, pin_num))
  320. {
  321. LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
  322. return;
  323. }
  324. gpio.outputLogic = 0;
  325. gpio.interruptMode = kGPIO_NoIntmode;
  326. switch (mode)
  327. {
  328. case PIN_MODE_OUTPUT:
  329. {
  330. gpio.direction = kGPIO_DigitalOutput;
  331. config_value = 0x0030U; /* Drive Strength R0/6 */
  332. }
  333. break;
  334. case PIN_MODE_INPUT:
  335. {
  336. gpio.direction = kGPIO_DigitalInput;
  337. config_value = 0x0830U; /* Open Drain Enable */
  338. }
  339. break;
  340. case PIN_MODE_INPUT_PULLDOWN:
  341. {
  342. gpio.direction = kGPIO_DigitalInput;
  343. config_value = 0x3030U; /* 100K Ohm Pull Down */
  344. }
  345. break;
  346. case PIN_MODE_INPUT_PULLUP:
  347. {
  348. gpio.direction = kGPIO_DigitalInput;
  349. config_value = 0xB030U; /* 100K Ohm Pull Up */
  350. }
  351. break;
  352. case PIN_MODE_OUTPUT_OD:
  353. {
  354. gpio.direction = kGPIO_DigitalOutput;
  355. config_value = 0x0830U; /* Open Drain Enable */
  356. }
  357. break;
  358. }
  359. if (mask_tab[port].gpio != GPIO5)
  360. {
  361. CLOCK_EnableClock(kCLOCK_Iomuxc);
  362. IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
  363. IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value);
  364. }
  365. else
  366. {
  367. CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
  368. IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_num * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_num * 4, 1);
  369. IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_num * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_num * 4, config_value);
  370. }
  371. GPIO_PinInit(mask_tab[port].gpio, pin_num, &gpio);
  372. }
  373. static int imxrt_pin_read(rt_device_t dev, rt_base_t pin)
  374. {
  375. int value;
  376. rt_int8_t port, pin_num;
  377. value = PIN_LOW;
  378. port = pin >> 5;
  379. pin_num = pin & 31;
  380. if (PIN_INVALID_CHECK(port, pin_num))
  381. {
  382. LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
  383. return value;
  384. }
  385. return GPIO_PinReadPadStatus(mask_tab[port].gpio, pin_num);
  386. }
  387. static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
  388. {
  389. rt_int8_t port, pin_num;
  390. port = pin >> 5;
  391. pin_num = pin & 31;
  392. if (PIN_INVALID_CHECK(port, pin_num))
  393. {
  394. LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
  395. return;
  396. }
  397. GPIO_PinWrite(mask_tab[port].gpio, pin_num, value);
  398. }
  399. static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
  400. rt_uint32_t mode, void (*hdr)(void *args), void *args)
  401. {
  402. rt_base_t level;
  403. rt_int8_t port, pin_num;
  404. port = pin >> 5;
  405. pin_num = pin & 31;
  406. if (PIN_INVALID_CHECK(port, pin_num))
  407. {
  408. LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
  409. return RT_ENOSYS;
  410. }
  411. level = rt_hw_interrupt_disable();
  412. if (hdr_tab[pin].pin == pin &&
  413. hdr_tab[pin].hdr == hdr &&
  414. hdr_tab[pin].mode == mode &&
  415. hdr_tab[pin].args == args)
  416. {
  417. rt_hw_interrupt_enable(level);
  418. return RT_EOK;
  419. }
  420. hdr_tab[pin].pin = pin;
  421. hdr_tab[pin].hdr = hdr;
  422. hdr_tab[pin].mode = mode;
  423. hdr_tab[pin].args = args;
  424. rt_hw_interrupt_enable(level);
  425. return RT_EOK;
  426. }
  427. static rt_err_t imxrt_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
  428. {
  429. rt_base_t level;
  430. rt_int8_t port, pin_num;
  431. port = pin >> 5;
  432. pin_num = pin & 31;
  433. if (PIN_INVALID_CHECK(port, pin_num))
  434. {
  435. LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
  436. return RT_ENOSYS;
  437. }
  438. level = rt_hw_interrupt_disable();
  439. if (hdr_tab[pin].pin == -1)
  440. {
  441. rt_hw_interrupt_enable(level);
  442. return RT_EOK;
  443. }
  444. hdr_tab[pin].pin = -1;
  445. hdr_tab[pin].hdr = RT_NULL;
  446. hdr_tab[pin].mode = 0;
  447. hdr_tab[pin].args = RT_NULL;
  448. rt_hw_interrupt_enable(level);
  449. return RT_EOK;
  450. }
  451. static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
  452. {
  453. gpio_interrupt_mode_t int_mode;
  454. rt_int8_t port, pin_num, irq_index;
  455. port = pin >> 5;
  456. pin_num = pin & 31;
  457. if (PIN_INVALID_CHECK(port, pin_num))
  458. {
  459. LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
  460. return RT_ENOSYS;
  461. }
  462. if (hdr_tab[pin].pin == -1)
  463. {
  464. LOG_D("rtt pin: %d callback function not initialized!\n", pin);
  465. return RT_ENOSYS;
  466. }
  467. if (enabled == PIN_IRQ_ENABLE)
  468. {
  469. switch (hdr_tab[pin].mode)
  470. {
  471. case PIN_IRQ_MODE_RISING:
  472. int_mode = kGPIO_IntRisingEdge;
  473. break;
  474. case PIN_IRQ_MODE_FALLING:
  475. int_mode = kGPIO_IntFallingEdge;
  476. break;
  477. case PIN_IRQ_MODE_RISING_FALLING:
  478. int_mode = kGPIO_IntRisingOrFallingEdge;
  479. break;
  480. case PIN_IRQ_MODE_HIGH_LEVEL:
  481. int_mode = kGPIO_IntHighLevel;
  482. break;
  483. case PIN_IRQ_MODE_LOW_LEVEL:
  484. int_mode = kGPIO_IntLowLevel;
  485. break;
  486. default:
  487. int_mode = kGPIO_IntRisingEdge;
  488. break;
  489. }
  490. irq_index = (port << 1) + (pin_num >> 4);
  491. GPIO_PinSetInterruptConfig(mask_tab[port].gpio, pin_num, int_mode);
  492. GPIO_PortEnableInterrupts(mask_tab[port].gpio, 1U << pin_num);
  493. NVIC_SetPriority(irq_tab[irq_index], NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
  494. EnableIRQ(irq_tab[irq_index]);
  495. }
  496. else if (enabled == PIN_IRQ_DISABLE)
  497. {
  498. GPIO_PortDisableInterrupts(mask_tab[port].gpio, 1U << pin_num);
  499. }
  500. else
  501. {
  502. return RT_EINVAL;
  503. }
  504. return RT_EOK;
  505. }
  506. const static struct rt_pin_ops imxrt_pin_ops =
  507. {
  508. imxrt_pin_mode,
  509. imxrt_pin_write,
  510. imxrt_pin_read,
  511. imxrt_pin_attach_irq,
  512. imxrt_pin_detach_irq,
  513. imxrt_pin_irq_enable,
  514. RT_NULL,
  515. };
  516. int rt_hw_pin_init(void)
  517. {
  518. int ret = RT_EOK;
  519. ret = rt_device_pin_register("pin", &imxrt_pin_ops, RT_NULL);
  520. return ret;
  521. }
  522. INIT_BOARD_EXPORT(rt_hw_pin_init);
  523. #endif /* BSP_USING_GPIO */