drv_i2c.c 9.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357
  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2017-08-08 Yang the first version
  9. * 2018-03-24 LaiYiKeTang add hardware iic
  10. * 2019-04-22 tyustli add imxrt series support
  11. *
  12. */
  13. #include <rtthread.h>
  14. #ifdef BSP_USING_I2C
  15. #define LOG_TAG "drv.i2c"
  16. #include <drv_log.h>
  17. #if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4)
  18. #error "Please define at least one BSP_USING_I2Cx"
  19. #endif
  20. #include <rtdevice.h>
  21. #include "fsl_lpi2c.h"
  22. #include "drv_i2c.h"
  23. struct imxrt_i2c_bus
  24. {
  25. struct rt_i2c_bus_device parent;
  26. LPI2C_Type *I2C;
  27. struct rt_i2c_msg *msg;
  28. rt_uint32_t msg_cnt;
  29. volatile rt_uint32_t msg_ptr;
  30. volatile rt_uint32_t dptr;
  31. char *device_name;
  32. };
  33. #if defined (BSP_USING_I2C1)
  34. #define I2C1BUS_NAME "i2c1"
  35. #endif /*BSP_USING_I2C1*/
  36. #if defined (BSP_USING_I2C2)
  37. #define I2C2BUS_NAME "i2c2"
  38. #endif /*BSP_USING_I2C2*/
  39. #if !defined (MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/
  40. #if defined (BSP_USING_I2C3)
  41. #define I2C3BUS_NAME "i2c3"
  42. #endif /*BSP_USING_I2C3*/
  43. #if defined (BSP_USING_I2C4)
  44. #define I2C4BUS_NAME "i2c4"
  45. #endif /*BSP_USING_I2C4*/
  46. #endif /* MIMXRT1015_SERIES */
  47. #define LPI2C_CLOCK_SOURCE_DIVIDER 4
  48. /* Get frequency of lpi2c clock */
  49. #define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER))
  50. #ifdef BSP_USING_I2C1
  51. static struct imxrt_i2c_bus lpi2c1 =
  52. {
  53. .I2C = LPI2C1,
  54. .device_name = I2C1BUS_NAME,
  55. };
  56. #endif /* RT_USING_HW_I2C1 */
  57. #ifdef BSP_USING_I2C2
  58. static struct imxrt_i2c_bus lpi2c2 =
  59. {
  60. .I2C = LPI2C2,
  61. .device_name = I2C2BUS_NAME,
  62. };
  63. #endif /* RT_USING_HW_I2C2 */
  64. #if !defined (MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/
  65. #ifdef BSP_USING_I2C3
  66. static struct imxrt_i2c_bus lpi2c3 =
  67. {
  68. .I2C = LPI2C3,
  69. .device_name = I2C3BUS_NAME,
  70. };
  71. #endif /* RT_USING_HW_I2C3 */
  72. #ifdef BSP_USING_I2C4
  73. static struct imxrt_i2c_bus lpi2c4 =
  74. {
  75. .I2C = LPI2C4,
  76. .device_name = I2C4BUS_NAME,
  77. };
  78. #endif /* RT_USING_HW_I2C4 */
  79. #endif /* MIMXRT1015_SERIES */
  80. #if (defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4))
  81. static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
  82. struct rt_i2c_msg msgs[],
  83. rt_uint32_t num);
  84. static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
  85. struct rt_i2c_msg msgs[],
  86. rt_uint32_t num);
  87. static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus,
  88. rt_uint32_t,
  89. rt_uint32_t);
  90. static const struct rt_i2c_bus_device_ops imxrt_i2c_ops =
  91. {
  92. .master_xfer = imxrt_i2c_mst_xfer,
  93. .slave_xfer = imxrt_i2c_slv_xfer,
  94. .i2c_bus_control = imxrt_i2c_bus_control,
  95. };
  96. static rt_err_t imxrt_lpi2c_configure(struct imxrt_i2c_bus *bus, lpi2c_master_config_t *cfg)
  97. {
  98. RT_ASSERT(bus != RT_NULL);
  99. RT_ASSERT(cfg != RT_NULL);
  100. bus->parent.ops = &imxrt_i2c_ops;
  101. LPI2C_MasterInit(bus->I2C, cfg, LPI2C_CLOCK_FREQUENCY);
  102. return RT_EOK;
  103. }
  104. status_t LPI2C_MasterCheck(LPI2C_Type *base, uint32_t status)
  105. {
  106. status_t result = kStatus_Success;
  107. /* Check for error. These errors cause a stop to automatically be sent. We must */
  108. /* clear the errors before a new transfer can start. */
  109. status &= 0x3c00;
  110. if (status)
  111. {
  112. /* Select the correct error code. Ordered by severity, with bus issues first. */
  113. if (status & kLPI2C_MasterPinLowTimeoutFlag)
  114. {
  115. result = kStatus_LPI2C_PinLowTimeout;
  116. }
  117. else if (status & kLPI2C_MasterArbitrationLostFlag)
  118. {
  119. result = kStatus_LPI2C_ArbitrationLost;
  120. }
  121. else if (status & kLPI2C_MasterNackDetectFlag)
  122. {
  123. result = kStatus_LPI2C_Nak;
  124. }
  125. else if (status & kLPI2C_MasterFifoErrFlag)
  126. {
  127. result = kStatus_LPI2C_FifoError;
  128. }
  129. else
  130. {
  131. assert(false);
  132. }
  133. /* Clear the flags. */
  134. LPI2C_MasterClearStatusFlags(base, status);
  135. /* Reset fifos. These flags clear automatically. */
  136. base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
  137. }
  138. return result;
  139. }
  140. /*!
  141. * @brief Wait until the tx fifo all empty.
  142. * @param base The LPI2C peripheral base address.
  143. * @retval #kStatus_Success
  144. * @retval #kStatus_LPI2C_PinLowTimeout
  145. * @retval #kStatus_LPI2C_ArbitrationLost
  146. * @retval #kStatus_LPI2C_Nak
  147. * @retval #kStatus_LPI2C_FifoError
  148. */
  149. static status_t LPI2C_MasterWaitForTxFifoAllEmpty(LPI2C_Type *base)
  150. {
  151. uint32_t status;
  152. size_t txCount;
  153. do
  154. {
  155. status_t result;
  156. /* Get the number of words in the tx fifo and compute empty slots. */
  157. LPI2C_MasterGetFifoCounts(base, NULL, &txCount);
  158. /* Check for error flags. */
  159. status = LPI2C_MasterGetStatusFlags(base);
  160. result = LPI2C_MasterCheck(base, status);
  161. if (result)
  162. {
  163. return result;
  164. }
  165. }
  166. while (txCount);
  167. return kStatus_Success;
  168. }
  169. static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
  170. struct rt_i2c_msg msgs[],
  171. rt_uint32_t num)
  172. {
  173. struct imxrt_i2c_bus *imxrt_i2c;
  174. rt_size_t i;
  175. RT_ASSERT(bus != RT_NULL);
  176. imxrt_i2c = (struct imxrt_i2c_bus *) bus;
  177. imxrt_i2c->msg = msgs;
  178. imxrt_i2c->msg_ptr = 0;
  179. imxrt_i2c->msg_cnt = num;
  180. imxrt_i2c->dptr = 0;
  181. for (i = 0; i < num; i++)
  182. {
  183. if (imxrt_i2c->msg[i].flags & RT_I2C_RD)
  184. {
  185. if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success)
  186. {
  187. i = 0;
  188. break;
  189. }
  190. while (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
  191. {
  192. }
  193. if (LPI2C_MasterRepeatedStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
  194. {
  195. i = 0;
  196. break;
  197. }
  198. if (LPI2C_MasterReceive(imxrt_i2c->I2C, imxrt_i2c->msg[i].buf, imxrt_i2c->msg[i].len) != kStatus_Success)
  199. {
  200. i = 0;
  201. break;
  202. }
  203. }
  204. else
  205. {
  206. if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success)
  207. {
  208. i = 0;
  209. break;
  210. }
  211. while (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
  212. {
  213. }
  214. if (LPI2C_MasterSend(imxrt_i2c->I2C, imxrt_i2c->msg[i].buf, imxrt_i2c->msg[i].len) != kStatus_Success)
  215. {
  216. i = 0;
  217. break;
  218. }
  219. if (LPI2C_MasterWaitForTxFifoAllEmpty(imxrt_i2c->I2C) != kStatus_Success)
  220. {
  221. i = 0;
  222. break;
  223. }
  224. }
  225. }
  226. if (LPI2C_MasterStop(imxrt_i2c->I2C) != kStatus_Success)
  227. {
  228. i = 0;
  229. }
  230. imxrt_i2c->msg = RT_NULL;
  231. imxrt_i2c->msg_ptr = 0;
  232. imxrt_i2c->msg_cnt = 0;
  233. imxrt_i2c->dptr = 0;
  234. return i;
  235. }
  236. static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
  237. struct rt_i2c_msg msgs[],
  238. rt_uint32_t num)
  239. {
  240. return 0;
  241. }
  242. static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus,
  243. rt_uint32_t cmd,
  244. rt_uint32_t arg)
  245. {
  246. return RT_ERROR;
  247. }
  248. #endif
  249. int rt_hw_i2c_init(void)
  250. {
  251. lpi2c_master_config_t masterConfig = {0};
  252. #if defined(BSP_USING_I2C1)
  253. LPI2C_MasterGetDefaultConfig(&masterConfig);
  254. #if defined(HW_I2C1_BADURATE_400kHZ)
  255. masterConfig.baudRate_Hz = 400000U;
  256. #elif defined(HW_I2C1_BADURATE_100kHZ)
  257. masterConfig.baudRate_Hz = 100000U;
  258. #endif /*HW_I2C1_BADURATE_400kHZ*/
  259. imxrt_lpi2c_configure(&lpi2c1, &masterConfig);
  260. rt_i2c_bus_device_register(&lpi2c1.parent, lpi2c1.device_name);
  261. #endif /* BSP_USING_I2C1 */
  262. #if defined(BSP_USING_I2C2)
  263. LPI2C_MasterGetDefaultConfig(&masterConfig);
  264. #if defined(HW_I2C2_BADURATE_400kHZ)
  265. masterConfig.baudRate_Hz = 400000U;
  266. #elif defined(HW_I2C2_BADURATE_100kHZ)
  267. masterConfig.baudRate_Hz = 100000U;
  268. #endif /* HW_I2C2_BADURATE_400kHZ */
  269. imxrt_lpi2c_configure(&lpi2c2, &masterConfig);
  270. rt_i2c_bus_device_register(&lpi2c2.parent, lpi2c2.device_name);
  271. #endif /* BSP_USING_I2C2 */
  272. #if !defined(MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/
  273. #if defined(BSP_USING_I2C3)
  274. LPI2C_MasterGetDefaultConfig(&masterConfig);
  275. #if defined(HW_I2C3_BADURATE_400kHZ)
  276. masterConfig.baudRate_Hz = 400000U;
  277. #elif defined(HW_I2C3_BADURATE_100kHZ)
  278. masterConfig.baudRate_Hz = 100000U;
  279. #endif /* HW_I2C3_BADURATE_400kHZ */
  280. imxrt_lpi2c_configure(&lpi2c3, &masterConfig);
  281. rt_i2c_bus_device_register(&lpi2c3.parent, lpi2c3.device_name);
  282. #endif /* BSP_USING_I2C3 */
  283. #if defined(BSP_USING_I2C4)
  284. LPI2C_MasterGetDefaultConfig(&masterConfig);
  285. #if defined(HW_I2C4_BADURATE_400kHZ)
  286. masterConfig.baudRate_Hz = 400000U;
  287. #elif defined(HW_I2C4_BADURATE_100kHZ)
  288. masterConfig.baudRate_Hz = 100000U;
  289. #endif /* HW_I2C4_BADURATE_400kHZ */
  290. imxrt_lpi2c_configure(&lpi2c4, &masterConfig);
  291. rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name);
  292. #endif /* BSP_USING_I2C4 */
  293. #endif /* MIMXRT1015_SERIES */
  294. return 0;
  295. }
  296. INIT_DEVICE_EXPORT(rt_hw_i2c_init);
  297. #endif /* BSP_USING_I2C */