drv_uart.c 17 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-23 AisinoChip the first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include "board.h"
  14. #include "uart_config.h"
  15. #ifdef RT_USING_SERIAL
  16. #ifdef RT_SERIAL_USING_DMA
  17. struct dma_config
  18. {
  19. DMA_Channel_TypeDef *Instance;
  20. rt_uint32_t dma_rcc;
  21. IRQn_Type dma_irq;
  22. rt_uint32_t channel;
  23. rt_uint32_t request;
  24. };
  25. #endif
  26. #ifdef RT_SERIAL_USING_DMA
  27. static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag);
  28. #endif /* RT_SERIAL_USING_DMA */
  29. struct acm32_uart_config
  30. {
  31. const char *name;
  32. UART_TypeDef *Instance;
  33. IRQn_Type irq_type;
  34. enum_Enable_ID_t enable_id;
  35. #ifdef RT_SERIAL_USING_DMA
  36. struct dma_config *dma_rx;
  37. struct dma_config *dma_tx;
  38. #endif
  39. enum_GPIOx_t tx_port;
  40. enum_GPIOx_t rx_port;
  41. rt_uint32_t tx_pin;
  42. rt_uint32_t rx_pin;
  43. };
  44. struct acm32_uart
  45. {
  46. UART_HandleTypeDef handle;
  47. struct acm32_uart_config *config;
  48. #ifdef RT_SERIAL_USING_DMA
  49. struct
  50. {
  51. DMA_HandleTypeDef handle;
  52. rt_size_t last_index;
  53. } dma_rx;
  54. struct
  55. {
  56. DMA_HandleTypeDef handle;
  57. } dma_tx;
  58. #endif
  59. rt_uint16_t uart_dma_flag;
  60. struct rt_serial_device serial;
  61. };
  62. static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size)
  63. {
  64. return RT_EOK;
  65. }
  66. static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  67. {
  68. struct acm32_uart *uart;
  69. RT_ASSERT(serial != RT_NULL);
  70. RT_ASSERT(cfg != RT_NULL);
  71. uart = rt_container_of(serial, struct acm32_uart, serial);
  72. uart->handle.Instance = uart->config->Instance;
  73. uart->handle.Init.BaudRate = cfg->baud_rate;
  74. if (cfg->data_bits == DATA_BITS_8)
  75. {
  76. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  77. }
  78. else /* not support */
  79. {
  80. return -RT_EINVAL;
  81. }
  82. if (cfg->stop_bits == STOP_BITS_1)
  83. {
  84. uart->handle.Init.StopBits = UART_STOPBITS_1;
  85. }
  86. else if (cfg->stop_bits == STOP_BITS_2)
  87. {
  88. uart->handle.Init.StopBits = UART_STOPBITS_2;
  89. }
  90. else /* not support */
  91. {
  92. return -RT_EINVAL;
  93. }
  94. if (cfg->parity == PARITY_NONE)
  95. {
  96. uart->handle.Init.Parity = UART_PARITY_NONE;
  97. }
  98. else if (cfg->parity == PARITY_ODD)
  99. {
  100. uart->handle.Init.Parity = UART_PARITY_ODD;
  101. }
  102. else if (cfg->parity == PARITY_EVEN)
  103. {
  104. uart->handle.Init.Parity = UART_PARITY_EVEN;
  105. }
  106. else /* not support */
  107. {
  108. return -RT_EINVAL;
  109. }
  110. uart->handle.Init.Mode = UART_MODE_TX_RX;
  111. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  112. HAL_UART_Init(&uart->handle);
  113. uart->handle.Instance->LCRH &= ~UART_LCRH_FEN;
  114. return RT_EOK;
  115. }
  116. static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  117. {
  118. struct acm32_uart *uart;
  119. #ifdef RT_SERIAL_USING_DMA
  120. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  121. #endif
  122. RT_ASSERT(serial != RT_NULL);
  123. uart = rt_container_of(serial, struct acm32_uart, serial);
  124. switch (cmd)
  125. {
  126. /* disable interrupt */
  127. case RT_DEVICE_CTRL_CLR_INT:
  128. NVIC_DisableIRQ(uart->config->irq_type);
  129. /* Disable RX interrupt */
  130. uart->handle.Instance->IE &= ~UART_IE_RXI;
  131. break;
  132. /* enable interrupt */
  133. case RT_DEVICE_CTRL_SET_INT:
  134. NVIC_EnableIRQ(uart->config->irq_type);
  135. /* Enable RX interrupt */
  136. uart->handle.Instance->IE |= UART_IE_RXI;
  137. break;
  138. #ifdef RT_SERIAL_USING_DMA
  139. /* UART config */
  140. case RT_DEVICE_CTRL_CONFIG :
  141. DMA_Configuration(serial, (rt_uint32_t)ctrl_arg);
  142. rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb);
  143. break;
  144. #endif /* RT_SERIAL_USING_DMA */
  145. }
  146. return RT_EOK;
  147. }
  148. static int _uart_putc(struct rt_serial_device *serial, char c)
  149. {
  150. struct acm32_uart *uart;
  151. RT_ASSERT(serial != RT_NULL);
  152. uart = rt_container_of(serial, struct acm32_uart, serial);
  153. while (uart->handle.Instance->FR & UART_FR_TXFF); /* wait Tx FIFO not full */
  154. uart->handle.Instance->DR = c;
  155. while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */
  156. return 1;
  157. }
  158. static int _uart_getc(struct rt_serial_device *serial)
  159. {
  160. struct acm32_uart *uart;
  161. int ch;
  162. RT_ASSERT(serial != RT_NULL);
  163. uart = rt_container_of(serial, struct acm32_uart, serial);
  164. ch = -1;
  165. if (!(uart->handle.Instance->FR & UART_FR_RXFE)) /* Rx FIFO not empty */
  166. {
  167. ch = uart->handle.Instance->DR & 0xff;
  168. }
  169. return ch;
  170. }
  171. #ifdef RT_SERIAL_USING_DMA
  172. /**
  173. * Serial port receive idle process. This need add to uart idle ISR.
  174. *
  175. * @param serial serial device
  176. */
  177. static void dma_uart_rx_idle_isr(struct rt_serial_device *serial)
  178. {
  179. struct acm32_uart *uart;
  180. RT_ASSERT(serial != RT_NULL);
  181. uart = rt_container_of(serial, struct acm32_uart, serial);
  182. rt_size_t recv_total_index, recv_len;
  183. rt_base_t level;
  184. /* disable interrupt */
  185. level = rt_hw_interrupt_disable();
  186. recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
  187. recv_len = recv_total_index - uart->handle.lu32_RxCount;
  188. uart->handle.lu32_RxCount = recv_total_index;
  189. /* enable interrupt */
  190. rt_hw_interrupt_enable(level);
  191. if (recv_len)
  192. {
  193. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  194. }
  195. }
  196. /*
  197. DMA receive done process. This need add to DMA receive done ISR.
  198. @param serial serial device
  199. */
  200. static void dma_rx_done_isr(struct rt_serial_device *serial)
  201. {
  202. struct acm32_uart *uart;
  203. struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  204. RT_ASSERT(serial != RT_NULL);
  205. uart = rt_container_of(serial, struct acm32_uart, serial);
  206. rt_size_t recv_len;
  207. rt_base_t level;
  208. /* disable interrupt */
  209. level = rt_hw_interrupt_disable();
  210. recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
  211. uart->dma_rx.last_index = 0;
  212. DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel); /* clear channel0 TC flag */
  213. /* enable interrupt */
  214. rt_hw_interrupt_enable(level);
  215. if (recv_len)
  216. {
  217. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  218. }
  219. HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz);
  220. }
  221. static rt_size_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  222. {
  223. struct acm32_uart *uart;
  224. RT_ASSERT(serial != RT_NULL);
  225. uart = rt_container_of(serial, struct acm32_uart, serial);
  226. if (size == 0)
  227. {
  228. return 0;
  229. }
  230. if (RT_SERIAL_DMA_TX == direction)
  231. {
  232. if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
  233. {
  234. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  235. return size;
  236. }
  237. else
  238. {
  239. return 0;
  240. }
  241. }
  242. return 0;
  243. }
  244. #endif /* RT_SERIAL_USING_DMA */
  245. static const struct rt_uart_ops acm32_uart_ops =
  246. {
  247. _uart_configure,
  248. _uart_control,
  249. _uart_putc,
  250. _uart_getc,
  251. #ifdef RT_SERIAL_USING_DMA
  252. _uart_dma_transmit,
  253. #endif
  254. };
  255. #ifdef RT_SERIAL_USING_DMA
  256. static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag)
  257. {
  258. struct rt_serial_rx_fifo *rx_fifo;
  259. DMA_HandleTypeDef *DMA_Handle;
  260. struct dma_config *dma_config;
  261. struct acm32_uart *uart;
  262. RT_ASSERT(serial != RT_NULL);
  263. uart = rt_container_of(serial, struct acm32_uart, serial);
  264. if (RT_DEVICE_FLAG_DMA_RX == flag)
  265. {
  266. DMA_Handle = &uart->dma_rx.handle;
  267. dma_config = uart->config->dma_rx;
  268. }
  269. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  270. {
  271. DMA_Handle = &uart->dma_tx.handle;
  272. dma_config = uart->config->dma_tx;
  273. }
  274. else
  275. {
  276. return;
  277. }
  278. DMA_Handle->Instance = dma_config->Instance;
  279. if (RT_DEVICE_FLAG_DMA_RX == flag)
  280. {
  281. DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_P2M;
  282. DMA_Handle->Init.Mode = DMA_NORMAL;
  283. DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE;
  284. DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE;
  285. }
  286. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  287. {
  288. DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_M2P;
  289. DMA_Handle->Init.Mode = DMA_NORMAL;
  290. DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_ENABLE;
  291. DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_DISABLE;
  292. }
  293. DMA_Handle->Init.Request_ID = dma_config->request;
  294. DMA_Handle->Init.Source_Width = DMA_SRC_WIDTH_BYTE;
  295. DMA_Handle->Init.Desination_Width = DMA_DST_WIDTH_BYTE;
  296. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  297. {
  298. RT_ASSERT(0);
  299. }
  300. if (RT_DEVICE_FLAG_DMA_RX == flag)
  301. {
  302. __HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle);
  303. }
  304. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  305. {
  306. __HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle);
  307. }
  308. /* enable interrupt */
  309. if (flag == RT_DEVICE_FLAG_DMA_RX)
  310. {
  311. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  312. /* Start DMA transfer */
  313. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
  314. {
  315. /* Transfer error in reception process */
  316. RT_ASSERT(0);
  317. }
  318. }
  319. }
  320. #endif /* RT_SERIAL_USING_DMA */
  321. enum
  322. {
  323. #ifdef BSP_USING_UART1
  324. UART1_INDEX,
  325. #endif
  326. #ifdef BSP_USING_UART2
  327. UART2_INDEX,
  328. #endif
  329. #ifdef BSP_USING_UART3
  330. UART3_INDEX,
  331. #endif
  332. #ifdef BSP_USING_UART4
  333. UART4_INDEX,
  334. #endif
  335. UART_MAX_INDEX,
  336. };
  337. static struct acm32_uart_config uart_config[] =
  338. {
  339. #ifdef BSP_USING_UART1
  340. UART1_CONFIG,
  341. #endif
  342. #ifdef BSP_USING_UART2
  343. UART2_CONFIG,
  344. #endif
  345. #ifdef BSP_USING_UART3
  346. UART3_CONFIG,
  347. #endif
  348. #ifdef BSP_USING_UART4
  349. UART4_CONFIG,
  350. #endif
  351. };
  352. static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  353. #ifdef RT_SERIAL_USING_DMA
  354. static void uart_get_dma_config(void)
  355. {
  356. #if defined(BSP_USING_UART1)
  357. #if defined(BSP_UART1_RX_USING_DMA)
  358. static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG;
  359. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  360. uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf;
  361. #endif /* BSP_UART1_RX_USING_DMA */
  362. #if defined(BSP_UART1_TX_USING_DMA)
  363. static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG;
  364. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  365. uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf;
  366. #endif /* BSP_UART1_TX_USING_DMA */
  367. #endif /* BSP_USING_UART1 */
  368. #if defined(BSP_USING_UART2)
  369. #if defined(BSP_UART2_RX_USING_DMA)
  370. static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG;
  371. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  372. uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf;
  373. #endif /* BSP_UART2_RX_USING_DMA */
  374. #if defined(BSP_UART2_TX_USING_DMA)
  375. static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG;
  376. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  377. uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf;
  378. #endif /* BSP_UART2_TX_USING_DMA */
  379. #endif /* BSP_USING_UART2 */
  380. #if defined(BSP_USING_UART3)
  381. #if defined(BSP_UART3_RX_USING_DMA)
  382. static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG;
  383. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  384. uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf;
  385. #endif /* BSP_UART3_RX_USING_DMA */
  386. #if defined(BSP_UART3_TX_USING_DMA)
  387. static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG;
  388. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  389. uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf;
  390. #endif /* BSP_UART3_TX_USING_DMA */
  391. #endif /* BSP_USING_UART3 */
  392. #if defined(BSP_USING_UART4)
  393. #if defined(BSP_UART4_RX_USING_DMA)
  394. static struct dma_config uart4_rx_dma_conf = UART4_DMA_RX_CONFIG;
  395. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  396. uart_config[UART4_INDEX].dma_rx = &uart4_rx_dma_conf;
  397. #endif /* BSP_UART4_RX_USING_DMA */
  398. #if defined(BSP_UART3_TX_USING_DMA)
  399. static struct dma_config uart4_tx_dma_conf = UART4_DMA_TX_CONFIG;
  400. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  401. uart_config[UART4_INDEX].dma_tx = &uart4_tx_dma_conf;
  402. #endif /* BSP_UART4_TX_USING_DMA */
  403. #endif /* BSP_USING_UART4 */
  404. }
  405. #endif
  406. rt_err_t rt_hw_uart_init(void)
  407. {
  408. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart);
  409. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  410. rt_err_t rc = RT_EOK;
  411. #ifdef RT_SERIAL_USING_DMA
  412. uart_get_dma_config();
  413. #endif
  414. for (int i = 0; i < obj_num; i++)
  415. {
  416. uart_obj[i].config = &uart_config[i];
  417. uart_obj[i].serial.ops = &acm32_uart_ops;
  418. uart_obj[i].serial.config = config;
  419. /* register UART device */
  420. rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
  421. RT_DEVICE_FLAG_RDWR
  422. | RT_DEVICE_FLAG_INT_RX
  423. | RT_DEVICE_FLAG_INT_TX
  424. | uart_obj[i].uart_dma_flag
  425. , NULL);
  426. RT_ASSERT(rc == RT_EOK);
  427. }
  428. return rc;
  429. }
  430. static void uart_isr(struct rt_serial_device *serial)
  431. {
  432. struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial);
  433. RT_ASSERT(serial != RT_NULL);
  434. /* receive interrupt enabled */
  435. if (uart->handle.Instance->IE & UART_IE_RXI)
  436. {
  437. if (uart->handle.Instance->RIS & UART_RIS_RXI)
  438. {
  439. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  440. }
  441. }
  442. #ifdef RT_SERIAL_USING_DMA
  443. if (uart->handle.Instance->IE & UART_IE_RTI) /* Receive TimeOut Interrupt */
  444. {
  445. dma_uart_rx_idle_isr(serial);
  446. /* Clear RTI Status */
  447. uart->handle.Instance->ICR = UART_ICR_RTI;
  448. }
  449. #endif /* RT_SERIAL_USING_DMA */
  450. if (uart->handle.Instance->IE & UART_IE_TXI && \
  451. uart->handle.Instance->RIS & UART_RIS_TXI)
  452. {
  453. /* Clear TXI Status */
  454. uart->handle.Instance->ICR = UART_ICR_TXI;
  455. if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
  456. {
  457. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  458. }
  459. /* Disable TX interrupt */
  460. uart->handle.Instance->IE &= ~UART_IE_TXI;
  461. }
  462. }
  463. #if defined(BSP_USING_UART1)
  464. void UART1_IRQHandler(void)
  465. {
  466. /* enter interrupt */
  467. rt_interrupt_enter();
  468. uart_isr(&uart_obj[UART1_INDEX].serial);
  469. /* leave interrupt */
  470. rt_interrupt_leave();
  471. }
  472. #endif /* BSP_USING_UART1 */
  473. #if defined(BSP_USING_UART2)
  474. void UART2_IRQHandler(void)
  475. {
  476. /* enter interrupt */
  477. rt_interrupt_enter();
  478. uart_isr(&uart_obj[UART2_INDEX].serial);
  479. /* leave interrupt */
  480. rt_interrupt_leave();
  481. }
  482. #endif /* BSP_USING_UART2 */
  483. #if defined(BSP_USING_UART3)
  484. void UART3_IRQHandler(void)
  485. {
  486. /* enter interrupt */
  487. rt_interrupt_enter();
  488. uart_isr(&uart_obj[UART3_INDEX].serial);
  489. /* leave interrupt */
  490. rt_interrupt_leave();
  491. }
  492. #endif /* BSP_USING_UART3 */
  493. #if defined(BSP_USING_UART4)
  494. void UART4_IRQHandler(void)
  495. {
  496. /* enter interrupt */
  497. rt_interrupt_enter();
  498. uart_isr(&uart_obj[UART4_INDEX].serial);
  499. /* leave interrupt */
  500. rt_interrupt_leave();
  501. }
  502. #endif /* BSP_USING_UART4 */
  503. #ifdef RT_SERIAL_USING_DMA
  504. void DMA_IRQHandler(void)
  505. {
  506. /* enter interrupt */
  507. rt_interrupt_enter();
  508. for (int i = 0; i < UART_MAX_INDEX; i++)
  509. {
  510. if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel))
  511. {
  512. dma_rx_done_isr(&uart_obj[i].serial);
  513. break;
  514. }
  515. if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel))
  516. {
  517. DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel); /* clear channel0 TC flag */
  518. break;
  519. }
  520. }
  521. /* leave interrupt */
  522. rt_interrupt_leave();
  523. }
  524. #endif /* RT_SERIAL_USING_DMA */
  525. void HAL_UART_MspInit(UART_HandleTypeDef *huart)
  526. {
  527. struct acm32_uart *uart;
  528. GPIO_InitTypeDef GPIO_Uart;
  529. RT_ASSERT(huart != RT_NULL);
  530. /* get uart object */
  531. uart = rt_container_of(huart, struct acm32_uart, handle);
  532. /* Enable Clock */
  533. System_Module_Enable(uart->config->enable_id);
  534. /* Initialization GPIO */
  535. GPIO_Uart.Pin = uart->config->tx_pin;
  536. GPIO_Uart.Mode = GPIO_MODE_AF_PP;
  537. GPIO_Uart.Pull = GPIO_PULLUP;
  538. GPIO_Uart.Alternate = GPIO_FUNCTION_2;
  539. HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart);
  540. GPIO_Uart.Pin = uart->config->rx_pin;
  541. GPIO_Uart.Mode = GPIO_MODE_AF_PP;
  542. GPIO_Uart.Pull = GPIO_PULLUP;
  543. GPIO_Uart.Alternate = GPIO_FUNCTION_2;
  544. HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart);
  545. /* NVIC Config */
  546. NVIC_ClearPendingIRQ(uart->config->irq_type);
  547. NVIC_SetPriority(uart->config->irq_type, 5);
  548. NVIC_EnableIRQ(uart->config->irq_type);
  549. }
  550. #endif /* RT_USING_SEARIAL */