drv_pwm.c 14 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-13 zylx first version
  9. */
  10. #include <board.h>
  11. #ifdef RT_USING_PWM
  12. #include "drv_config.h"
  13. //#define DRV_DEBUG
  14. #define LOG_TAG "drv.pwm"
  15. #include <drv_log.h>
  16. #define MAX_PERIOD 65535
  17. #define MIN_PERIOD 3
  18. #define MIN_PULSE 2
  19. extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
  20. enum
  21. {
  22. #ifdef BSP_USING_PWM1
  23. PWM1_INDEX,
  24. #endif
  25. #ifdef BSP_USING_PWM2
  26. PWM2_INDEX,
  27. #endif
  28. #ifdef BSP_USING_PWM3
  29. PWM3_INDEX,
  30. #endif
  31. #ifdef BSP_USING_PWM4
  32. PWM4_INDEX,
  33. #endif
  34. #ifdef BSP_USING_PWM5
  35. PWM5_INDEX,
  36. #endif
  37. #ifdef BSP_USING_PWM6
  38. PWM6_INDEX,
  39. #endif
  40. #ifdef BSP_USING_PWM7
  41. PWM7_INDEX,
  42. #endif
  43. #ifdef BSP_USING_PWM8
  44. PWM8_INDEX,
  45. #endif
  46. #ifdef BSP_USING_PWM9
  47. PWM9_INDEX,
  48. #endif
  49. #ifdef BSP_USING_PWM10
  50. PWM10_INDEX,
  51. #endif
  52. #ifdef BSP_USING_PWM11
  53. PWM11_INDEX,
  54. #endif
  55. #ifdef BSP_USING_PWM12
  56. PWM12_INDEX,
  57. #endif
  58. #ifdef BSP_USING_PWM13
  59. PWM13_INDEX,
  60. #endif
  61. #ifdef BSP_USING_PWM14
  62. PWM14_INDEX,
  63. #endif
  64. #ifdef BSP_USING_PWM15
  65. PWM15_INDEX,
  66. #endif
  67. #ifdef BSP_USING_PWM16
  68. PWM16_INDEX,
  69. #endif
  70. #ifdef BSP_USING_PWM17
  71. PWM17_INDEX,
  72. #endif
  73. };
  74. struct stm32_pwm
  75. {
  76. struct rt_device_pwm pwm_device;
  77. TIM_HandleTypeDef tim_handle;
  78. rt_uint8_t channel;
  79. char *name;
  80. };
  81. static struct stm32_pwm stm32_pwm_obj[] =
  82. {
  83. #ifdef BSP_USING_PWM1
  84. PWM1_CONFIG,
  85. #endif
  86. #ifdef BSP_USING_PWM2
  87. PWM2_CONFIG,
  88. #endif
  89. #ifdef BSP_USING_PWM3
  90. PWM3_CONFIG,
  91. #endif
  92. #ifdef BSP_USING_PWM4
  93. PWM4_CONFIG,
  94. #endif
  95. #ifdef BSP_USING_PWM5
  96. PWM5_CONFIG,
  97. #endif
  98. #ifdef BSP_USING_PWM6
  99. PWM6_CONFIG,
  100. #endif
  101. #ifdef BSP_USING_PWM7
  102. PWM7_CONFIG,
  103. #endif
  104. #ifdef BSP_USING_PWM8
  105. PWM8_CONFIG,
  106. #endif
  107. #ifdef BSP_USING_PWM9
  108. PWM9_CONFIG,
  109. #endif
  110. #ifdef BSP_USING_PWM10
  111. PWM10_CONFIG,
  112. #endif
  113. #ifdef BSP_USING_PWM11
  114. PWM11_CONFIG,
  115. #endif
  116. #ifdef BSP_USING_PWM12
  117. PWM12_CONFIG,
  118. #endif
  119. #ifdef BSP_USING_PWM13
  120. PWM13_CONFIG,
  121. #endif
  122. #ifdef BSP_USING_PWM14
  123. PWM14_CONFIG,
  124. #endif
  125. #ifdef BSP_USING_PWM15
  126. PWM15_CONFIG,
  127. #endif
  128. #ifdef BSP_USING_PWM16
  129. PWM16_CONFIG,
  130. #endif
  131. #ifdef BSP_USING_PWM17
  132. PWM17_CONFIG,
  133. #endif
  134. };
  135. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
  136. static struct rt_pwm_ops drv_ops =
  137. {
  138. drv_pwm_control
  139. };
  140. static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
  141. {
  142. /* Converts the channel number to the channel number of Hal library */
  143. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  144. if (!enable)
  145. {
  146. HAL_TIM_PWM_Stop(htim, channel);
  147. }
  148. else
  149. {
  150. HAL_TIM_PWM_Start(htim, channel);
  151. }
  152. return RT_EOK;
  153. }
  154. static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  155. {
  156. /* Converts the channel number to the channel number of Hal library */
  157. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  158. rt_uint64_t tim_clock;
  159. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  160. if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
  161. #elif defined(SOC_SERIES_STM32L4)
  162. if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
  163. #elif defined(SOC_SERIES_STM32MP1)
  164. if (htim->Instance == TIM4)
  165. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  166. if (0)
  167. #endif
  168. {
  169. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  170. tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
  171. #endif
  172. }
  173. else
  174. {
  175. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  176. tim_clock = HAL_RCC_GetPCLK1Freq();
  177. #else
  178. tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
  179. #endif
  180. }
  181. if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
  182. {
  183. tim_clock = tim_clock / 2;
  184. }
  185. else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
  186. {
  187. tim_clock = tim_clock / 4;
  188. }
  189. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  190. tim_clock /= 1000000UL;
  191. configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  192. configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  193. return RT_EOK;
  194. }
  195. static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  196. {
  197. rt_uint32_t period, pulse;
  198. rt_uint64_t tim_clock, psc;
  199. /* Converts the channel number to the channel number of Hal library */
  200. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  201. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  202. if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
  203. #elif defined(SOC_SERIES_STM32L4)
  204. if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
  205. #elif defined(SOC_SERIES_STM32MP1)
  206. if (htim->Instance == TIM4)
  207. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  208. if (0)
  209. #endif
  210. {
  211. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  212. tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
  213. #endif
  214. }
  215. else
  216. {
  217. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  218. tim_clock = HAL_RCC_GetPCLK1Freq();
  219. #else
  220. tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
  221. #endif
  222. }
  223. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  224. tim_clock /= 1000000UL;
  225. period = (unsigned long long)configuration->period * tim_clock / 1000ULL ;
  226. psc = period / MAX_PERIOD + 1;
  227. period = period / psc;
  228. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  229. if (period < MIN_PERIOD)
  230. {
  231. period = MIN_PERIOD;
  232. }
  233. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  234. pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL;
  235. if (pulse < MIN_PULSE)
  236. {
  237. pulse = MIN_PULSE;
  238. }
  239. else if (pulse > period)
  240. {
  241. pulse = period;
  242. }
  243. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  244. __HAL_TIM_SET_COUNTER(htim, 0);
  245. /* Update frequency value */
  246. HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE);
  247. return RT_EOK;
  248. }
  249. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
  250. {
  251. struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
  252. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
  253. switch (cmd)
  254. {
  255. case PWM_CMD_ENABLE:
  256. return drv_pwm_enable(htim, configuration, RT_TRUE);
  257. case PWM_CMD_DISABLE:
  258. return drv_pwm_enable(htim, configuration, RT_FALSE);
  259. case PWM_CMD_SET:
  260. return drv_pwm_set(htim, configuration);
  261. case PWM_CMD_GET:
  262. return drv_pwm_get(htim, configuration);
  263. default:
  264. return RT_EINVAL;
  265. }
  266. }
  267. static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
  268. {
  269. rt_err_t result = RT_EOK;
  270. TIM_HandleTypeDef *tim = RT_NULL;
  271. TIM_OC_InitTypeDef oc_config = {0};
  272. TIM_MasterConfigTypeDef master_config = {0};
  273. TIM_ClockConfigTypeDef clock_config = {0};
  274. RT_ASSERT(device != RT_NULL);
  275. tim = (TIM_HandleTypeDef *)&device->tim_handle;
  276. /* configure the timer to pwm mode */
  277. tim->Init.Prescaler = 0;
  278. tim->Init.CounterMode = TIM_COUNTERMODE_UP;
  279. tim->Init.Period = 0;
  280. tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  281. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
  282. tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  283. #endif
  284. if (HAL_TIM_PWM_Init(tim) != HAL_OK)
  285. {
  286. LOG_E("%s pwm init failed", device->name);
  287. result = -RT_ERROR;
  288. goto __exit;
  289. }
  290. clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  291. if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
  292. {
  293. LOG_E("%s clock init failed", device->name);
  294. result = -RT_ERROR;
  295. goto __exit;
  296. }
  297. master_config.MasterOutputTrigger = TIM_TRGO_RESET;
  298. master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  299. if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
  300. {
  301. LOG_E("%s master config failed", device->name);
  302. result = -RT_ERROR;
  303. goto __exit;
  304. }
  305. oc_config.OCMode = TIM_OCMODE_PWM1;
  306. oc_config.Pulse = 0;
  307. oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
  308. oc_config.OCFastMode = TIM_OCFAST_DISABLE;
  309. oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  310. oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
  311. /* config pwm channel */
  312. if (device->channel & 0x01)
  313. {
  314. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
  315. {
  316. LOG_E("%s channel1 config failed", device->name);
  317. result = -RT_ERROR;
  318. goto __exit;
  319. }
  320. }
  321. if (device->channel & 0x02)
  322. {
  323. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
  324. {
  325. LOG_E("%s channel2 config failed", device->name);
  326. result = -RT_ERROR;
  327. goto __exit;
  328. }
  329. }
  330. if (device->channel & 0x04)
  331. {
  332. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
  333. {
  334. LOG_E("%s channel3 config failed", device->name);
  335. result = -RT_ERROR;
  336. goto __exit;
  337. }
  338. }
  339. if (device->channel & 0x08)
  340. {
  341. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
  342. {
  343. LOG_E("%s channel4 config failed", device->name);
  344. result = -RT_ERROR;
  345. goto __exit;
  346. }
  347. }
  348. /* pwm pin configuration */
  349. HAL_TIM_MspPostInit(tim);
  350. /* enable update request source */
  351. __HAL_TIM_URS_ENABLE(tim);
  352. __exit:
  353. return result;
  354. }
  355. static void pwm_get_channel(void)
  356. {
  357. #ifdef BSP_USING_PWM1_CH1
  358. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
  359. #endif
  360. #ifdef BSP_USING_PWM1_CH2
  361. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
  362. #endif
  363. #ifdef BSP_USING_PWM1_CH3
  364. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
  365. #endif
  366. #ifdef BSP_USING_PWM1_CH4
  367. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
  368. #endif
  369. #ifdef BSP_USING_PWM2_CH1
  370. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
  371. #endif
  372. #ifdef BSP_USING_PWM2_CH2
  373. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
  374. #endif
  375. #ifdef BSP_USING_PWM2_CH3
  376. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
  377. #endif
  378. #ifdef BSP_USING_PWM2_CH4
  379. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
  380. #endif
  381. #ifdef BSP_USING_PWM3_CH1
  382. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
  383. #endif
  384. #ifdef BSP_USING_PWM3_CH2
  385. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
  386. #endif
  387. #ifdef BSP_USING_PWM3_CH3
  388. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
  389. #endif
  390. #ifdef BSP_USING_PWM3_CH4
  391. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
  392. #endif
  393. #ifdef BSP_USING_PWM4_CH1
  394. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
  395. #endif
  396. #ifdef BSP_USING_PWM4_CH2
  397. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
  398. #endif
  399. #ifdef BSP_USING_PWM4_CH3
  400. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
  401. #endif
  402. #ifdef BSP_USING_PWM4_CH4
  403. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
  404. #endif
  405. #ifdef BSP_USING_PWM5_CH1
  406. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
  407. #endif
  408. #ifdef BSP_USING_PWM5_CH2
  409. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
  410. #endif
  411. #ifdef BSP_USING_PWM5_CH3
  412. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
  413. #endif
  414. #ifdef BSP_USING_PWM5_CH4
  415. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
  416. #endif
  417. #ifdef BSP_USING_PWM6_CH1
  418. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
  419. #endif
  420. #ifdef BSP_USING_PWM6_CH2
  421. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
  422. #endif
  423. #ifdef BSP_USING_PWM6_CH3
  424. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
  425. #endif
  426. #ifdef BSP_USING_PWM6_CH4
  427. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
  428. #endif
  429. #ifdef BSP_USING_PWM7_CH1
  430. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
  431. #endif
  432. #ifdef BSP_USING_PWM7_CH2
  433. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
  434. #endif
  435. #ifdef BSP_USING_PWM7_CH3
  436. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
  437. #endif
  438. #ifdef BSP_USING_PWM7_CH4
  439. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
  440. #endif
  441. #ifdef BSP_USING_PWM8_CH1
  442. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
  443. #endif
  444. #ifdef BSP_USING_PWM8_CH2
  445. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
  446. #endif
  447. #ifdef BSP_USING_PWM8_CH3
  448. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
  449. #endif
  450. #ifdef BSP_USING_PWM8_CH4
  451. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
  452. #endif
  453. #ifdef BSP_USING_PWM9_CH1
  454. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
  455. #endif
  456. #ifdef BSP_USING_PWM9_CH2
  457. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
  458. #endif
  459. #ifdef BSP_USING_PWM9_CH3
  460. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
  461. #endif
  462. #ifdef BSP_USING_PWM9_CH4
  463. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
  464. #endif
  465. #ifdef BSP_USING_PWM12_CH1
  466. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
  467. #endif
  468. #ifdef BSP_USING_PWM12_CH2
  469. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
  470. #endif
  471. }
  472. static int stm32_pwm_init(void)
  473. {
  474. int i = 0;
  475. int result = RT_EOK;
  476. pwm_get_channel();
  477. for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
  478. {
  479. /* pwm init */
  480. if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
  481. {
  482. LOG_E("%s init failed", stm32_pwm_obj[i].name);
  483. result = -RT_ERROR;
  484. goto __exit;
  485. }
  486. else
  487. {
  488. LOG_D("%s init success", stm32_pwm_obj[i].name);
  489. /* register pwm device */
  490. if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
  491. {
  492. LOG_D("%s register success", stm32_pwm_obj[i].name);
  493. }
  494. else
  495. {
  496. LOG_E("%s register failed", stm32_pwm_obj[i].name);
  497. result = -RT_ERROR;
  498. }
  499. }
  500. }
  501. __exit:
  502. return result;
  503. }
  504. INIT_DEVICE_EXPORT(stm32_pwm_init);
  505. #endif /* RT_USING_PWM */