drv_usart_v2.c 40 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346
  1. /*
  2. * Copyright (c) 2006-2024 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-06-01 KyleChan first version
  9. */
  10. #include "board.h"
  11. #include "drv_usart_v2.h"
  12. #ifdef RT_USING_SERIAL_V2
  13. // #define DRV_DEBUG
  14. #define DBG_TAG "drv.usart"
  15. #ifdef DRV_DEBUG
  16. #define DBG_LVL DBG_LOG
  17. #else
  18. #define DBG_LVL DBG_INFO
  19. #endif /* DRV_DEBUG */
  20. #include <rtdbg.h>
  21. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  22. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  23. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  24. #error "Please define at least one BSP_USING_UARTx"
  25. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  26. #endif
  27. #ifdef RT_SERIAL_USING_DMA
  28. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  29. #endif
  30. enum
  31. {
  32. #ifdef BSP_USING_UART1
  33. UART1_INDEX,
  34. #endif
  35. #ifdef BSP_USING_UART2
  36. UART2_INDEX,
  37. #endif
  38. #ifdef BSP_USING_UART3
  39. UART3_INDEX,
  40. #endif
  41. #ifdef BSP_USING_UART4
  42. UART4_INDEX,
  43. #endif
  44. #ifdef BSP_USING_UART5
  45. UART5_INDEX,
  46. #endif
  47. #ifdef BSP_USING_UART6
  48. UART6_INDEX,
  49. #endif
  50. #ifdef BSP_USING_UART7
  51. UART7_INDEX,
  52. #endif
  53. #ifdef BSP_USING_UART8
  54. UART8_INDEX,
  55. #endif
  56. #ifdef BSP_USING_LPUART1
  57. LPUART1_INDEX,
  58. #endif
  59. };
  60. static struct stm32_uart_config uart_config[] =
  61. {
  62. #ifdef BSP_USING_UART1
  63. UART1_CONFIG,
  64. #endif
  65. #ifdef BSP_USING_UART2
  66. UART2_CONFIG,
  67. #endif
  68. #ifdef BSP_USING_UART3
  69. UART3_CONFIG,
  70. #endif
  71. #ifdef BSP_USING_UART4
  72. UART4_CONFIG,
  73. #endif
  74. #ifdef BSP_USING_UART5
  75. UART5_CONFIG,
  76. #endif
  77. #ifdef BSP_USING_UART6
  78. UART6_CONFIG,
  79. #endif
  80. #ifdef BSP_USING_UART7
  81. UART7_CONFIG,
  82. #endif
  83. #ifdef BSP_USING_UART8
  84. UART8_CONFIG,
  85. #endif
  86. #ifdef BSP_USING_LPUART1
  87. LPUART1_CONFIG,
  88. #endif
  89. };
  90. static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  91. static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  92. {
  93. struct stm32_uart *uart;
  94. RT_ASSERT(serial != RT_NULL);
  95. RT_ASSERT(cfg != RT_NULL);
  96. uart = rt_container_of(serial, struct stm32_uart, serial);
  97. uart->handle.Instance = uart->config->Instance;
  98. uart->handle.Init.BaudRate = cfg->baud_rate;
  99. uart->handle.Init.Mode = UART_MODE_TX_RX;
  100. #ifdef USART_CR1_OVER8
  101. uart->handle.Init.OverSampling = cfg->baud_rate > 5000000 ? UART_OVERSAMPLING_8 : UART_OVERSAMPLING_16;
  102. #else
  103. uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
  104. #endif /* USART_CR1_OVER8 */
  105. switch (cfg->data_bits)
  106. {
  107. case DATA_BITS_8:
  108. if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
  109. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  110. else
  111. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  112. break;
  113. case DATA_BITS_9:
  114. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  115. break;
  116. default:
  117. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  118. break;
  119. }
  120. switch (cfg->stop_bits)
  121. {
  122. case STOP_BITS_1:
  123. uart->handle.Init.StopBits = UART_STOPBITS_1;
  124. break;
  125. case STOP_BITS_2:
  126. uart->handle.Init.StopBits = UART_STOPBITS_2;
  127. break;
  128. default:
  129. uart->handle.Init.StopBits = UART_STOPBITS_1;
  130. break;
  131. }
  132. switch (cfg->parity)
  133. {
  134. case PARITY_NONE:
  135. uart->handle.Init.Parity = UART_PARITY_NONE;
  136. break;
  137. case PARITY_ODD:
  138. uart->handle.Init.Parity = UART_PARITY_ODD;
  139. break;
  140. case PARITY_EVEN:
  141. uart->handle.Init.Parity = UART_PARITY_EVEN;
  142. break;
  143. default:
  144. uart->handle.Init.Parity = UART_PARITY_NONE;
  145. break;
  146. }
  147. switch (cfg->flowcontrol)
  148. {
  149. case RT_SERIAL_FLOWCONTROL_NONE:
  150. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  151. break;
  152. case RT_SERIAL_FLOWCONTROL_CTSRTS:
  153. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
  154. break;
  155. default:
  156. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  157. break;
  158. }
  159. #ifdef RT_SERIAL_USING_DMA
  160. uart->dma_rx.remaining_cnt = serial->config.dma_ping_bufsz;
  161. #endif
  162. if (HAL_UART_Init(&uart->handle) != HAL_OK)
  163. {
  164. return -RT_ERROR;
  165. }
  166. return RT_EOK;
  167. }
  168. static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
  169. {
  170. struct stm32_uart *uart;
  171. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  172. RT_ASSERT(serial != RT_NULL);
  173. uart = rt_container_of(serial, struct stm32_uart, serial);
  174. if(ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
  175. {
  176. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
  177. ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
  178. else
  179. ctrl_arg = RT_DEVICE_FLAG_INT_RX;
  180. }
  181. else if(ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
  182. {
  183. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  184. ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
  185. else
  186. ctrl_arg = RT_DEVICE_FLAG_INT_TX;
  187. }
  188. switch (cmd)
  189. {
  190. /* disable interrupt */
  191. case RT_DEVICE_CTRL_CLR_INT:
  192. NVIC_DisableIRQ(uart->config->irq_type);
  193. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
  194. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  195. else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
  196. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
  197. #ifdef RT_SERIAL_USING_DMA
  198. else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  199. {
  200. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  201. HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
  202. if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
  203. {
  204. RT_ASSERT(0);
  205. }
  206. if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
  207. {
  208. RT_ASSERT(0);
  209. }
  210. }
  211. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  212. {
  213. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
  214. HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
  215. HAL_DMA_Abort(&(uart->dma_tx.handle));
  216. if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
  217. {
  218. RT_ASSERT(0);
  219. }
  220. }
  221. #endif
  222. break;
  223. case RT_DEVICE_CTRL_SET_INT:
  224. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  225. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  226. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
  227. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
  228. else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
  229. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TXE);
  230. break;
  231. case RT_DEVICE_CTRL_CONFIG:
  232. if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX))
  233. {
  234. #ifdef RT_SERIAL_USING_DMA
  235. stm32_dma_config(serial, ctrl_arg);
  236. #endif
  237. }
  238. else
  239. stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg);
  240. break;
  241. case RT_DEVICE_CHECK_OPTMODE:
  242. {
  243. if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
  244. return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
  245. else
  246. return RT_SERIAL_TX_BLOCKING_BUFFER;
  247. }
  248. case RT_DEVICE_CTRL_CLOSE:
  249. if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
  250. {
  251. RT_ASSERT(0)
  252. }
  253. break;
  254. }
  255. return RT_EOK;
  256. }
  257. static int stm32_putc(struct rt_serial_device *serial, char c)
  258. {
  259. struct stm32_uart *uart;
  260. RT_ASSERT(serial != RT_NULL);
  261. uart = rt_container_of(serial, struct stm32_uart, serial);
  262. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  263. UART_SET_TDR(&uart->handle, c);
  264. while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
  265. return 1;
  266. }
  267. rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
  268. {
  269. rt_uint32_t mask = 0;
  270. if (word_length == UART_WORDLENGTH_8B)
  271. {
  272. if (parity == UART_PARITY_NONE)
  273. {
  274. mask = 0x00FFU ;
  275. }
  276. else
  277. {
  278. mask = 0x007FU ;
  279. }
  280. }
  281. #ifdef UART_WORDLENGTH_9B
  282. else if (word_length == UART_WORDLENGTH_9B)
  283. {
  284. if (parity == UART_PARITY_NONE)
  285. {
  286. mask = 0x01FFU ;
  287. }
  288. else
  289. {
  290. mask = 0x00FFU ;
  291. }
  292. }
  293. #endif
  294. #ifdef UART_WORDLENGTH_7B
  295. else if (word_length == UART_WORDLENGTH_7B)
  296. {
  297. if (parity == UART_PARITY_NONE)
  298. {
  299. mask = 0x007FU ;
  300. }
  301. else
  302. {
  303. mask = 0x003FU ;
  304. }
  305. }
  306. else
  307. {
  308. mask = 0x0000U;
  309. }
  310. #endif
  311. return mask;
  312. }
  313. static int stm32_getc(struct rt_serial_device *serial)
  314. {
  315. int ch;
  316. struct stm32_uart *uart;
  317. RT_ASSERT(serial != RT_NULL);
  318. uart = rt_container_of(serial, struct stm32_uart, serial);
  319. ch = -1;
  320. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  321. ch = UART_GET_RDR(&uart->handle, stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity));
  322. return ch;
  323. }
  324. static rt_ssize_t stm32_transmit(struct rt_serial_device *serial,
  325. rt_uint8_t *buf,
  326. rt_size_t size,
  327. rt_uint32_t tx_flag)
  328. {
  329. struct stm32_uart *uart;
  330. RT_ASSERT(serial != RT_NULL);
  331. RT_ASSERT(buf != RT_NULL);
  332. uart = rt_container_of(serial, struct stm32_uart, serial);
  333. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  334. {
  335. HAL_UART_Transmit_DMA(&uart->handle, buf, size);
  336. return size;
  337. }
  338. stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag);
  339. return size;
  340. }
  341. #ifdef RT_SERIAL_USING_DMA
  342. static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag)
  343. {
  344. struct stm32_uart *uart;
  345. rt_size_t recv_len, counter;
  346. RT_ASSERT(serial != RT_NULL);
  347. uart = rt_container_of(serial, struct stm32_uart, serial);
  348. counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  349. if (counter <= uart->dma_rx.remaining_cnt)
  350. recv_len = uart->dma_rx.remaining_cnt - counter;
  351. else
  352. recv_len = serial->config.dma_ping_bufsz + uart->dma_rx.remaining_cnt - counter;
  353. if (recv_len)
  354. {
  355. #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
  356. rt_uint8_t *ptr = NULL;
  357. rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, &ptr);
  358. SCB_InvalidateDCache_by_Addr((uint32_t *)ptr, serial->config.dma_ping_bufsz);
  359. #endif
  360. uart->dma_rx.remaining_cnt = counter;
  361. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  362. }
  363. }
  364. #endif /* RT_SERIAL_USING_DMA */
  365. /**
  366. * Uart common interrupt process. This need add to uart ISR.
  367. *
  368. * @param serial serial device
  369. */
  370. static void uart_isr(struct rt_serial_device *serial)
  371. {
  372. struct stm32_uart *uart;
  373. RT_ASSERT(serial != RT_NULL);
  374. uart = rt_container_of(serial, struct stm32_uart, serial);
  375. /* If the Read data register is not empty and the RXNE interrupt is enabled (RDR) */
  376. if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
  377. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
  378. {
  379. char chr = UART_GET_RDR(&uart->handle, stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity));
  380. rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, &chr);
  381. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  382. }
  383. /* If the Transmit data register is empty and the TXE interrupt enable is enabled (TDR) */
  384. else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) &&
  385. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TXE)) != RESET)
  386. {
  387. rt_uint8_t put_char = 0;
  388. if (rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GETC, &put_char) == RT_EOK)
  389. {
  390. UART_SET_TDR(&uart->handle, put_char);
  391. }
  392. else
  393. {
  394. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
  395. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TC);
  396. }
  397. }
  398. else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
  399. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
  400. {
  401. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  402. {
  403. /* The HAL_UART_TxCpltCallback will be triggered */
  404. HAL_UART_IRQHandler(&(uart->handle));
  405. }
  406. else
  407. {
  408. /* Transmission complete interrupt disable ( CR1 Register) */
  409. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
  410. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  411. }
  412. /* Clear Transmission complete interrupt flag ( ISR Register ) */
  413. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  414. }
  415. #ifdef RT_SERIAL_USING_DMA
  416. else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
  417. && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
  418. {
  419. dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
  420. __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
  421. }
  422. #endif
  423. else
  424. {
  425. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
  426. {
  427. LOG_E("(%s) serial device Overrun error!", serial->parent.parent.name);
  428. __HAL_UART_CLEAR_OREFLAG(&uart->handle);
  429. }
  430. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
  431. {
  432. __HAL_UART_CLEAR_NEFLAG(&uart->handle);
  433. }
  434. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
  435. {
  436. __HAL_UART_CLEAR_FEFLAG(&uart->handle);
  437. }
  438. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
  439. {
  440. __HAL_UART_CLEAR_PEFLAG(&uart->handle);
  441. }
  442. #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
  443. && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
  444. && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \
  445. && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS)
  446. #ifdef SOC_SERIES_STM32F3
  447. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
  448. {
  449. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
  450. }
  451. #else
  452. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
  453. {
  454. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
  455. }
  456. #endif
  457. #endif
  458. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
  459. {
  460. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
  461. }
  462. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
  463. {
  464. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
  465. }
  466. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
  467. {
  468. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  469. }
  470. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  471. {
  472. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
  473. }
  474. }
  475. }
  476. #if defined(BSP_USING_UART1)
  477. void USART1_IRQHandler(void)
  478. {
  479. /* enter interrupt */
  480. rt_interrupt_enter();
  481. uart_isr(&(uart_obj[UART1_INDEX].serial));
  482. /* leave interrupt */
  483. rt_interrupt_leave();
  484. }
  485. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  486. void UART1_DMA_RX_IRQHandler(void)
  487. {
  488. /* enter interrupt */
  489. rt_interrupt_enter();
  490. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  491. /* leave interrupt */
  492. rt_interrupt_leave();
  493. }
  494. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  495. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  496. void UART1_DMA_TX_IRQHandler(void)
  497. {
  498. /* enter interrupt */
  499. rt_interrupt_enter();
  500. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  501. /* leave interrupt */
  502. rt_interrupt_leave();
  503. }
  504. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  505. #endif /* BSP_USING_UART1 */
  506. #if defined(BSP_USING_UART2)
  507. void USART2_IRQHandler(void)
  508. {
  509. /* enter interrupt */
  510. rt_interrupt_enter();
  511. uart_isr(&(uart_obj[UART2_INDEX].serial));
  512. /* leave interrupt */
  513. rt_interrupt_leave();
  514. }
  515. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  516. void UART2_DMA_RX_IRQHandler(void)
  517. {
  518. /* enter interrupt */
  519. rt_interrupt_enter();
  520. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  521. /* leave interrupt */
  522. rt_interrupt_leave();
  523. }
  524. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  525. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  526. void UART2_DMA_TX_IRQHandler(void)
  527. {
  528. /* enter interrupt */
  529. rt_interrupt_enter();
  530. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  531. /* leave interrupt */
  532. rt_interrupt_leave();
  533. }
  534. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  535. #endif /* BSP_USING_UART2 */
  536. #if defined(BSP_USING_UART3)
  537. void USART3_IRQHandler(void)
  538. {
  539. /* enter interrupt */
  540. rt_interrupt_enter();
  541. uart_isr(&(uart_obj[UART3_INDEX].serial));
  542. /* leave interrupt */
  543. rt_interrupt_leave();
  544. }
  545. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  546. void UART3_DMA_RX_IRQHandler(void)
  547. {
  548. /* enter interrupt */
  549. rt_interrupt_enter();
  550. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  551. /* leave interrupt */
  552. rt_interrupt_leave();
  553. }
  554. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  555. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  556. void UART3_DMA_TX_IRQHandler(void)
  557. {
  558. /* enter interrupt */
  559. rt_interrupt_enter();
  560. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  561. /* leave interrupt */
  562. rt_interrupt_leave();
  563. }
  564. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  565. #endif /* BSP_USING_UART3*/
  566. #if defined(BSP_USING_UART4)
  567. void UART4_IRQHandler(void)
  568. {
  569. /* enter interrupt */
  570. rt_interrupt_enter();
  571. uart_isr(&(uart_obj[UART4_INDEX].serial));
  572. /* leave interrupt */
  573. rt_interrupt_leave();
  574. }
  575. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  576. void UART4_DMA_RX_IRQHandler(void)
  577. {
  578. /* enter interrupt */
  579. rt_interrupt_enter();
  580. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  581. /* leave interrupt */
  582. rt_interrupt_leave();
  583. }
  584. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  585. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  586. void UART4_DMA_TX_IRQHandler(void)
  587. {
  588. /* enter interrupt */
  589. rt_interrupt_enter();
  590. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  591. /* leave interrupt */
  592. rt_interrupt_leave();
  593. }
  594. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  595. #endif /* BSP_USING_UART4*/
  596. #if defined(BSP_USING_UART5)
  597. void UART5_IRQHandler(void)
  598. {
  599. /* enter interrupt */
  600. rt_interrupt_enter();
  601. uart_isr(&(uart_obj[UART5_INDEX].serial));
  602. /* leave interrupt */
  603. rt_interrupt_leave();
  604. }
  605. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  606. void UART5_DMA_RX_IRQHandler(void)
  607. {
  608. /* enter interrupt */
  609. rt_interrupt_enter();
  610. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  611. /* leave interrupt */
  612. rt_interrupt_leave();
  613. }
  614. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  615. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  616. void UART5_DMA_TX_IRQHandler(void)
  617. {
  618. /* enter interrupt */
  619. rt_interrupt_enter();
  620. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  621. /* leave interrupt */
  622. rt_interrupt_leave();
  623. }
  624. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  625. #endif /* BSP_USING_UART5*/
  626. #if defined(BSP_USING_UART6)
  627. void USART6_IRQHandler(void)
  628. {
  629. /* enter interrupt */
  630. rt_interrupt_enter();
  631. uart_isr(&(uart_obj[UART6_INDEX].serial));
  632. /* leave interrupt */
  633. rt_interrupt_leave();
  634. }
  635. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  636. void UART6_DMA_RX_IRQHandler(void)
  637. {
  638. /* enter interrupt */
  639. rt_interrupt_enter();
  640. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  641. /* leave interrupt */
  642. rt_interrupt_leave();
  643. }
  644. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  645. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  646. void UART6_DMA_TX_IRQHandler(void)
  647. {
  648. /* enter interrupt */
  649. rt_interrupt_enter();
  650. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  651. /* leave interrupt */
  652. rt_interrupt_leave();
  653. }
  654. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  655. #endif /* BSP_USING_UART6*/
  656. #if defined(BSP_USING_UART7)
  657. void UART7_IRQHandler(void)
  658. {
  659. /* enter interrupt */
  660. rt_interrupt_enter();
  661. uart_isr(&(uart_obj[UART7_INDEX].serial));
  662. /* leave interrupt */
  663. rt_interrupt_leave();
  664. }
  665. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  666. void UART7_DMA_RX_IRQHandler(void)
  667. {
  668. /* enter interrupt */
  669. rt_interrupt_enter();
  670. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  671. /* leave interrupt */
  672. rt_interrupt_leave();
  673. }
  674. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  675. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  676. void UART7_DMA_TX_IRQHandler(void)
  677. {
  678. /* enter interrupt */
  679. rt_interrupt_enter();
  680. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  681. /* leave interrupt */
  682. rt_interrupt_leave();
  683. }
  684. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  685. #endif /* BSP_USING_UART7*/
  686. #if defined(BSP_USING_UART8)
  687. void UART8_IRQHandler(void)
  688. {
  689. /* enter interrupt */
  690. rt_interrupt_enter();
  691. uart_isr(&(uart_obj[UART8_INDEX].serial));
  692. /* leave interrupt */
  693. rt_interrupt_leave();
  694. }
  695. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  696. void UART8_DMA_RX_IRQHandler(void)
  697. {
  698. /* enter interrupt */
  699. rt_interrupt_enter();
  700. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  701. /* leave interrupt */
  702. rt_interrupt_leave();
  703. }
  704. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  705. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  706. void UART8_DMA_TX_IRQHandler(void)
  707. {
  708. /* enter interrupt */
  709. rt_interrupt_enter();
  710. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  711. /* leave interrupt */
  712. rt_interrupt_leave();
  713. }
  714. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  715. #endif /* BSP_USING_UART8*/
  716. #if defined(BSP_USING_LPUART1)
  717. void LPUART1_IRQHandler(void)
  718. {
  719. /* enter interrupt */
  720. rt_interrupt_enter();
  721. uart_isr(&(uart_obj[LPUART1_INDEX].serial));
  722. /* leave interrupt */
  723. rt_interrupt_leave();
  724. }
  725. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
  726. void LPUART1_DMA_RX_IRQHandler(void)
  727. {
  728. /* enter interrupt */
  729. rt_interrupt_enter();
  730. HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
  731. /* leave interrupt */
  732. rt_interrupt_leave();
  733. }
  734. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
  735. #endif /* BSP_USING_LPUART1*/
  736. #if defined(SOC_SERIES_STM32G0)
  737. #if defined(BSP_USING_UART2)
  738. #if defined(STM32G0B1xx) || defined(STM32G0C1xx)
  739. void USART2_LPUART2_IRQHandler(void)
  740. {
  741. USART2_IRQHandler();
  742. }
  743. #endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
  744. #endif /* defined(BSP_USING_UART2) */
  745. #if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
  746. || defined(BSP_USING_LPUART1)
  747. #if defined(STM32G070xx)
  748. void USART3_4_IRQHandler(void)
  749. #elif defined(STM32G071xx) || defined(STM32G081xx)
  750. void USART3_4_LPUART1_IRQHandler(void)
  751. #elif defined(STM32G0B0xx)
  752. void USART3_4_5_6_IRQHandler(void)
  753. #elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
  754. void USART3_4_5_6_LPUART1_IRQHandler(void)
  755. #endif /* defined(STM32G070xx) */
  756. {
  757. #if defined(BSP_USING_UART3)
  758. USART3_IRQHandler();
  759. #endif
  760. #if defined(BSP_USING_UART4)
  761. UART4_IRQHandler();
  762. #endif
  763. #if defined(BSP_USING_UART5)
  764. UART5_IRQHandler();
  765. #endif
  766. #if defined(BSP_USING_UART6)
  767. USART6_IRQHandler();
  768. #endif
  769. #if defined(BSP_USING_LPUART1)
  770. LPUART1_IRQHandler();
  771. #endif
  772. }
  773. #endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
  774. #if defined(RT_SERIAL_USING_DMA)
  775. void UART_DMA_RX_TX_IRQHandler(void)
  776. {
  777. #if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
  778. UART1_DMA_TX_IRQHandler();
  779. #endif
  780. #if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
  781. UART1_DMA_RX_IRQHandler();
  782. #endif
  783. #if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
  784. UART2_DMA_TX_IRQHandler();
  785. #endif
  786. #if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
  787. UART2_DMA_RX_IRQHandler();
  788. #endif
  789. }
  790. #endif /* defined(RT_SERIAL_USING_DMA) */
  791. #endif /* defined(SOC_SERIES_STM32G0) */
  792. static void stm32_uart_get_config(void)
  793. {
  794. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  795. #ifdef BSP_USING_UART1
  796. uart_obj[UART1_INDEX].serial.config = config;
  797. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  798. uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
  799. uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
  800. #ifdef BSP_UART1_RX_USING_DMA
  801. uart_obj[UART1_INDEX].serial.config.dma_ping_bufsz = BSP_UART1_DMA_PING_BUFSIZE;
  802. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  803. static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
  804. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  805. #endif
  806. #ifdef BSP_UART1_TX_USING_DMA
  807. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  808. static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
  809. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  810. #endif
  811. #endif
  812. #ifdef BSP_USING_UART2
  813. uart_obj[UART2_INDEX].serial.config = config;
  814. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  815. uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
  816. uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
  817. #ifdef BSP_UART2_RX_USING_DMA
  818. uart_obj[UART2_INDEX].serial.config.dma_ping_bufsz = BSP_UART2_DMA_PING_BUFSIZE;
  819. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  820. static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
  821. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  822. #endif
  823. #ifdef BSP_UART2_TX_USING_DMA
  824. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  825. static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
  826. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  827. #endif
  828. #endif
  829. #ifdef BSP_USING_UART3
  830. uart_obj[UART3_INDEX].serial.config = config;
  831. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  832. uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
  833. uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
  834. #ifdef BSP_UART3_RX_USING_DMA
  835. uart_obj[UART3_INDEX].serial.config.dma_ping_bufsz = BSP_UART3_DMA_PING_BUFSIZE;
  836. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  837. static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
  838. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  839. #endif
  840. #ifdef BSP_UART3_TX_USING_DMA
  841. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  842. static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
  843. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  844. #endif
  845. #endif
  846. #ifdef BSP_USING_UART4
  847. uart_obj[UART4_INDEX].serial.config = config;
  848. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  849. uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
  850. uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
  851. #ifdef BSP_UART4_RX_USING_DMA
  852. uart_obj[UART4_INDEX].serial.config.dma_ping_bufsz = BSP_UART4_DMA_PING_BUFSIZE;
  853. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  854. static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
  855. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  856. #endif
  857. #ifdef BSP_UART4_TX_USING_DMA
  858. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  859. static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
  860. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  861. #endif
  862. #endif
  863. #ifdef BSP_USING_UART5
  864. uart_obj[UART5_INDEX].serial.config = config;
  865. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  866. uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
  867. uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
  868. #ifdef BSP_UART5_RX_USING_DMA
  869. uart_obj[UART5_INDEX].serial.config.dma_ping_bufsz = BSP_UART5_DMA_PING_BUFSIZE;
  870. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  871. static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
  872. uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
  873. #endif
  874. #ifdef BSP_UART5_TX_USING_DMA
  875. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  876. static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
  877. uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
  878. #endif
  879. #endif
  880. #ifdef BSP_USING_UART6
  881. uart_obj[UART6_INDEX].serial.config = config;
  882. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  883. uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
  884. uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
  885. #ifdef BSP_UART6_RX_USING_DMA
  886. uart_obj[UART6_INDEX].serial.config.dma_ping_bufsz = BSP_UART6_DMA_PING_BUFSIZE;
  887. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  888. static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
  889. uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
  890. #endif
  891. #ifdef BSP_UART6_TX_USING_DMA
  892. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  893. static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
  894. uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
  895. #endif
  896. #endif
  897. #ifdef BSP_USING_UART7
  898. uart_obj[UART7_INDEX].serial.config = config;
  899. uart_obj[UART7_INDEX].uart_dma_flag = 0;
  900. uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
  901. uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
  902. #ifdef BSP_UART7_RX_USING_DMA
  903. uart_obj[UART7_INDEX].serial.config.dma_ping_bufsz = BSP_UART7_DMA_PING_BUFSIZE;
  904. uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  905. static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
  906. uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx;
  907. #endif
  908. #ifdef BSP_UART7_TX_USING_DMA
  909. uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  910. static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG;
  911. uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
  912. #endif
  913. #endif
  914. #ifdef BSP_USING_UART8
  915. uart_obj[UART8_INDEX].serial.config = config;
  916. uart_obj[UART8_INDEX].uart_dma_flag = 0;
  917. uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE;
  918. uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE;
  919. #ifdef BSP_UART8_RX_USING_DMA
  920. uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  921. static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG;
  922. uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx;
  923. #endif
  924. #ifdef BSP_UART8_TX_USING_DMA
  925. uart_obj[UART8_INDEX].serial.config.dma_ping_bufsz = BSP_UART8_DMA_PING_BUFSIZE;
  926. uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  927. static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG;
  928. uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
  929. #endif
  930. #endif
  931. #ifdef BSP_USING_LPUART1
  932. uart_obj[LPUART1_INDEX].serial.config = config;
  933. uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
  934. uart_obj[LPUART1_INDEX].serial.config.rx_bufsz = BSP_LPUART1_RX_BUFSIZE;
  935. uart_obj[LPUART1_INDEX].serial.config.tx_bufsz = BSP_LPUART1_TX_BUFSIZE;
  936. #ifdef BSP_LPUART1_RX_USING_DMA
  937. uart_obj[LPUART1_INDEX].serial.config.dma_ping_bufsz = BSP_LPUART1_DMA_PING_BUFSIZE;
  938. uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  939. static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
  940. uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
  941. #endif
  942. #endif
  943. }
  944. #ifdef RT_SERIAL_USING_DMA
  945. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  946. {
  947. DMA_HandleTypeDef *DMA_Handle;
  948. struct dma_config *dma_config;
  949. struct stm32_uart *uart;
  950. RT_ASSERT(serial != RT_NULL);
  951. RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
  952. uart = rt_container_of(serial, struct stm32_uart, serial);
  953. if (RT_DEVICE_FLAG_DMA_RX == flag)
  954. {
  955. DMA_Handle = &uart->dma_rx.handle;
  956. dma_config = uart->config->dma_rx;
  957. }
  958. else /* RT_DEVICE_FLAG_DMA_TX == flag */
  959. {
  960. DMA_Handle = &uart->dma_tx.handle;
  961. dma_config = uart->config->dma_tx;
  962. }
  963. LOG_D("%s dma config start", uart->config->name);
  964. {
  965. rt_uint32_t tmpreg = 0x00U;
  966. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
  967. || defined(SOC_SERIES_STM32L0)
  968. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  969. SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
  970. tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
  971. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
  972. || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
  973. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  974. SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  975. tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  976. #elif defined(SOC_SERIES_STM32MP1)
  977. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  978. SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  979. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  980. #endif
  981. #if defined(DMAMUX1) && (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB))
  982. /* enable DMAMUX clock for L4+ and G4 */
  983. __HAL_RCC_DMAMUX1_CLK_ENABLE();
  984. #elif defined(SOC_SERIES_STM32MP1)
  985. __HAL_RCC_DMAMUX_CLK_ENABLE();
  986. #endif
  987. UNUSED(tmpreg); /* To avoid compiler warnings */
  988. }
  989. if (RT_DEVICE_FLAG_DMA_RX == flag)
  990. {
  991. __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
  992. }
  993. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  994. {
  995. __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
  996. }
  997. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
  998. DMA_Handle->Instance = dma_config->Instance;
  999. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  1000. DMA_Handle->Instance = dma_config->Instance;
  1001. DMA_Handle->Init.Channel = dma_config->channel;
  1002. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
  1003. || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  1004. DMA_Handle->Instance = dma_config->Instance;
  1005. DMA_Handle->Init.Request = dma_config->request;
  1006. #endif
  1007. DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
  1008. DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
  1009. DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  1010. DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  1011. if (RT_DEVICE_FLAG_DMA_RX == flag)
  1012. {
  1013. DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
  1014. DMA_Handle->Init.Mode = DMA_CIRCULAR;
  1015. }
  1016. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  1017. {
  1018. DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
  1019. DMA_Handle->Init.Mode = DMA_NORMAL;
  1020. }
  1021. DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
  1022. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  1023. DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  1024. #endif
  1025. if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
  1026. {
  1027. RT_ASSERT(0);
  1028. }
  1029. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  1030. {
  1031. RT_ASSERT(0);
  1032. }
  1033. /* enable interrupt */
  1034. if (flag == RT_DEVICE_FLAG_DMA_RX)
  1035. {
  1036. rt_uint8_t *ptr = NULL;
  1037. rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, &ptr);
  1038. /* Start DMA transfer */
  1039. if (HAL_UART_Receive_DMA(&(uart->handle), ptr, serial->config.dma_ping_bufsz) != HAL_OK)
  1040. {
  1041. /* Transfer error in reception process */
  1042. RT_ASSERT(0);
  1043. }
  1044. CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
  1045. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
  1046. }
  1047. /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
  1048. HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
  1049. HAL_NVIC_EnableIRQ(dma_config->dma_irq);
  1050. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  1051. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  1052. LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
  1053. LOG_D("%s dma config done", uart->config->name);
  1054. }
  1055. /**
  1056. * @brief UART error callbacks
  1057. * @param huart: UART handle
  1058. * @note This example shows a simple way to report transfer error, and you can
  1059. * add your own implementation.
  1060. * @retval None
  1061. */
  1062. void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  1063. {
  1064. RT_ASSERT(huart != NULL);
  1065. struct stm32_uart *uart = (struct stm32_uart *)huart;
  1066. LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
  1067. UNUSED(uart);
  1068. }
  1069. /**
  1070. * @brief Rx Transfer completed callback
  1071. * @param huart: UART handle
  1072. * @note This example shows a simple way to report end of DMA Rx transfer, and
  1073. * you can add your own implementation.
  1074. * @retval None
  1075. */
  1076. void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  1077. {
  1078. struct stm32_uart *uart;
  1079. RT_ASSERT(huart != NULL);
  1080. uart = (struct stm32_uart *)huart;
  1081. dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG);
  1082. }
  1083. /**
  1084. * @brief Rx Half transfer completed callback
  1085. * @param huart: UART handle
  1086. * @note This example shows a simple way to report end of DMA Rx Half transfer,
  1087. * and you can add your own implementation.
  1088. * @retval None
  1089. */
  1090. void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  1091. {
  1092. struct stm32_uart *uart;
  1093. RT_ASSERT(huart != NULL);
  1094. uart = (struct stm32_uart *)huart;
  1095. dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG);
  1096. }
  1097. /**
  1098. * @brief HAL_UART_TxCpltCallback
  1099. * @param huart: UART handle
  1100. * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
  1101. * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
  1102. * @retval None
  1103. */
  1104. void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  1105. {
  1106. struct stm32_uart *uart;
  1107. struct rt_serial_device *serial;
  1108. rt_size_t trans_total_index;
  1109. rt_base_t level;
  1110. RT_ASSERT(huart != NULL);
  1111. uart = (struct stm32_uart *)huart;
  1112. serial = &uart->serial;
  1113. RT_ASSERT(serial != RT_NULL);
  1114. level = rt_hw_interrupt_disable();
  1115. trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
  1116. rt_hw_interrupt_enable(level);
  1117. if (trans_total_index) return;
  1118. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  1119. }
  1120. #endif /* RT_SERIAL_USING_DMA */
  1121. static const struct rt_uart_ops stm32_uart_ops =
  1122. {
  1123. .configure = stm32_configure,
  1124. .control = stm32_control,
  1125. .putc = stm32_putc,
  1126. .getc = stm32_getc,
  1127. .transmit = stm32_transmit
  1128. };
  1129. int rt_hw_usart_init(void)
  1130. {
  1131. rt_err_t result = 0;
  1132. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
  1133. stm32_uart_get_config();
  1134. for (rt_uint32_t i = 0; i < obj_num; i++)
  1135. {
  1136. /* init UART object */
  1137. uart_obj[i].config = &uart_config[i];
  1138. uart_obj[i].serial.ops = &stm32_uart_ops;
  1139. /* register UART device */
  1140. result = rt_hw_serial_register(&uart_obj[i].serial,
  1141. uart_obj[i].config->name,
  1142. RT_DEVICE_FLAG_RDWR,
  1143. NULL);
  1144. RT_ASSERT(result == RT_EOK);
  1145. }
  1146. return result;
  1147. }
  1148. #endif /* RT_USING_SERIAL_V2 */