board.c 72 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2009-01-05 Bernard first implementation
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "board.h"
  13. #include "pin_mux.h"
  14. #include "fsl_iomuxc.h"
  15. #include "fsl_gpio.h"
  16. #ifdef BSP_USING_DMA
  17. #include "fsl_dmamux.h"
  18. #include "fsl_edma.h"
  19. #endif
  20. #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
  21. 4 bits for subpriority */
  22. #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
  23. 3 bits for subpriority */
  24. #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
  25. 2 bits for subpriority */
  26. #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
  27. 1 bits for subpriority */
  28. #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
  29. 0 bits for subpriority */
  30. /* MPU configuration. */
  31. void BOARD_ConfigMPU(void)
  32. {
  33. #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
  34. extern uint32_t Image$$RW_m_ncache$$Base[];
  35. /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
  36. extern uint32_t Image$$RW_m_ncache_unused$$Base[];
  37. extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
  38. uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
  39. uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
  40. 0 :
  41. ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
  42. #elif defined(__MCUXPRESSO)
  43. extern uint32_t __base_NCACHE_REGION;
  44. extern uint32_t __top_NCACHE_REGION;
  45. uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
  46. uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
  47. #elif defined(__ICCARM__) || defined(__GNUC__)
  48. extern uint32_t __NCACHE_REGION_START[];
  49. extern uint32_t __NCACHE_REGION_SIZE[];
  50. uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
  51. uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
  52. #endif
  53. volatile uint32_t i = 0;
  54. /* Disable I cache and D cache */
  55. if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
  56. {
  57. SCB_DisableICache();
  58. }
  59. if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
  60. {
  61. SCB_DisableDCache();
  62. }
  63. /* Disable MPU */
  64. ARM_MPU_Disable();
  65. /* MPU configure:
  66. * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
  67. * SubRegionDisable, Size)
  68. * API in mpu_armv7.h.
  69. * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
  70. * disabled.
  71. * param AccessPermission Data access permissions, allows you to configure read/write access for User and
  72. * Privileged mode.
  73. * Use MACROS defined in mpu_armv7.h:
  74. * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
  75. * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
  76. * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
  77. * 0 x 0 0 Strongly Ordered shareable
  78. * 0 x 0 1 Device shareable
  79. * 0 0 1 0 Normal not shareable Outer and inner write
  80. * through no write allocate
  81. * 0 0 1 1 Normal not shareable Outer and inner write
  82. * back no write allocate
  83. * 0 1 1 0 Normal shareable Outer and inner write
  84. * through no write allocate
  85. * 0 1 1 1 Normal shareable Outer and inner write
  86. * back no write allocate
  87. * 1 0 0 0 Normal not shareable outer and inner
  88. * noncache
  89. * 1 1 0 0 Normal shareable outer and inner
  90. * noncache
  91. * 1 0 1 1 Normal not shareable outer and inner write
  92. * back write/read acllocate
  93. * 1 1 1 1 Normal shareable outer and inner write
  94. * back write/read acllocate
  95. * 2 x 0 0 Device not shareable
  96. * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
  97. * policy.
  98. * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
  99. * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
  100. * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
  101. * mpu_armv7.h.
  102. */
  103. /*
  104. * Add default region to deny access to whole address space to workaround speculative prefetch.
  105. * Refer to Arm errata 1013783-B for more details.
  106. *
  107. */
  108. /* Region 0 setting: Instruction access disabled, No data access permission. */
  109. MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
  110. MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
  111. /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
  112. MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
  113. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  114. /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
  115. MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
  116. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  117. #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
  118. /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
  119. MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
  120. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
  121. #endif
  122. /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
  123. MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
  124. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
  125. /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
  126. MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
  127. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
  128. /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
  129. MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
  130. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
  131. /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
  132. MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
  133. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
  134. /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
  135. MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
  136. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
  137. /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
  138. MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
  139. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
  140. while ((size >> i) > 0x1U)
  141. {
  142. i++;
  143. }
  144. if (i != 0)
  145. {
  146. /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
  147. assert(!(nonCacheStart % size));
  148. assert(size == (uint32_t)(1 << i));
  149. assert(i >= 5);
  150. /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
  151. MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
  152. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
  153. }
  154. /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
  155. MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
  156. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
  157. /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
  158. MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
  159. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
  160. /* Enable MPU */
  161. ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
  162. /* Enable I cache and D cache */
  163. SCB_EnableDCache();
  164. SCB_EnableICache();
  165. }
  166. /* This is the timer interrupt service routine. */
  167. void SysTick_Handler(void)
  168. {
  169. /* enter interrupt */
  170. rt_interrupt_enter();
  171. rt_tick_increase();
  172. /* leave interrupt */
  173. rt_interrupt_leave();
  174. }
  175. #ifdef BSP_USING_DMA
  176. void imxrt_dma_init(void)
  177. {
  178. edma_config_t config;
  179. DMAMUX_Init(DMAMUX);
  180. EDMA_GetDefaultConfig(&config);
  181. EDMA_Init(DMA0, &config);
  182. }
  183. #endif
  184. #ifdef BSP_USING_SPI
  185. void imxrt_spi_pins_init(void) {
  186. CLOCK_EnableClock(kCLOCK_Iomuxc);
  187. IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, 0U);
  188. IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, 0U);
  189. IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, 0U);
  190. IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK,0x10B0);
  191. IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO,0x10B0);
  192. IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI,0x10B0);
  193. }
  194. #endif
  195. #ifdef BSP_USING_LPUART
  196. void imxrt_uart_pins_init(void)
  197. {
  198. #ifdef BSP_USING_LPUART1
  199. IOMUXC_SetPinMux(
  200. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
  201. 0U); /* Software Input On Field: Input Path is determined by functionality */
  202. IOMUXC_SetPinMux(
  203. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
  204. 0U); /* Software Input On Field: Input Path is determined by functionality */
  205. IOMUXC_SetPinConfig(
  206. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
  207. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  208. Drive Strength Field: R0/6
  209. Speed Field: medium(100MHz)
  210. Open Drain Enable Field: Open Drain Disabled
  211. Pull / Keep Enable Field: Pull/Keeper Enabled
  212. Pull / Keep Select Field: Keeper
  213. Pull Up / Down Config. Field: 100K Ohm Pull Down
  214. Hyst. Enable Field: Hysteresis Disabled */
  215. IOMUXC_SetPinConfig(
  216. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
  217. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  218. Drive Strength Field: R0/6
  219. Speed Field: medium(100MHz)
  220. Open Drain Enable Field: Open Drain Disabled
  221. Pull / Keep Enable Field: Pull/Keeper Enabled
  222. Pull / Keep Select Field: Keeper
  223. Pull Up / Down Config. Field: 100K Ohm Pull Down
  224. Hyst. Enable Field: Hysteresis Disabled */
  225. #endif
  226. #ifdef BSP_USING_LPUART2
  227. IOMUXC_SetPinMux(
  228. IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
  229. 0U);
  230. IOMUXC_SetPinMux(
  231. IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
  232. 0U);
  233. IOMUXC_SetPinConfig(
  234. IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
  235. 0x10B0u);
  236. IOMUXC_SetPinConfig(
  237. IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
  238. 0x10B0u);
  239. #endif
  240. #ifdef BSP_USING_LPUART3
  241. IOMUXC_SetPinMux(
  242. IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
  243. 0U);
  244. IOMUXC_SetPinMux(
  245. IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
  246. 0U);
  247. IOMUXC_SetPinConfig(
  248. IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
  249. 0x10B0u);
  250. IOMUXC_SetPinConfig(
  251. IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
  252. 0x10B0u);
  253. #endif
  254. #ifdef BSP_USING_LPUART4
  255. IOMUXC_SetPinMux(
  256. IOMUXC_GPIO_B1_00_LPUART4_TX,
  257. 0U);
  258. IOMUXC_SetPinMux(
  259. IOMUXC_GPIO_B1_01_LPUART4_RX,
  260. 0U);
  261. IOMUXC_SetPinConfig(
  262. IOMUXC_GPIO_B1_00_LPUART4_TX,
  263. 0x10B0u);
  264. IOMUXC_SetPinConfig(
  265. IOMUXC_GPIO_B1_01_LPUART4_RX,
  266. 0x10B0u);
  267. #endif
  268. #ifdef BSP_USING_LPUART5
  269. IOMUXC_SetPinMux(
  270. IOMUXC_GPIO_B1_12_LPUART5_TX,
  271. 0U);
  272. IOMUXC_SetPinMux(
  273. IOMUXC_GPIO_B1_13_LPUART5_RX,
  274. 0U);
  275. IOMUXC_SetPinConfig(
  276. IOMUXC_GPIO_B1_12_LPUART5_TX,
  277. 0x10B0u);
  278. IOMUXC_SetPinConfig(
  279. IOMUXC_GPIO_B1_13_LPUART5_RX,
  280. 0x10B0u);
  281. #endif
  282. #ifdef BSP_USING_LPUART6
  283. IOMUXC_SetPinMux(
  284. IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
  285. 0U);
  286. IOMUXC_SetPinMux(
  287. IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
  288. 0U);
  289. IOMUXC_SetPinConfig(
  290. IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
  291. 0x10B0u);
  292. IOMUXC_SetPinConfig(
  293. IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
  294. 0x10B0u);
  295. #endif
  296. #ifdef BSP_USING_LPUART7
  297. IOMUXC_SetPinMux(
  298. IOMUXC_GPIO_EMC_31_LPUART7_TX,
  299. 0U);
  300. IOMUXC_SetPinMux(
  301. IOMUXC_GPIO_EMC_32_LPUART7_RX,
  302. 0U);
  303. IOMUXC_SetPinConfig(
  304. IOMUXC_GPIO_EMC_31_LPUART7_TX,
  305. 0x10B0u);
  306. IOMUXC_SetPinConfig(
  307. IOMUXC_GPIO_EMC_32_LPUART7_RX,
  308. 0x10B0u);
  309. #endif
  310. #ifdef BSP_USING_LPUART8
  311. IOMUXC_SetPinMux(
  312. IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
  313. 0U);
  314. IOMUXC_SetPinMux(
  315. IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
  316. 0U);
  317. IOMUXC_SetPinConfig(
  318. IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
  319. 0x10B0u);
  320. IOMUXC_SetPinConfig(
  321. IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
  322. 0x10B0u);
  323. #endif
  324. }
  325. #endif /* BSP_USING_LPUART */
  326. #ifdef BSP_USING_I2C
  327. static void imxrt_i2c_pins_init(void)
  328. {
  329. #ifdef BSP_USING_I2C1
  330. IOMUXC_SetPinMux(
  331. IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
  332. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
  333. IOMUXC_SetPinMux(
  334. IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
  335. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
  336. IOMUXC_SetPinConfig(
  337. IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
  338. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  339. Drive Strength Field: R0/6
  340. Speed Field: medium(100MHz)
  341. Open Drain Enable Field: Open Drain Enabled
  342. Pull / Keep Enable Field: Pull/Keeper Enabled
  343. Pull / Keep Select Field: Keeper
  344. Pull Up / Down Config. Field: 22K Ohm Pull Up
  345. Hyst. Enable Field: Hysteresis Disabled */
  346. IOMUXC_SetPinConfig(
  347. IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
  348. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  349. Drive Strength Field: R0/6
  350. Speed Field: medium(100MHz)
  351. Open Drain Enable Field: Open Drain Enabled
  352. Pull / Keep Enable Field: Pull/Keeper Enabled
  353. Pull / Keep Select Field: Keeper
  354. Pull Up / Down Config. Field: 22K Ohm Pull Up
  355. Hyst. Enable Field: Hysteresis Disabled */
  356. #endif
  357. #ifdef BSP_USING_I2C3
  358. IOMUXC_SetPinMux(
  359. IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
  360. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
  361. IOMUXC_SetPinMux(
  362. IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
  363. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
  364. IOMUXC_SetPinConfig(
  365. IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
  366. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  367. Drive Strength Field: R0/6
  368. Speed Field: medium(100MHz)
  369. Open Drain Enable Field: Open Drain Enabled
  370. Pull / Keep Enable Field: Pull/Keeper Enabled
  371. Pull / Keep Select Field: Keeper
  372. Pull Up / Down Config. Field: 22K Ohm Pull Up
  373. Hyst. Enable Field: Hysteresis Disabled */
  374. IOMUXC_SetPinConfig(
  375. IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
  376. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  377. Drive Strength Field: R0/6
  378. Speed Field: medium(100MHz)
  379. Open Drain Enable Field: Open Drain Enabled
  380. Pull / Keep Enable Field: Pull/Keeper Enabled
  381. Pull / Keep Select Field: Keeper
  382. Pull Up / Down Config. Field: 22K Ohm Pull Up
  383. Hyst. Enable Field: Hysteresis Disabled */
  384. #endif
  385. #ifdef BSP_USING_I2C4
  386. IOMUXC_SetPinMux(
  387. IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
  388. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
  389. IOMUXC_SetPinMux(
  390. IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
  391. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
  392. IOMUXC_SetPinConfig(
  393. IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
  394. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  395. Drive Strength Field: R0/6
  396. Speed Field: medium(100MHz)
  397. Open Drain Enable Field: Open Drain Enabled
  398. Pull / Keep Enable Field: Pull/Keeper Enabled
  399. Pull / Keep Select Field: Keeper
  400. Pull Up / Down Config. Field: 22K Ohm Pull Up
  401. Hyst. Enable Field: Hysteresis Disabled */
  402. IOMUXC_SetPinConfig(
  403. IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
  404. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  405. Drive Strength Field: R0/6
  406. Speed Field: medium(100MHz)
  407. Open Drain Enable Field: Open Drain Enabled
  408. Pull / Keep Enable Field: Pull/Keeper Enabled
  409. Pull / Keep Select Field: Keeper
  410. Pull Up / Down Config. Field: 22K Ohm Pull Up
  411. Hyst. Enable Field: Hysteresis Disabled */
  412. #endif
  413. }
  414. #endif /* BSP_USING_I2C */
  415. #ifdef BSP_USING_LCD
  416. static void imxrt_lcd_pins_init(void)
  417. {
  418. IOMUXC_SetPinMux(
  419. IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO_AD_B0_02 is configured as GPIO1_IO02 */
  420. 0U); /* Software Input On Field: Input Path is determined by functionality */
  421. IOMUXC_SetPinMux(
  422. IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, /* GPIO_AD_B0_11 is configured as GPIO1_IO11 */
  423. 0U); /* Software Input On Field: Input Path is determined by functionality */
  424. IOMUXC_SetPinMux(
  425. IOMUXC_GPIO_B1_15_GPIO2_IO31, /* GPIO_B1_15 is configured as GPIO2_IO31 */
  426. 0U); /* Software Input On Field: Input Path is determined by functionality */
  427. IOMUXC_SetPinMux(
  428. IOMUXC_GPIO_B0_00_LCD_CLK, /* GPIO_B0_00 is configured as LCD_CLK */
  429. 0U); /* Software Input On Field: Input Path is determined by functionality */
  430. IOMUXC_SetPinMux(
  431. IOMUXC_GPIO_B0_01_LCD_ENABLE, /* GPIO_B0_01 is configured as LCD_ENABLE */
  432. 0U); /* Software Input On Field: Input Path is determined by functionality */
  433. IOMUXC_SetPinMux(
  434. IOMUXC_GPIO_B0_02_LCD_HSYNC, /* GPIO_B0_02 is configured as LCD_HSYNC */
  435. 0U); /* Software Input On Field: Input Path is determined by functionality */
  436. IOMUXC_SetPinMux(
  437. IOMUXC_GPIO_B0_03_LCD_VSYNC, /* GPIO_B0_03 is configured as LCD_VSYNC */
  438. 0U); /* Software Input On Field: Input Path is determined by functionality */
  439. IOMUXC_SetPinMux(
  440. IOMUXC_GPIO_B0_04_LCD_DATA00, /* GPIO_B0_04 is configured as LCD_DATA00 */
  441. 0U); /* Software Input On Field: Input Path is determined by functionality */
  442. IOMUXC_SetPinMux(
  443. IOMUXC_GPIO_B0_05_LCD_DATA01, /* GPIO_B0_05 is configured as LCD_DATA01 */
  444. 0U); /* Software Input On Field: Input Path is determined by functionality */
  445. IOMUXC_SetPinMux(
  446. IOMUXC_GPIO_B0_06_LCD_DATA02, /* GPIO_B0_06 is configured as LCD_DATA02 */
  447. 0U); /* Software Input On Field: Input Path is determined by functionality */
  448. IOMUXC_SetPinMux(
  449. IOMUXC_GPIO_B0_07_LCD_DATA03, /* GPIO_B0_07 is configured as LCD_DATA03 */
  450. 0U); /* Software Input On Field: Input Path is determined by functionality */
  451. IOMUXC_SetPinMux(
  452. IOMUXC_GPIO_B0_08_LCD_DATA04, /* GPIO_B0_08 is configured as LCD_DATA04 */
  453. 0U); /* Software Input On Field: Input Path is determined by functionality */
  454. IOMUXC_SetPinMux(
  455. IOMUXC_GPIO_B0_09_LCD_DATA05, /* GPIO_B0_09 is configured as LCD_DATA05 */
  456. 0U); /* Software Input On Field: Input Path is determined by functionality */
  457. IOMUXC_SetPinMux(
  458. IOMUXC_GPIO_B0_10_LCD_DATA06, /* GPIO_B0_10 is configured as LCD_DATA06 */
  459. 0U); /* Software Input On Field: Input Path is determined by functionality */
  460. IOMUXC_SetPinMux(
  461. IOMUXC_GPIO_B0_11_LCD_DATA07, /* GPIO_B0_11 is configured as LCD_DATA07 */
  462. 0U); /* Software Input On Field: Input Path is determined by functionality */
  463. IOMUXC_SetPinMux(
  464. IOMUXC_GPIO_B0_12_LCD_DATA08, /* GPIO_B0_12 is configured as LCD_DATA08 */
  465. 0U); /* Software Input On Field: Input Path is determined by functionality */
  466. IOMUXC_SetPinMux(
  467. IOMUXC_GPIO_B0_13_LCD_DATA09, /* GPIO_B0_13 is configured as LCD_DATA09 */
  468. 0U); /* Software Input On Field: Input Path is determined by functionality */
  469. IOMUXC_SetPinMux(
  470. IOMUXC_GPIO_B0_14_LCD_DATA10, /* GPIO_B0_14 is configured as LCD_DATA10 */
  471. 0U); /* Software Input On Field: Input Path is determined by functionality */
  472. IOMUXC_SetPinMux(
  473. IOMUXC_GPIO_B0_15_LCD_DATA11, /* GPIO_B0_15 is configured as LCD_DATA11 */
  474. 0U); /* Software Input On Field: Input Path is determined by functionality */
  475. IOMUXC_SetPinMux(
  476. IOMUXC_GPIO_B1_00_LCD_DATA12, /* GPIO_B1_00 is configured as LCD_DATA12 */
  477. 0U); /* Software Input On Field: Input Path is determined by functionality */
  478. IOMUXC_SetPinMux(
  479. IOMUXC_GPIO_B1_01_LCD_DATA13, /* GPIO_B1_01 is configured as LCD_DATA13 */
  480. 0U); /* Software Input On Field: Input Path is determined by functionality */
  481. IOMUXC_SetPinMux(
  482. IOMUXC_GPIO_B1_02_LCD_DATA14, /* GPIO_B1_02 is configured as LCD_DATA14 */
  483. 0U); /* Software Input On Field: Input Path is determined by functionality */
  484. IOMUXC_SetPinMux(
  485. IOMUXC_GPIO_B1_03_LCD_DATA15, /* GPIO_B1_03 is configured as LCD_DATA15 */
  486. 0U); /* Software Input On Field: Input Path is determined by functionality */
  487. IOMUXC_SetPinConfig(
  488. IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO_AD_B0_02 PAD functional properties : */
  489. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  490. Drive Strength Field: R0/6
  491. Speed Field: medium(100MHz)
  492. Open Drain Enable Field: Open Drain Disabled
  493. Pull / Keep Enable Field: Pull/Keeper Enabled
  494. Pull / Keep Select Field: Keeper
  495. Pull Up / Down Config. Field: 100K Ohm Pull Down
  496. Hyst. Enable Field: Hysteresis Disabled */
  497. IOMUXC_SetPinConfig(
  498. IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, /* GPIO_AD_B0_11 PAD functional properties : */
  499. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  500. Drive Strength Field: R0/6
  501. Speed Field: medium(100MHz)
  502. Open Drain Enable Field: Open Drain Disabled
  503. Pull / Keep Enable Field: Pull/Keeper Enabled
  504. Pull / Keep Select Field: Keeper
  505. Pull Up / Down Config. Field: 100K Ohm Pull Down
  506. Hyst. Enable Field: Hysteresis Disabled */
  507. IOMUXC_SetPinConfig(
  508. IOMUXC_GPIO_B1_15_GPIO2_IO31, /* GPIO_B1_15 PAD functional properties : */
  509. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  510. Drive Strength Field: R0/6
  511. Speed Field: medium(100MHz)
  512. Open Drain Enable Field: Open Drain Disabled
  513. Pull / Keep Enable Field: Pull/Keeper Enabled
  514. Pull / Keep Select Field: Keeper
  515. Pull Up / Down Config. Field: 100K Ohm Pull Down
  516. Hyst. Enable Field: Hysteresis Disabled */
  517. IOMUXC_SetPinConfig(
  518. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
  519. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  520. Drive Strength Field: R0/6
  521. Speed Field: medium(100MHz)
  522. Open Drain Enable Field: Open Drain Disabled
  523. Pull / Keep Enable Field: Pull/Keeper Enabled
  524. Pull / Keep Select Field: Keeper
  525. Pull Up / Down Config. Field: 100K Ohm Pull Down
  526. Hyst. Enable Field: Hysteresis Disabled */
  527. IOMUXC_SetPinConfig(
  528. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
  529. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  530. Drive Strength Field: R0/6
  531. Speed Field: medium(100MHz)
  532. Open Drain Enable Field: Open Drain Disabled
  533. Pull / Keep Enable Field: Pull/Keeper Enabled
  534. Pull / Keep Select Field: Keeper
  535. Pull Up / Down Config. Field: 100K Ohm Pull Down
  536. Hyst. Enable Field: Hysteresis Disabled */
  537. IOMUXC_SetPinConfig(
  538. IOMUXC_GPIO_B0_00_LCD_CLK, /* GPIO_B0_00 PAD functional properties : */
  539. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  540. Drive Strength Field: R0/6
  541. Speed Field: medium(100MHz)
  542. Open Drain Enable Field: Open Drain Disabled
  543. Pull / Keep Enable Field: Pull/Keeper Enabled
  544. Pull / Keep Select Field: Pull
  545. Pull Up / Down Config. Field: 100K Ohm Pull Up
  546. Hyst. Enable Field: Hysteresis Enabled */
  547. IOMUXC_SetPinConfig(
  548. IOMUXC_GPIO_B0_01_LCD_ENABLE, /* GPIO_B0_01 PAD functional properties : */
  549. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  550. Drive Strength Field: R0/6
  551. Speed Field: medium(100MHz)
  552. Open Drain Enable Field: Open Drain Disabled
  553. Pull / Keep Enable Field: Pull/Keeper Enabled
  554. Pull / Keep Select Field: Pull
  555. Pull Up / Down Config. Field: 100K Ohm Pull Up
  556. Hyst. Enable Field: Hysteresis Enabled */
  557. IOMUXC_SetPinConfig(
  558. IOMUXC_GPIO_B0_02_LCD_HSYNC, /* GPIO_B0_02 PAD functional properties : */
  559. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  560. Drive Strength Field: R0/6
  561. Speed Field: medium(100MHz)
  562. Open Drain Enable Field: Open Drain Disabled
  563. Pull / Keep Enable Field: Pull/Keeper Enabled
  564. Pull / Keep Select Field: Pull
  565. Pull Up / Down Config. Field: 100K Ohm Pull Up
  566. Hyst. Enable Field: Hysteresis Enabled */
  567. IOMUXC_SetPinConfig(
  568. IOMUXC_GPIO_B0_03_LCD_VSYNC, /* GPIO_B0_03 PAD functional properties : */
  569. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  570. Drive Strength Field: R0/6
  571. Speed Field: medium(100MHz)
  572. Open Drain Enable Field: Open Drain Disabled
  573. Pull / Keep Enable Field: Pull/Keeper Enabled
  574. Pull / Keep Select Field: Pull
  575. Pull Up / Down Config. Field: 100K Ohm Pull Up
  576. Hyst. Enable Field: Hysteresis Enabled */
  577. IOMUXC_SetPinConfig(
  578. IOMUXC_GPIO_B0_04_LCD_DATA00, /* GPIO_B0_04 PAD functional properties : */
  579. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  580. Drive Strength Field: R0/6
  581. Speed Field: medium(100MHz)
  582. Open Drain Enable Field: Open Drain Disabled
  583. Pull / Keep Enable Field: Pull/Keeper Enabled
  584. Pull / Keep Select Field: Pull
  585. Pull Up / Down Config. Field: 100K Ohm Pull Up
  586. Hyst. Enable Field: Hysteresis Enabled */
  587. IOMUXC_SetPinConfig(
  588. IOMUXC_GPIO_B0_05_LCD_DATA01, /* GPIO_B0_05 PAD functional properties : */
  589. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  590. Drive Strength Field: R0/6
  591. Speed Field: medium(100MHz)
  592. Open Drain Enable Field: Open Drain Disabled
  593. Pull / Keep Enable Field: Pull/Keeper Enabled
  594. Pull / Keep Select Field: Pull
  595. Pull Up / Down Config. Field: 100K Ohm Pull Up
  596. Hyst. Enable Field: Hysteresis Enabled */
  597. IOMUXC_SetPinConfig(
  598. IOMUXC_GPIO_B0_06_LCD_DATA02, /* GPIO_B0_06 PAD functional properties : */
  599. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  600. Drive Strength Field: R0/6
  601. Speed Field: medium(100MHz)
  602. Open Drain Enable Field: Open Drain Disabled
  603. Pull / Keep Enable Field: Pull/Keeper Enabled
  604. Pull / Keep Select Field: Pull
  605. Pull Up / Down Config. Field: 100K Ohm Pull Up
  606. Hyst. Enable Field: Hysteresis Enabled */
  607. IOMUXC_SetPinConfig(
  608. IOMUXC_GPIO_B0_07_LCD_DATA03, /* GPIO_B0_07 PAD functional properties : */
  609. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  610. Drive Strength Field: R0/6
  611. Speed Field: medium(100MHz)
  612. Open Drain Enable Field: Open Drain Disabled
  613. Pull / Keep Enable Field: Pull/Keeper Enabled
  614. Pull / Keep Select Field: Pull
  615. Pull Up / Down Config. Field: 100K Ohm Pull Up
  616. Hyst. Enable Field: Hysteresis Enabled */
  617. IOMUXC_SetPinConfig(
  618. IOMUXC_GPIO_B0_08_LCD_DATA04, /* GPIO_B0_08 PAD functional properties : */
  619. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  620. Drive Strength Field: R0/6
  621. Speed Field: medium(100MHz)
  622. Open Drain Enable Field: Open Drain Disabled
  623. Pull / Keep Enable Field: Pull/Keeper Enabled
  624. Pull / Keep Select Field: Pull
  625. Pull Up / Down Config. Field: 100K Ohm Pull Up
  626. Hyst. Enable Field: Hysteresis Enabled */
  627. IOMUXC_SetPinConfig(
  628. IOMUXC_GPIO_B0_09_LCD_DATA05, /* GPIO_B0_09 PAD functional properties : */
  629. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  630. Drive Strength Field: R0/6
  631. Speed Field: medium(100MHz)
  632. Open Drain Enable Field: Open Drain Disabled
  633. Pull / Keep Enable Field: Pull/Keeper Enabled
  634. Pull / Keep Select Field: Pull
  635. Pull Up / Down Config. Field: 100K Ohm Pull Up
  636. Hyst. Enable Field: Hysteresis Enabled */
  637. IOMUXC_SetPinConfig(
  638. IOMUXC_GPIO_B0_10_LCD_DATA06, /* GPIO_B0_10 PAD functional properties : */
  639. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  640. Drive Strength Field: R0/6
  641. Speed Field: medium(100MHz)
  642. Open Drain Enable Field: Open Drain Disabled
  643. Pull / Keep Enable Field: Pull/Keeper Enabled
  644. Pull / Keep Select Field: Pull
  645. Pull Up / Down Config. Field: 100K Ohm Pull Up
  646. Hyst. Enable Field: Hysteresis Enabled */
  647. IOMUXC_SetPinConfig(
  648. IOMUXC_GPIO_B0_11_LCD_DATA07, /* GPIO_B0_11 PAD functional properties : */
  649. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  650. Drive Strength Field: R0/6
  651. Speed Field: medium(100MHz)
  652. Open Drain Enable Field: Open Drain Disabled
  653. Pull / Keep Enable Field: Pull/Keeper Enabled
  654. Pull / Keep Select Field: Pull
  655. Pull Up / Down Config. Field: 100K Ohm Pull Up
  656. Hyst. Enable Field: Hysteresis Enabled */
  657. IOMUXC_SetPinConfig(
  658. IOMUXC_GPIO_B0_12_LCD_DATA08, /* GPIO_B0_12 PAD functional properties : */
  659. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  660. Drive Strength Field: R0/6
  661. Speed Field: medium(100MHz)
  662. Open Drain Enable Field: Open Drain Disabled
  663. Pull / Keep Enable Field: Pull/Keeper Enabled
  664. Pull / Keep Select Field: Pull
  665. Pull Up / Down Config. Field: 100K Ohm Pull Up
  666. Hyst. Enable Field: Hysteresis Enabled */
  667. IOMUXC_SetPinConfig(
  668. IOMUXC_GPIO_B0_13_LCD_DATA09, /* GPIO_B0_13 PAD functional properties : */
  669. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  670. Drive Strength Field: R0/6
  671. Speed Field: medium(100MHz)
  672. Open Drain Enable Field: Open Drain Disabled
  673. Pull / Keep Enable Field: Pull/Keeper Enabled
  674. Pull / Keep Select Field: Pull
  675. Pull Up / Down Config. Field: 100K Ohm Pull Up
  676. Hyst. Enable Field: Hysteresis Enabled */
  677. IOMUXC_SetPinConfig(
  678. IOMUXC_GPIO_B0_14_LCD_DATA10, /* GPIO_B0_14 PAD functional properties : */
  679. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  680. Drive Strength Field: R0/6
  681. Speed Field: medium(100MHz)
  682. Open Drain Enable Field: Open Drain Disabled
  683. Pull / Keep Enable Field: Pull/Keeper Enabled
  684. Pull / Keep Select Field: Pull
  685. Pull Up / Down Config. Field: 100K Ohm Pull Up
  686. Hyst. Enable Field: Hysteresis Enabled */
  687. IOMUXC_SetPinConfig(
  688. IOMUXC_GPIO_B0_15_LCD_DATA11, /* GPIO_B0_15 PAD functional properties : */
  689. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  690. Drive Strength Field: R0/6
  691. Speed Field: medium(100MHz)
  692. Open Drain Enable Field: Open Drain Disabled
  693. Pull / Keep Enable Field: Pull/Keeper Enabled
  694. Pull / Keep Select Field: Pull
  695. Pull Up / Down Config. Field: 100K Ohm Pull Up
  696. Hyst. Enable Field: Hysteresis Enabled */
  697. IOMUXC_SetPinConfig(
  698. IOMUXC_GPIO_B1_00_LCD_DATA12, /* GPIO_B1_00 PAD functional properties : */
  699. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  700. Drive Strength Field: R0/6
  701. Speed Field: medium(100MHz)
  702. Open Drain Enable Field: Open Drain Disabled
  703. Pull / Keep Enable Field: Pull/Keeper Enabled
  704. Pull / Keep Select Field: Pull
  705. Pull Up / Down Config. Field: 100K Ohm Pull Up
  706. Hyst. Enable Field: Hysteresis Enabled */
  707. IOMUXC_SetPinConfig(
  708. IOMUXC_GPIO_B1_01_LCD_DATA13, /* GPIO_B1_01 PAD functional properties : */
  709. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  710. Drive Strength Field: R0/6
  711. Speed Field: medium(100MHz)
  712. Open Drain Enable Field: Open Drain Disabled
  713. Pull / Keep Enable Field: Pull/Keeper Enabled
  714. Pull / Keep Select Field: Pull
  715. Pull Up / Down Config. Field: 100K Ohm Pull Up
  716. Hyst. Enable Field: Hysteresis Enabled */
  717. IOMUXC_SetPinConfig(
  718. IOMUXC_GPIO_B1_02_LCD_DATA14, /* GPIO_B1_02 PAD functional properties : */
  719. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  720. Drive Strength Field: R0/6
  721. Speed Field: medium(100MHz)
  722. Open Drain Enable Field: Open Drain Disabled
  723. Pull / Keep Enable Field: Pull/Keeper Enabled
  724. Pull / Keep Select Field: Pull
  725. Pull Up / Down Config. Field: 100K Ohm Pull Up
  726. Hyst. Enable Field: Hysteresis Enabled */
  727. IOMUXC_SetPinConfig(
  728. IOMUXC_GPIO_B1_03_LCD_DATA15, /* GPIO_B1_03 PAD functional properties : */
  729. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  730. Drive Strength Field: R0/6
  731. Speed Field: medium(100MHz)
  732. Open Drain Enable Field: Open Drain Disabled
  733. Pull / Keep Enable Field: Pull/Keeper Enabled
  734. Pull / Keep Select Field: Pull
  735. Pull Up / Down Config. Field: 100K Ohm Pull Up
  736. Hyst. Enable Field: Hysteresis Enabled */
  737. }
  738. #endif
  739. #ifdef BSP_USING_ETH
  740. void imxrt_enet_pins_init(void)
  741. {
  742. CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
  743. IOMUXC_SetPinMux(
  744. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
  745. 0U); /* Software Input On Field: Input Path is determined by functionality */
  746. IOMUXC_SetPinMux(
  747. IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
  748. 0U); /* Software Input On Field: Input Path is determined by functionality */
  749. IOMUXC_SetPinMux(
  750. IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
  751. 0U); /* Software Input On Field: Input Path is determined by functionality */
  752. IOMUXC_SetPinMux(
  753. IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
  754. 0U); /* Software Input On Field: Input Path is determined by functionality */
  755. IOMUXC_SetPinMux(
  756. IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
  757. 0U); /* Software Input On Field: Input Path is determined by functionality */
  758. IOMUXC_SetPinMux(
  759. IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
  760. 0U); /* Software Input On Field: Input Path is determined by functionality */
  761. IOMUXC_SetPinMux(
  762. IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
  763. 0U); /* Software Input On Field: Input Path is determined by functionality */
  764. IOMUXC_SetPinMux(
  765. IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
  766. 0U); /* Software Input On Field: Input Path is determined by functionality */
  767. IOMUXC_SetPinMux(
  768. IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
  769. 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
  770. IOMUXC_SetPinMux(
  771. IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
  772. 0U); /* Software Input On Field: Input Path is determined by functionality */
  773. IOMUXC_SetPinMux(
  774. IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
  775. 0U); /* Software Input On Field: Input Path is determined by functionality */
  776. IOMUXC_SetPinMux(
  777. IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
  778. 0U); /* Software Input On Field: Input Path is determined by functionality */
  779. IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
  780. (~(IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */
  781. | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) /* GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: 0x00U */
  782. );
  783. IOMUXC_SetPinConfig(
  784. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
  785. 0xB0A9U); /* Slew Rate Field: Fast Slew Rate
  786. Drive Strength Field: R0/5
  787. Speed Field: medium(100MHz)
  788. Open Drain Enable Field: Open Drain Disabled
  789. Pull / Keep Enable Field: Pull/Keeper Enabled
  790. Pull / Keep Select Field: Pull
  791. Pull Up / Down Config. Field: 100K Ohm Pull Up
  792. Hyst. Enable Field: Hysteresis Disabled */
  793. IOMUXC_SetPinConfig(
  794. IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
  795. 0xB0A9U); /* Slew Rate Field: Fast Slew Rate
  796. Drive Strength Field: R0/5
  797. Speed Field: medium(100MHz)
  798. Open Drain Enable Field: Open Drain Disabled
  799. Pull / Keep Enable Field: Pull/Keeper Enabled
  800. Pull / Keep Select Field: Pull
  801. Pull Up / Down Config. Field: 100K Ohm Pull Up
  802. Hyst. Enable Field: Hysteresis Disabled */
  803. IOMUXC_SetPinConfig(
  804. IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
  805. 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
  806. Drive Strength Field: R0/5
  807. Speed Field: max(200MHz)
  808. Open Drain Enable Field: Open Drain Disabled
  809. Pull / Keep Enable Field: Pull/Keeper Enabled
  810. Pull / Keep Select Field: Pull
  811. Pull Up / Down Config. Field: 100K Ohm Pull Up
  812. Hyst. Enable Field: Hysteresis Disabled */
  813. IOMUXC_SetPinConfig(
  814. IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
  815. 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
  816. Drive Strength Field: R0/5
  817. Speed Field: max(200MHz)
  818. Open Drain Enable Field: Open Drain Disabled
  819. Pull / Keep Enable Field: Pull/Keeper Enabled
  820. Pull / Keep Select Field: Pull
  821. Pull Up / Down Config. Field: 100K Ohm Pull Up
  822. Hyst. Enable Field: Hysteresis Disabled */
  823. IOMUXC_SetPinConfig(
  824. IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
  825. 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
  826. Drive Strength Field: R0/5
  827. Speed Field: max(200MHz)
  828. Open Drain Enable Field: Open Drain Disabled
  829. Pull / Keep Enable Field: Pull/Keeper Enabled
  830. Pull / Keep Select Field: Pull
  831. Pull Up / Down Config. Field: 100K Ohm Pull Up
  832. Hyst. Enable Field: Hysteresis Disabled */
  833. IOMUXC_SetPinConfig(
  834. IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
  835. 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
  836. Drive Strength Field: R0/5
  837. Speed Field: max(200MHz)
  838. Open Drain Enable Field: Open Drain Disabled
  839. Pull / Keep Enable Field: Pull/Keeper Enabled
  840. Pull / Keep Select Field: Pull
  841. Pull Up / Down Config. Field: 100K Ohm Pull Up
  842. Hyst. Enable Field: Hysteresis Disabled */
  843. IOMUXC_SetPinConfig(
  844. IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
  845. 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
  846. Drive Strength Field: R0/5
  847. Speed Field: max(200MHz)
  848. Open Drain Enable Field: Open Drain Disabled
  849. Pull / Keep Enable Field: Pull/Keeper Enabled
  850. Pull / Keep Select Field: Pull
  851. Pull Up / Down Config. Field: 100K Ohm Pull Up
  852. Hyst. Enable Field: Hysteresis Disabled */
  853. IOMUXC_SetPinConfig(
  854. IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
  855. 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
  856. Drive Strength Field: R0/5
  857. Speed Field: max(200MHz)
  858. Open Drain Enable Field: Open Drain Disabled
  859. Pull / Keep Enable Field: Pull/Keeper Enabled
  860. Pull / Keep Select Field: Pull
  861. Pull Up / Down Config. Field: 100K Ohm Pull Up
  862. Hyst. Enable Field: Hysteresis Disabled */
  863. IOMUXC_SetPinConfig(
  864. IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
  865. 0x31U); /* Slew Rate Field: Fast Slew Rate
  866. Drive Strength Field: R0/6
  867. Speed Field: low(50MHz)
  868. Open Drain Enable Field: Open Drain Disabled
  869. Pull / Keep Enable Field: Pull/Keeper Disabled
  870. Pull / Keep Select Field: Keeper
  871. Pull Up / Down Config. Field: 100K Ohm Pull Down
  872. Hyst. Enable Field: Hysteresis Disabled */
  873. IOMUXC_SetPinConfig(
  874. IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
  875. 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
  876. Drive Strength Field: R0/5
  877. Speed Field: max(200MHz)
  878. Open Drain Enable Field: Open Drain Disabled
  879. Pull / Keep Enable Field: Pull/Keeper Enabled
  880. Pull / Keep Select Field: Pull
  881. Pull Up / Down Config. Field: 100K Ohm Pull Up
  882. Hyst. Enable Field: Hysteresis Disabled */
  883. IOMUXC_SetPinConfig(
  884. IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
  885. 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
  886. Drive Strength Field: R0/5
  887. Speed Field: max(200MHz)
  888. Open Drain Enable Field: Open Drain Disabled
  889. Pull / Keep Enable Field: Pull/Keeper Enabled
  890. Pull / Keep Select Field: Pull
  891. Pull Up / Down Config. Field: 100K Ohm Pull Up
  892. Hyst. Enable Field: Hysteresis Disabled */
  893. IOMUXC_SetPinConfig(
  894. IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
  895. 0xB829U); /* Slew Rate Field: Fast Slew Rate
  896. Drive Strength Field: R0/5
  897. Speed Field: low(50MHz)
  898. Open Drain Enable Field: Open Drain Enabled
  899. Pull / Keep Enable Field: Pull/Keeper Enabled
  900. Pull / Keep Select Field: Pull
  901. Pull Up / Down Config. Field: 100K Ohm Pull Up
  902. Hyst. Enable Field: Hysteresis Disabled */
  903. }
  904. #ifndef BSP_USING_PHY
  905. void imxrt_enet_phy_reset_by_gpio(void)
  906. {
  907. gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
  908. GPIO_PinInit(GPIO1, 9, &gpio_config);
  909. GPIO_PinInit(GPIO1, 10, &gpio_config);
  910. /* pull up the ENET_INT before RESET. */
  911. GPIO_WritePinOutput(GPIO1, 10, 1);
  912. GPIO_WritePinOutput(GPIO1, 9, 0);
  913. rt_thread_delay(100);
  914. GPIO_WritePinOutput(GPIO1, 9, 1);
  915. }
  916. #endif /* BSP_USING_PHY */
  917. #endif /* BSP_USING_ETH */
  918. #ifdef BSP_USING_PHY
  919. void imxrt_phy_pins_init( void )
  920. {
  921. IOMUXC_SetPinMux(
  922. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
  923. 0U); /* Software Input On Field: Input Path is determined by functionality */
  924. IOMUXC_SetPinConfig(
  925. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_B0_00 PAD functional properties : */
  926. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  927. Drive Strength Field: R0/6
  928. Speed Field: medium(100MHz)
  929. Open Drain Enable Field: Open Drain Disabled
  930. Pull / Keep Enable Field: Pull/Keeper Enabled
  931. Pull / Keep Select Field: Keeper
  932. Pull Up / Down Config. Field: 100K Ohm Pull Down
  933. Hyst. Enable Field: Hysteresis Disabled */
  934. }
  935. #endif /* BSP_USING_PHY */
  936. #ifdef BSP_USING_SDIO
  937. void imrt_sdio_pins_init(void)
  938. {
  939. CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
  940. IOMUXC_SetPinMux(
  941. IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, /* GPIO_AD_B0_05 is configured as GPIO1_IO05 */
  942. 0U); /* Software Input On Field: Input Path is determined by functionality */
  943. IOMUXC_SetPinMux(
  944. IOMUXC_GPIO_B1_12_GPIO2_IO28, /* GPIO_B1_12 is configured as GPIO2_IO28 */
  945. 0U); /* Software Input On Field: Input Path is determined by functionality */
  946. IOMUXC_SetPinMux(
  947. IOMUXC_GPIO_B1_14_USDHC1_VSELECT, /* GPIO_B1_14 is configured as USDHC1_VSELECT */
  948. 0U); /* Software Input On Field: Input Path is determined by functionality */
  949. IOMUXC_SetPinMux(
  950. IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, /* GPIO_SD_B0_00 is configured as USDHC1_CMD */
  951. 0U); /* Software Input On Field: Input Path is determined by functionality */
  952. IOMUXC_SetPinMux(
  953. IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, /* GPIO_SD_B0_01 is configured as USDHC1_CLK */
  954. 0U); /* Software Input On Field: Input Path is determined by functionality */
  955. IOMUXC_SetPinMux(
  956. IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, /* GPIO_SD_B0_02 is configured as USDHC1_DATA0 */
  957. 0U); /* Software Input On Field: Input Path is determined by functionality */
  958. IOMUXC_SetPinMux(
  959. IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, /* GPIO_SD_B0_03 is configured as USDHC1_DATA1 */
  960. 0U); /* Software Input On Field: Input Path is determined by functionality */
  961. IOMUXC_SetPinMux(
  962. IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, /* GPIO_SD_B0_04 is configured as USDHC1_DATA2 */
  963. 0U); /* Software Input On Field: Input Path is determined by functionality */
  964. IOMUXC_SetPinMux(
  965. IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, /* GPIO_SD_B0_05 is configured as USDHC1_DATA3 */
  966. 0U); /* Software Input On Field: Input Path is determined by functionality */
  967. IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
  968. (~(IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */
  969. | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) /* GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: 0x00U */
  970. );
  971. IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
  972. (~(IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */
  973. | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U) /* GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: 0x00U */
  974. );
  975. IOMUXC_SetPinConfig(
  976. IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, /* GPIO_AD_B0_05 PAD functional properties : */
  977. 0x10B0U); /* Slew Rate Field: Slow Slew Rate
  978. Drive Strength Field: R0/6
  979. Speed Field: medium(100MHz)
  980. Open Drain Enable Field: Open Drain Disabled
  981. Pull / Keep Enable Field: Pull/Keeper Enabled
  982. Pull / Keep Select Field: Keeper
  983. Pull Up / Down Config. Field: 100K Ohm Pull Down
  984. Hyst. Enable Field: Hysteresis Disabled */
  985. IOMUXC_SetPinConfig(
  986. IOMUXC_GPIO_B1_12_GPIO2_IO28, /* GPIO_B1_12 PAD functional properties : */
  987. 0x017089U); /* Slew Rate Field: Fast Slew Rate
  988. Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
  989. Speed Field: medium(100MHz)
  990. Open Drain Enable Field: Open Drain Disabled
  991. Pull / Keep Enable Field: Pull/Keeper Enabled
  992. Pull / Keep Select Field: Pull
  993. Pull Up / Down Config. Field: 47K Ohm Pull Up
  994. Hyst. Enable Field: Hysteresis Enabled */
  995. IOMUXC_SetPinConfig(
  996. IOMUXC_GPIO_B1_14_USDHC1_VSELECT, /* GPIO_B1_14 PAD functional properties : */
  997. 0x0170A1U); /* Slew Rate Field: Fast Slew Rate
  998. Drive Strength Field: R0/4
  999. Speed Field: medium(100MHz)
  1000. Open Drain Enable Field: Open Drain Disabled
  1001. Pull / Keep Enable Field: Pull/Keeper Enabled
  1002. Pull / Keep Select Field: Pull
  1003. Pull Up / Down Config. Field: 47K Ohm Pull Up
  1004. Hyst. Enable Field: Hysteresis Enabled */
  1005. IOMUXC_SetPinConfig(
  1006. IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, /* GPIO_SD_B0_00 PAD functional properties : */
  1007. 0x017089U); /* Slew Rate Field: Fast Slew Rate
  1008. Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
  1009. Speed Field: medium(100MHz)
  1010. Open Drain Enable Field: Open Drain Disabled
  1011. Pull / Keep Enable Field: Pull/Keeper Enabled
  1012. Pull / Keep Select Field: Pull
  1013. Pull Up / Down Config. Field: 47K Ohm Pull Up
  1014. Hyst. Enable Field: Hysteresis Enabled */
  1015. IOMUXC_SetPinConfig(
  1016. IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, /* GPIO_SD_B0_01 PAD functional properties : */
  1017. 0x014089U); /* Slew Rate Field: Fast Slew Rate
  1018. Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
  1019. Speed Field: medium(100MHz)
  1020. Open Drain Enable Field: Open Drain Disabled
  1021. Pull / Keep Enable Field: Pull/Keeper Disabled
  1022. Pull / Keep Select Field: Keeper
  1023. Pull Up / Down Config. Field: 47K Ohm Pull Up
  1024. Hyst. Enable Field: Hysteresis Enabled */
  1025. IOMUXC_SetPinConfig(
  1026. IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, /* GPIO_SD_B0_02 PAD functional properties : */
  1027. 0x017089U); /* Slew Rate Field: Fast Slew Rate
  1028. Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
  1029. Speed Field: medium(100MHz)
  1030. Open Drain Enable Field: Open Drain Disabled
  1031. Pull / Keep Enable Field: Pull/Keeper Enabled
  1032. Pull / Keep Select Field: Pull
  1033. Pull Up / Down Config. Field: 47K Ohm Pull Up
  1034. Hyst. Enable Field: Hysteresis Enabled */
  1035. IOMUXC_SetPinConfig(
  1036. IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, /* GPIO_SD_B0_03 PAD functional properties : */
  1037. 0x017089U); /* Slew Rate Field: Fast Slew Rate
  1038. Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
  1039. Speed Field: medium(100MHz)
  1040. Open Drain Enable Field: Open Drain Disabled
  1041. Pull / Keep Enable Field: Pull/Keeper Enabled
  1042. Pull / Keep Select Field: Pull
  1043. Pull Up / Down Config. Field: 47K Ohm Pull Up
  1044. Hyst. Enable Field: Hysteresis Enabled */
  1045. IOMUXC_SetPinConfig(
  1046. IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, /* GPIO_SD_B0_04 PAD functional properties : */
  1047. 0x017089U); /* Slew Rate Field: Fast Slew Rate
  1048. Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
  1049. Speed Field: medium(100MHz)
  1050. Open Drain Enable Field: Open Drain Disabled
  1051. Pull / Keep Enable Field: Pull/Keeper Enabled
  1052. Pull / Keep Select Field: Pull
  1053. Pull Up / Down Config. Field: 47K Ohm Pull Up
  1054. Hyst. Enable Field: Hysteresis Enabled */
  1055. IOMUXC_SetPinConfig(
  1056. IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, /* GPIO_SD_B0_05 PAD functional properties : */
  1057. 0x017089U); /* Slew Rate Field: Fast Slew Rate
  1058. Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
  1059. Speed Field: medium(100MHz)
  1060. Open Drain Enable Field: Open Drain Disabled
  1061. Pull / Keep Enable Field: Pull/Keeper Enabled
  1062. Pull / Keep Select Field: Pull
  1063. Pull Up / Down Config. Field: 47K Ohm Pull Up
  1064. Hyst. Enable Field: Hysteresis Enabled */
  1065. }
  1066. #endif
  1067. /*
  1068. * When PXP fetch images from FlexSPI flash, the default FlexSPI RX buffer
  1069. * configuration does not meet the PXP bandwidth requirement. Reconfigure
  1070. * here.
  1071. */
  1072. void BOARD_ReconfigFlexSpiRxBuffer(void)
  1073. {
  1074. uint32_t ahbcr;
  1075. /* Disable I cache and D cache */
  1076. if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
  1077. {
  1078. SCB_DisableICache();
  1079. }
  1080. if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
  1081. {
  1082. SCB_DisableDCache();
  1083. }
  1084. ahbcr = FLEXSPI->AHBCR;
  1085. /* Temporarily disable prefetching while changing the buffer settings */
  1086. FLEXSPI->AHBCR = ahbcr & ~(FLEXSPI_AHBCR_CACHABLEEN_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK);
  1087. /* Wait for FlexSPI idle to make sure no flash data transfer. */
  1088. while ((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) == 0U)
  1089. {
  1090. }
  1091. /* Allocate half of the prefetch buffer to the core */
  1092. FLEXSPI->AHBRXBUFCR0[0] =
  1093. FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID(0) | FLEXSPI_AHBRXBUFCR0_BUFSZ(0x40);
  1094. /* Disable dedicate prefetch buffer for DMA. */
  1095. FLEXSPI->AHBRXBUFCR0[1] =
  1096. FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID(1) | FLEXSPI_AHBRXBUFCR0_BUFSZ(0x00);
  1097. /* Disable dedicate prefetch buffer for DCP. */
  1098. FLEXSPI->AHBRXBUFCR0[2] =
  1099. FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID(2) | FLEXSPI_AHBRXBUFCR0_BUFSZ(0x00);
  1100. /* Other half of the buffer for other masters incl. PXP */
  1101. FLEXSPI->AHBRXBUFCR0[3] =
  1102. FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID(3) | FLEXSPI_AHBRXBUFCR0_BUFSZ(0x40);
  1103. FLEXSPI->AHBCR = ahbcr; /* Set AHBCR back to the original value */
  1104. /* Enable I cache and D cache */
  1105. SCB_EnableDCache();
  1106. SCB_EnableICache();
  1107. }
  1108. /**
  1109. * This function will initial rt1050 board.
  1110. */
  1111. void rt_hw_board_init()
  1112. {
  1113. /* Init board hardware. */
  1114. /* Set the eLCDIF read_qos priority high, to make sure eLCDIF
  1115. * can fetch data in time when PXP is used.
  1116. */
  1117. *((volatile uint32_t *)0x41044100) = 5;
  1118. BOARD_ConfigMPU();
  1119. // BOARD_ReconfigFlexSpiRxBuffer();
  1120. BOARD_InitPins();
  1121. BOARD_InitSemcPins();
  1122. BOARD_BootClockRUN();
  1123. NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  1124. SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  1125. #ifdef BSP_USING_LPUART
  1126. imxrt_uart_pins_init();
  1127. #endif
  1128. #ifdef BSP_USING_I2C
  1129. imxrt_i2c_pins_init();
  1130. #endif
  1131. #ifdef BSP_USING_ETH
  1132. imxrt_enet_pins_init();
  1133. #endif
  1134. #ifdef BSP_USING_PHY
  1135. imxrt_phy_pins_init();
  1136. #endif
  1137. #ifdef BSP_USING_LCD
  1138. imxrt_lcd_pins_init();
  1139. #endif
  1140. #ifdef BSP_USING_SDIO
  1141. imrt_sdio_pins_init();
  1142. #endif
  1143. #ifdef BSP_USING_DMA
  1144. imxrt_dma_init();
  1145. #endif
  1146. #ifdef RT_USING_HEAP
  1147. rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
  1148. #endif
  1149. #ifdef BSP_USING_SPI
  1150. imxrt_spi_pins_init();
  1151. #endif
  1152. #ifdef RT_USING_COMPONENTS_INIT
  1153. rt_components_board_init();
  1154. #endif
  1155. #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
  1156. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  1157. #endif
  1158. }