evkmimxrt1060_sdram_init.mac 8.9 KB

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  1. /*
  2. * Copyright 2018-2020 NXP
  3. * All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. _load_dcdc_trim()
  8. {
  9. __var dcdc_trim_loaded;
  10. __var ocotp_base;
  11. __var ocotp_fuse_bank0_base;
  12. __var dcdc_base;
  13. __var reg;
  14. __var trim_value;
  15. __var index;
  16. ocotp_base = 0x401F4000;
  17. ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
  18. dcdc_base = 0x40080000;
  19. dcdc_trim_loaded = 0;
  20. reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
  21. if (reg & (1<<10))
  22. {
  23. // DCDC: REG0->VBG_TRM
  24. trim_value = (reg & (0x1F << 11)) >> 11;
  25. reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
  26. __writeMemory32(reg, dcdc_base + 0x4, "Memory");
  27. dcdc_trim_loaded = 1;
  28. }
  29. reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
  30. if (reg & (1<<30))
  31. {
  32. index = (reg & (3 << 28)) >> 28;
  33. if (index < 4)
  34. {
  35. // DCDC: REG3->TRG
  36. reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
  37. __writeMemory32(reg, dcdc_base + 0xC, "Memory");
  38. dcdc_trim_loaded = 1;
  39. }
  40. }
  41. if (dcdc_trim_loaded)
  42. {
  43. // delay 1ms for dcdc to get stable
  44. __delay(1);
  45. __message "DCDC trim value loaded.\n";
  46. }
  47. }
  48. SDRAM_WaitIpCmdDone()
  49. {
  50. __var reg;
  51. do
  52. {
  53. reg = __readMemory32(0x402F003C, "Memory");
  54. }while((reg & 0x3) == 0);
  55. __writeMemory32(0x00000003, 0x402F003C, "Memory"); // clear IPCMDERR and IPCMDDONE bits
  56. }
  57. _clock_init()
  58. {
  59. __var reg;
  60. // Enable all clocks
  61. __writeMemory32(0xffffffff, 0x400FC068, "Memory");
  62. __writeMemory32(0xffffffff, 0x400FC06C, "Memory");
  63. __writeMemory32(0xffffffff, 0x400FC070, "Memory");
  64. __writeMemory32(0xffffffff, 0x400FC074, "Memory");
  65. __writeMemory32(0xffffffff, 0x400FC078, "Memory");
  66. __writeMemory32(0xffffffff, 0x400FC07C, "Memory");
  67. __writeMemory32(0xffffffff, 0x400FC080, "Memory");
  68. // PERCLK_PODF: 1 divide by 2
  69. __writeMemory32(0x04900001, 0x400FC01C, "Memory");
  70. // Enable SYS PLL but keep it bypassed.
  71. __writeMemory32(0x00012001, 0x400D8030, "Memory");
  72. do
  73. {
  74. reg = __readMemory32(0x400D8030, "Memory");
  75. }while((reg & 0x80000000) == 0);
  76. // Disable bypass of SYS PLL
  77. __writeMemory32(0x00002001, 0x400D8030, "Memory");
  78. // PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
  79. // Ungate SYS PLL PFD2
  80. reg = __readMemory32(0x400D8100, "Memory");
  81. reg &= ~0xBF0000;
  82. reg |= 0x1D0000;
  83. __writeMemory32(reg, 0x400D8100, "Memory");
  84. // SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
  85. // SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
  86. // SEMC_CLK_SEL: 1 SEMC_ALT_CLK
  87. __writeMemory32(0x00010D40, 0x400FC014, "Memory");
  88. __message "clock init done\n";
  89. }
  90. _sdr_Init()
  91. {
  92. // Config IOMUX
  93. __writeMemory32(0x00000000, 0x401F8014, "Memory");
  94. __writeMemory32(0x00000000, 0x401F8018, "Memory");
  95. __writeMemory32(0x00000000, 0x401F801C, "Memory");
  96. __writeMemory32(0x00000000, 0x401F8020, "Memory");
  97. __writeMemory32(0x00000000, 0x401F8024, "Memory");
  98. __writeMemory32(0x00000000, 0x401F8028, "Memory");
  99. __writeMemory32(0x00000000, 0x401F802C, "Memory");
  100. __writeMemory32(0x00000000, 0x401F8030, "Memory");
  101. __writeMemory32(0x00000000, 0x401F8034, "Memory");
  102. __writeMemory32(0x00000000, 0x401F8038, "Memory");
  103. __writeMemory32(0x00000000, 0x401F803C, "Memory");
  104. __writeMemory32(0x00000000, 0x401F8040, "Memory");
  105. __writeMemory32(0x00000000, 0x401F8044, "Memory");
  106. __writeMemory32(0x00000000, 0x401F8048, "Memory");
  107. __writeMemory32(0x00000000, 0x401F804C, "Memory");
  108. __writeMemory32(0x00000000, 0x401F8050, "Memory");
  109. __writeMemory32(0x00000000, 0x401F8054, "Memory");
  110. __writeMemory32(0x00000000, 0x401F8058, "Memory");
  111. __writeMemory32(0x00000000, 0x401F805C, "Memory");
  112. __writeMemory32(0x00000000, 0x401F8060, "Memory");
  113. __writeMemory32(0x00000000, 0x401F8064, "Memory");
  114. __writeMemory32(0x00000000, 0x401F8068, "Memory");
  115. __writeMemory32(0x00000000, 0x401F806C, "Memory");
  116. __writeMemory32(0x00000000, 0x401F8070, "Memory");
  117. __writeMemory32(0x00000000, 0x401F8074, "Memory");
  118. __writeMemory32(0x00000000, 0x401F8078, "Memory");
  119. __writeMemory32(0x00000000, 0x401F807C, "Memory");
  120. __writeMemory32(0x00000000, 0x401F8080, "Memory");
  121. __writeMemory32(0x00000000, 0x401F8084, "Memory");
  122. __writeMemory32(0x00000000, 0x401F8088, "Memory");
  123. __writeMemory32(0x00000000, 0x401F808C, "Memory");
  124. __writeMemory32(0x00000000, 0x401F8090, "Memory");
  125. __writeMemory32(0x00000000, 0x401F8094, "Memory");
  126. __writeMemory32(0x00000000, 0x401F8098, "Memory");
  127. __writeMemory32(0x00000000, 0x401F809C, "Memory");
  128. __writeMemory32(0x00000000, 0x401F80A0, "Memory");
  129. __writeMemory32(0x00000000, 0x401F80A4, "Memory");
  130. __writeMemory32(0x00000000, 0x401F80A8, "Memory");
  131. __writeMemory32(0x00000000, 0x401F80AC, "Memory");
  132. __writeMemory32(0x00000010, 0x401F80B0, "Memory"); // EMC_39, DQS PIN, enable SION
  133. // PAD ctrl
  134. // drive strength = 0x7 to increase drive strength
  135. // otherwise the data7 bit may fail.
  136. __writeMemory32(0x000110F9, 0x401F8204, "Memory");
  137. __writeMemory32(0x000110F9, 0x401F8208, "Memory");
  138. __writeMemory32(0x000110F9, 0x401F820C, "Memory");
  139. __writeMemory32(0x000110F9, 0x401F8210, "Memory");
  140. __writeMemory32(0x000110F9, 0x401F8214, "Memory");
  141. __writeMemory32(0x000110F9, 0x401F8218, "Memory");
  142. __writeMemory32(0x000110F9, 0x401F821C, "Memory");
  143. __writeMemory32(0x000110F9, 0x401F8220, "Memory");
  144. __writeMemory32(0x000110F9, 0x401F8224, "Memory");
  145. __writeMemory32(0x000110F9, 0x401F8228, "Memory");
  146. __writeMemory32(0x000110F9, 0x401F822C, "Memory");
  147. __writeMemory32(0x000110F9, 0x401F8230, "Memory");
  148. __writeMemory32(0x000110F9, 0x401F8234, "Memory");
  149. __writeMemory32(0x000110F9, 0x401F8238, "Memory");
  150. __writeMemory32(0x000110F9, 0x401F823C, "Memory");
  151. __writeMemory32(0x000110F9, 0x401F8240, "Memory");
  152. __writeMemory32(0x000110F9, 0x401F8244, "Memory");
  153. __writeMemory32(0x000110F9, 0x401F8248, "Memory");
  154. __writeMemory32(0x000110F9, 0x401F824C, "Memory");
  155. __writeMemory32(0x000110F9, 0x401F8250, "Memory");
  156. __writeMemory32(0x000110F9, 0x401F8254, "Memory");
  157. __writeMemory32(0x000110F9, 0x401F8258, "Memory");
  158. __writeMemory32(0x000110F9, 0x401F825C, "Memory");
  159. __writeMemory32(0x000110F9, 0x401F8260, "Memory");
  160. __writeMemory32(0x000110F9, 0x401F8264, "Memory");
  161. __writeMemory32(0x000110F9, 0x401F8268, "Memory");
  162. __writeMemory32(0x000110F9, 0x401F826C, "Memory");
  163. __writeMemory32(0x000110F9, 0x401F8270, "Memory");
  164. __writeMemory32(0x000110F9, 0x401F8274, "Memory");
  165. __writeMemory32(0x000110F9, 0x401F8278, "Memory");
  166. __writeMemory32(0x000110F9, 0x401F827C, "Memory");
  167. __writeMemory32(0x000110F9, 0x401F8280, "Memory");
  168. __writeMemory32(0x000110F9, 0x401F8284, "Memory");
  169. __writeMemory32(0x000110F9, 0x401F8288, "Memory");
  170. __writeMemory32(0x000110F9, 0x401F828C, "Memory");
  171. __writeMemory32(0x000110F9, 0x401F8290, "Memory");
  172. __writeMemory32(0x000110F9, 0x401F8294, "Memory");
  173. __writeMemory32(0x000110F9, 0x401F8298, "Memory");
  174. __writeMemory32(0x000110F9, 0x401F829C, "Memory");
  175. __writeMemory32(0x000110F9, 0x401F82A0, "Memory");
  176. // Config SDR Controller Registers/
  177. __writeMemory32(0x10000004, 0x402F0000, "Memory"); // MCR
  178. __writeMemory32(0x00000081, 0x402F0008, "Memory"); // BMCR0
  179. __writeMemory32(0x00000081, 0x402F000C, "Memory"); // BMCR1
  180. __writeMemory32(0x8000001B, 0x402F0010, "Memory"); // BR0, 32MB
  181. __writeMemory32(0x00000F31, 0x402F0040, "Memory"); // SDRAMCR0
  182. __writeMemory32(0x00662A22, 0x402F0044, "Memory"); // SDRAMCR1
  183. __writeMemory32(0x000A0A0A, 0x402F0048, "Memory"); // SDRAMCR2
  184. __writeMemory32(0x08080A00, 0x402F004C, "Memory"); // SDRAMCR3
  185. __writeMemory32(0x80000000, 0x402F0090, "Memory"); // IPCR0
  186. __writeMemory32(0x00000002, 0x402F0094, "Memory"); // IPCR1
  187. __writeMemory32(0x00000000, 0x402F0098, "Memory"); // IPCR2
  188. __writeMemory32(0xA55A000F, 0x402F009C, "Memory"); // IPCMD, SD_CC_IPREA
  189. SDRAM_WaitIpCmdDone();
  190. __writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
  191. SDRAM_WaitIpCmdDone();
  192. __writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
  193. SDRAM_WaitIpCmdDone();
  194. __writeMemory32(0x00000033, 0x402F00A0, "Memory"); // IPTXDAT
  195. __writeMemory32(0xA55A000A, 0x402F009C, "Memory"); // SD_CC_IMS
  196. SDRAM_WaitIpCmdDone();
  197. __writeMemory32(0x08080A01, 0x402F004C, "Memory"); // enable sdram self refresh after initialization done.
  198. __message "SDRAM init done\n";
  199. }
  200. restoreFlexRAM()
  201. {
  202. __var base;
  203. __var value;
  204. base = 0x400AC000;
  205. value = __readMemory32(base + 0x44, "Memory");
  206. value &= ~(0xFFFFFFFF);
  207. value |= 0x55AFFA55;
  208. __writeMemory32(value, base + 0x44, "Memory");
  209. value = __readMemory32(base + 0x40, "Memory");
  210. value |= (1 << 2);
  211. __writeMemory32(value, base + 0x40, "Memory");
  212. __message "FlexRAM configuration is restored";
  213. }
  214. execUserPreload()
  215. {
  216. restoreFlexRAM();
  217. _load_dcdc_trim();
  218. _clock_init();
  219. _sdr_Init();
  220. __message "execUserPreload() done.\n";
  221. }
  222. execUserReset()
  223. {
  224. restoreFlexRAM();
  225. _load_dcdc_trim();
  226. _clock_init();
  227. _sdr_Init();
  228. __message "execUserReset() done.\n";
  229. }