cmsis_iar.h 5.7 KB

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  1. /**************************************************
  2. *
  3. * This file shall be included in appropriate CMSIS header
  4. * files, to provide required functions and intrinsics when
  5. * building with the IAR C/C++ Compiler for ARM (iccarm).
  6. *
  7. * Copyright 2011 IAR Systems. All rights reserved.
  8. *
  9. * $Revision: 78346 $
  10. *
  11. **************************************************/
  12. #ifndef __CMSIS_IAR_H__
  13. #define __CMSIS_IAR_H__
  14. #ifndef __ICCARM__
  15. #error This file should only be compiled by ICCARM
  16. #endif
  17. #pragma system_include
  18. #include <intrinsics.h>
  19. #if (__CORE__ == __ARM6M__)
  20. /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
  21. #define __CLZ __cmsis_iar_clz
  22. #define __SSAT __cmsis_iar_ssat
  23. #endif
  24. #pragma diag_suppress=Pe940
  25. #pragma diag_suppress=Pe177
  26. #define __enable_irq __enable_interrupt
  27. #define __disable_irq __disable_interrupt
  28. #define __NOP __no_operation
  29. #if (__VER__ >= 6040000) /* If iccarm version is 6.40.x or newer ---------- */
  30. #define __BKPT(value) asm volatile ("BKPT\t%0" : : "i"(value))
  31. #endif
  32. #if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
  33. #if (__VER__ < 6010002) /* If iccarm version is older than 6.10.2 ---------- */
  34. static uint32_t __get_APSR(void)
  35. {
  36. __ASM("mrs r0, apsr");
  37. }
  38. static uint32_t __get_xPSR(void)
  39. {
  40. __ASM("mrs r0, psr"); /* assembler does not know "xpsr" */
  41. }
  42. #endif /* __VER__ < 6010002 */
  43. static uint32_t __get_IPSR(void)
  44. {
  45. __ASM("mrs r0, ipsr");
  46. }
  47. static uint32_t __get_PSR(void)
  48. {
  49. __ASM("mrs r0, psr");
  50. }
  51. static uint32_t __get_PSP(void)
  52. {
  53. __ASM("mrs r0, psp");
  54. }
  55. static void __set_PSP(uint32_t topOfProcStack)
  56. {
  57. __ASM("msr psp, r0");
  58. }
  59. static uint32_t __get_MSP(void)
  60. {
  61. __ASM("mrs r0, msp");
  62. }
  63. static void __set_MSP(uint32_t topOfMainStack)
  64. {
  65. __ASM("msr msp, r0");
  66. }
  67. static __INLINE void __WFI(void)
  68. {
  69. __ASM ("wfi");
  70. }
  71. static __INLINE void __WFE(void)
  72. {
  73. __ASM ("wfe");
  74. }
  75. static __INLINE void __SEV(void)
  76. {
  77. __ASM ("sev");
  78. }
  79. static uint32_t __REV16(uint32_t value)
  80. {
  81. __ASM("rev16 r0, r0");
  82. }
  83. #else /* __VER__ < 6020000 */
  84. static uint32_t __get_xPSR(void)
  85. {
  86. return __get_PSR(); /* __get_PSR() intrinsic introduced in iccarm 6.20 */
  87. }
  88. #endif /* __VER__ < 6020000 */
  89. #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
  90. #if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
  91. static __INLINE void __enable_fault_irq(void)
  92. {
  93. __ASM ("cpsie f");
  94. }
  95. static __INLINE void __disable_fault_irq(void)
  96. {
  97. __ASM ("cpsid f");
  98. }
  99. static uint32_t __RBIT(uint32_t value)
  100. {
  101. __ASM("rbit r0, r0");
  102. }
  103. static uint8_t __LDREXB(volatile uint8_t *addr)
  104. {
  105. __ASM("ldrexb r0, [r0]");
  106. }
  107. static uint16_t __LDREXH(volatile uint16_t *addr)
  108. {
  109. __ASM("ldrexh r0, [r0]");
  110. }
  111. static uint32_t __LDREXW(volatile uint32_t *addr)
  112. {
  113. __ASM("ldrex r0, [r0]");
  114. }
  115. static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
  116. {
  117. __ASM("strexb r0, r0, [r1]");
  118. }
  119. static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
  120. {
  121. __ASM("strexh r0, r0, [r1]");
  122. }
  123. static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
  124. {
  125. __ASM("strex r0, r0, [r1]");
  126. }
  127. static __INLINE void __CLREX(void)
  128. {
  129. __ASM ("clrex");
  130. }
  131. #else /* __VER__ >= 6020000 --------------------- */
  132. #define __LDREXW __LDREX
  133. #define __STREXW __STREX
  134. #define __enable_fault_irq __enable_fiq
  135. #define __disable_fault_irq __disable_fiq
  136. #endif /* __VER__ < 6020000 */
  137. #endif /* (__CORTEX_M >= 0x03) */
  138. #if (__CORTEX_M == 0x04) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
  139. #if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
  140. static uint32_t __get_FPSCR(void)
  141. {
  142. #if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
  143. __ASM("vmrs r0, fpscr");
  144. #else
  145. return(0);
  146. #endif
  147. }
  148. static void __set_FPSCR(uint32_t fpscr)
  149. {
  150. #if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
  151. __ASM("vmsr fpscr, r0");
  152. #endif
  153. }
  154. #endif /* __VER__ < 6020000 */
  155. #endif /* (__CORTEX_M == 0x04) */
  156. #if (__VER__ >= 7000000) /* If iccarm version is 7.x or newer ---------- */
  157. #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
  158. static __INLINE uint32_t __RRX(uint32_t value)
  159. {
  160. uint32_t result;
  161. __ASM("RRX %0, %1" : "=r"(result) : "r" (value) );
  162. return(result);
  163. }
  164. static __INLINE uint8_t __LDRBT(volatile uint8_t *addr)
  165. {
  166. uint32_t result;
  167. __ASM("LDRBT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  168. return ((uint8_t) result);
  169. }
  170. static __INLINE uint16_t __LDRHT(volatile uint16_t *addr)
  171. {
  172. uint32_t result;
  173. __ASM("LDRHT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  174. return ((uint16_t) result);
  175. }
  176. static __INLINE uint32_t __LDRT(volatile uint32_t *addr)
  177. {
  178. uint32_t result;
  179. __ASM("LDRT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  180. return(result);
  181. }
  182. static __INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
  183. {
  184. __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory" );
  185. }
  186. static __INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
  187. {
  188. __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory" );
  189. }
  190. static __INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
  191. {
  192. __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory" );
  193. }
  194. #endif /* (__CORTEX_M >= 0x03) */
  195. #endif /* __VER__ >= 7000000 */
  196. static __INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
  197. {
  198. return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
  199. }
  200. #pragma diag_default=Pe940
  201. #pragma diag_default=Pe177
  202. #endif /* __CMSIS_IAR_H__ */