drv_adc.c 6.8 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-05 zylx first version
  9. * 2018-12-12 greedyhao Porting for stm32f7xx
  10. * 2019-02-01 yuneizhilin fix the stm32_adc_init function initialization issue
  11. */
  12. #include <board.h>
  13. #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
  14. #include "drv_config.h"
  15. //#define DRV_DEBUG
  16. #define LOG_TAG "drv.adc"
  17. #include <drv_log.h>
  18. static ADC_HandleTypeDef adc_config[] =
  19. {
  20. #ifdef BSP_USING_ADC1
  21. ADC1_CONFIG,
  22. #endif
  23. #ifdef BSP_USING_ADC2
  24. ADC2_CONFIG,
  25. #endif
  26. #ifdef BSP_USING_ADC3
  27. ADC3_CONFIG,
  28. #endif
  29. };
  30. struct stm32_adc
  31. {
  32. ADC_HandleTypeDef ADC_Handler;
  33. struct rt_adc_device stm32_adc_device;
  34. };
  35. static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
  36. static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
  37. {
  38. ADC_HandleTypeDef *stm32_adc_handler;
  39. RT_ASSERT(device != RT_NULL);
  40. stm32_adc_handler = device->parent.user_data;
  41. if (enabled)
  42. {
  43. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
  44. ADC_Enable(stm32_adc_handler);
  45. #else
  46. __HAL_ADC_ENABLE(stm32_adc_handler);
  47. #endif
  48. }
  49. else
  50. {
  51. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
  52. ADC_Disable(stm32_adc_handler);
  53. #else
  54. __HAL_ADC_DISABLE(stm32_adc_handler);
  55. #endif
  56. }
  57. return RT_EOK;
  58. }
  59. static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
  60. {
  61. rt_uint32_t stm32_channel = 0;
  62. switch (channel)
  63. {
  64. case 0:
  65. stm32_channel = ADC_CHANNEL_0;
  66. break;
  67. case 1:
  68. stm32_channel = ADC_CHANNEL_1;
  69. break;
  70. case 2:
  71. stm32_channel = ADC_CHANNEL_2;
  72. break;
  73. case 3:
  74. stm32_channel = ADC_CHANNEL_3;
  75. break;
  76. case 4:
  77. stm32_channel = ADC_CHANNEL_4;
  78. break;
  79. case 5:
  80. stm32_channel = ADC_CHANNEL_5;
  81. break;
  82. case 6:
  83. stm32_channel = ADC_CHANNEL_6;
  84. break;
  85. case 7:
  86. stm32_channel = ADC_CHANNEL_7;
  87. break;
  88. case 8:
  89. stm32_channel = ADC_CHANNEL_8;
  90. break;
  91. case 9:
  92. stm32_channel = ADC_CHANNEL_9;
  93. break;
  94. case 10:
  95. stm32_channel = ADC_CHANNEL_10;
  96. break;
  97. case 11:
  98. stm32_channel = ADC_CHANNEL_11;
  99. break;
  100. case 12:
  101. stm32_channel = ADC_CHANNEL_12;
  102. break;
  103. case 13:
  104. stm32_channel = ADC_CHANNEL_13;
  105. break;
  106. case 14:
  107. stm32_channel = ADC_CHANNEL_14;
  108. break;
  109. case 15:
  110. stm32_channel = ADC_CHANNEL_15;
  111. break;
  112. case 16:
  113. stm32_channel = ADC_CHANNEL_16;
  114. break;
  115. case 17:
  116. stm32_channel = ADC_CHANNEL_17;
  117. break;
  118. #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
  119. case 18:
  120. stm32_channel = ADC_CHANNEL_18;
  121. break;
  122. #endif
  123. }
  124. return stm32_channel;
  125. }
  126. static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
  127. {
  128. ADC_ChannelConfTypeDef ADC_ChanConf;
  129. ADC_HandleTypeDef *stm32_adc_handler;
  130. RT_ASSERT(device != RT_NULL);
  131. RT_ASSERT(value != RT_NULL);
  132. stm32_adc_handler = device->parent.user_data;
  133. rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
  134. #if defined(SOC_SERIES_STM32F1)
  135. if (channel <= 17)
  136. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
  137. || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
  138. if (channel <= 18)
  139. #endif
  140. {
  141. /* set stm32 ADC channel */
  142. ADC_ChanConf.Channel = stm32_adc_get_channel(channel);
  143. }
  144. else
  145. {
  146. #if defined(SOC_SERIES_STM32F1)
  147. LOG_E("ADC channel must be between 0 and 17.");
  148. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
  149. || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
  150. LOG_E("ADC channel must be between 0 and 18.");
  151. #endif
  152. return -RT_ERROR;
  153. }
  154. ADC_ChanConf.Rank = 1;
  155. #if defined(SOC_SERIES_STM32F0)
  156. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
  157. #elif defined(SOC_SERIES_STM32F1)
  158. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
  159. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  160. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
  161. #elif defined(SOC_SERIES_STM32L4)
  162. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
  163. #endif
  164. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
  165. ADC_ChanConf.Offset = 0;
  166. #endif
  167. #ifdef SOC_SERIES_STM32L4
  168. ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
  169. ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
  170. #endif
  171. HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
  172. /* start ADC */
  173. HAL_ADC_Start(stm32_adc_handler);
  174. /* Wait for the ADC to convert */
  175. HAL_ADC_PollForConversion(stm32_adc_handler, 100);
  176. /* get ADC value */
  177. *value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
  178. return RT_EOK;
  179. }
  180. static const struct rt_adc_ops stm_adc_ops =
  181. {
  182. .enabled = stm32_adc_enabled,
  183. .convert = stm32_get_adc_value,
  184. };
  185. static int stm32_adc_init(void)
  186. {
  187. int result = RT_EOK;
  188. /* save adc name */
  189. char name_buf[5] = {'a', 'd', 'c', '0', 0};
  190. int i = 0;
  191. for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
  192. {
  193. /* ADC init */
  194. name_buf[3] = '0';
  195. stm32_adc_obj[i].ADC_Handler = adc_config[i];
  196. #if defined(ADC1)
  197. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC1)
  198. {
  199. name_buf[3] = '1';
  200. }
  201. #endif
  202. #if defined(ADC2)
  203. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC2)
  204. {
  205. name_buf[3] = '2';
  206. }
  207. #endif
  208. #if defined(ADC3)
  209. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC3)
  210. {
  211. name_buf[3] = '3';
  212. }
  213. #endif
  214. if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
  215. {
  216. LOG_E("%s init failed", name_buf);
  217. result = -RT_ERROR;
  218. }
  219. else
  220. {
  221. /* register ADC device */
  222. if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
  223. {
  224. LOG_D("%s init success", name_buf);
  225. }
  226. else
  227. {
  228. LOG_E("%s register failed", name_buf);
  229. result = -RT_ERROR;
  230. }
  231. }
  232. }
  233. return result;
  234. }
  235. INIT_BOARD_EXPORT(stm32_adc_init);
  236. #endif /* BSP_USING_ADC */