spi_flash_w25qxx.c 12 KB

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  1. /*
  2. * File : spi_flash_w25qxx.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2011-12-16 aozima the first version
  13. * 2012-05-06 aozima can page write.
  14. * 2012-08-23 aozima add flash lock.
  15. * 2012-08-24 aozima fixed write status register BUG.
  16. * 2015-05-13 bernard add GD25Q flash ID.
  17. */
  18. #include <stdint.h>
  19. #include "spi_flash_w25qxx.h"
  20. #define FLASH_DEBUG
  21. #ifdef FLASH_DEBUG
  22. #define FLASH_TRACE rt_kprintf
  23. #else
  24. #define FLASH_TRACE(...)
  25. #endif /* #ifdef FLASH_DEBUG */
  26. #define PAGE_SIZE 4096
  27. /* JEDEC Manufacturer��s ID */
  28. #define MF_ID (0xEF)
  29. #define GD_ID (0xC8)
  30. /* JEDEC Device ID: Memory type and Capacity */
  31. #define MTC_W25Q80_BV (0x4014) /* W25Q80BV */
  32. #define MTC_W25Q16_BV_CL_CV (0x4015) /* W25Q16BV W25Q16CL W25Q16CV */
  33. #define MTC_W25Q16_DW (0x6015) /* W25Q16DW */
  34. #define MTC_W25Q32_BV (0x4016) /* W25Q32BV */
  35. #define MTC_W25Q32_DW (0x6016) /* W25Q32DW */
  36. #define MTC_W25Q64_BV_CV (0x4017) /* W25Q64BV W25Q64CV */
  37. #define MTC_W25Q64_DW (0x4017) /* W25Q64DW */
  38. #define MTC_W25Q128_BV (0x4018) /* W25Q128BV */
  39. #define MTC_W25Q256_FV (TBD) /* W25Q256FV */
  40. /* command list */
  41. #define CMD_WRSR (0x01) /* Write Status Register */
  42. #define CMD_PP (0x02) /* Page Program */
  43. #define CMD_READ (0x03) /* Read Data */
  44. #define CMD_WRDI (0x04) /* Write Disable */
  45. #define CMD_RDSR1 (0x05) /* Read Status Register-1 */
  46. #define CMD_WREN (0x06) /* Write Enable */
  47. #define CMD_FAST_READ (0x0B) /* Fast Read */
  48. #define CMD_ERASE_4K (0x20) /* Sector Erase:4K */
  49. #define CMD_RDSR2 (0x35) /* Read Status Register-2 */
  50. #define CMD_ERASE_32K (0x52) /* 32KB Block Erase */
  51. #define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */
  52. #define CMD_ERASE_full (0xC7) /* Chip Erase */
  53. #define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */
  54. #define DUMMY (0xFF)
  55. static struct spi_flash_device spi_flash_device;
  56. static void flash_lock(struct spi_flash_device * flash_device)
  57. {
  58. rt_mutex_take(&flash_device->lock, RT_WAITING_FOREVER);
  59. }
  60. static void flash_unlock(struct spi_flash_device * flash_device)
  61. {
  62. rt_mutex_release(&flash_device->lock);
  63. }
  64. static uint8_t w25qxx_read_status(void)
  65. {
  66. return rt_spi_sendrecv8(spi_flash_device.rt_spi_device, CMD_RDSR1);
  67. }
  68. static void w25qxx_wait_busy(void)
  69. {
  70. while( w25qxx_read_status() & (0x01));
  71. }
  72. /** \brief read [size] byte from [offset] to [buffer]
  73. *
  74. * \param offset uint32_t unit : byte
  75. * \param buffer uint8_t*
  76. * \param size uint32_t unit : byte
  77. * \return uint32_t byte for read
  78. *
  79. */
  80. static uint32_t w25qxx_read(uint32_t offset, uint8_t * buffer, uint32_t size)
  81. {
  82. uint8_t send_buffer[4];
  83. send_buffer[0] = CMD_WRDI;
  84. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  85. send_buffer[0] = CMD_READ;
  86. send_buffer[1] = (uint8_t)(offset>>16);
  87. send_buffer[2] = (uint8_t)(offset>>8);
  88. send_buffer[3] = (uint8_t)(offset);
  89. rt_spi_send_then_recv(spi_flash_device.rt_spi_device,
  90. send_buffer, 4,
  91. buffer, size);
  92. return size;
  93. }
  94. /** \brief write N page on [page]
  95. *
  96. * \param page_addr uint32_t unit : byte (4096 * N,1 page = 4096byte)
  97. * \param buffer const uint8_t*
  98. * \return uint32_t
  99. *
  100. */
  101. uint32_t w25qxx_page_write(uint32_t page_addr, const uint8_t* buffer)
  102. {
  103. uint32_t index;
  104. uint8_t send_buffer[4];
  105. RT_ASSERT((page_addr&0xFF) == 0); /* page addr must align to 256byte. */
  106. send_buffer[0] = CMD_WREN;
  107. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  108. send_buffer[0] = CMD_ERASE_4K;
  109. send_buffer[1] = (page_addr >> 16);
  110. send_buffer[2] = (page_addr >> 8);
  111. send_buffer[3] = (page_addr);
  112. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 4);
  113. w25qxx_wait_busy(); // wait erase done.
  114. for(index=0; index < (PAGE_SIZE / 256); index++)
  115. {
  116. send_buffer[0] = CMD_WREN;
  117. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  118. send_buffer[0] = CMD_PP;
  119. send_buffer[1] = (uint8_t)(page_addr >> 16);
  120. send_buffer[2] = (uint8_t)(page_addr >> 8);
  121. send_buffer[3] = (uint8_t)(page_addr);
  122. rt_spi_send_then_send(spi_flash_device.rt_spi_device,
  123. send_buffer,
  124. 4,
  125. buffer,
  126. 256);
  127. buffer += 256;
  128. page_addr += 256;
  129. w25qxx_wait_busy();
  130. }
  131. send_buffer[0] = CMD_WRDI;
  132. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  133. return PAGE_SIZE;
  134. }
  135. /* RT-Thread device interface */
  136. static rt_err_t w25qxx_flash_init(rt_device_t dev)
  137. {
  138. return RT_EOK;
  139. }
  140. static rt_err_t w25qxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
  141. {
  142. uint8_t send_buffer[3];
  143. flash_lock((struct spi_flash_device *)dev);
  144. send_buffer[0] = CMD_WREN;
  145. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  146. send_buffer[0] = CMD_WRSR;
  147. send_buffer[1] = 0;
  148. send_buffer[2] = 0;
  149. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 3);
  150. w25qxx_wait_busy();
  151. flash_unlock((struct spi_flash_device *)dev);
  152. return RT_EOK;
  153. }
  154. static rt_err_t w25qxx_flash_close(rt_device_t dev)
  155. {
  156. return RT_EOK;
  157. }
  158. static rt_err_t w25qxx_flash_control(rt_device_t dev, rt_uint8_t cmd, void *args)
  159. {
  160. RT_ASSERT(dev != RT_NULL);
  161. if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
  162. {
  163. struct rt_device_blk_geometry *geometry;
  164. geometry = (struct rt_device_blk_geometry *)args;
  165. if (geometry == RT_NULL) return -RT_ERROR;
  166. geometry->bytes_per_sector = spi_flash_device.geometry.bytes_per_sector;
  167. geometry->sector_count = spi_flash_device.geometry.sector_count;
  168. geometry->block_size = spi_flash_device.geometry.block_size;
  169. }
  170. return RT_EOK;
  171. }
  172. static rt_size_t w25qxx_flash_read(rt_device_t dev,
  173. rt_off_t pos,
  174. void* buffer,
  175. rt_size_t size)
  176. {
  177. flash_lock((struct spi_flash_device *)dev);
  178. w25qxx_read(pos*spi_flash_device.geometry.bytes_per_sector,
  179. buffer,
  180. size*spi_flash_device.geometry.bytes_per_sector);
  181. flash_unlock((struct spi_flash_device *)dev);
  182. return size;
  183. }
  184. static rt_size_t w25qxx_flash_write(rt_device_t dev,
  185. rt_off_t pos,
  186. const void* buffer,
  187. rt_size_t size)
  188. {
  189. rt_size_t i = 0;
  190. rt_size_t block = size;
  191. const uint8_t * ptr = buffer;
  192. flash_lock((struct spi_flash_device *)dev);
  193. while(block--)
  194. {
  195. w25qxx_page_write((pos + i)*spi_flash_device.geometry.bytes_per_sector,
  196. ptr);
  197. ptr += PAGE_SIZE;
  198. i++;
  199. }
  200. flash_unlock((struct spi_flash_device *)dev);
  201. return size;
  202. }
  203. rt_err_t w25qxx_init(const char * flash_device_name, const char * spi_device_name)
  204. {
  205. struct rt_spi_device * rt_spi_device;
  206. /* initialize mutex */
  207. if (rt_mutex_init(&spi_flash_device.lock, spi_device_name, RT_IPC_FLAG_FIFO) != RT_EOK)
  208. {
  209. rt_kprintf("init sd lock mutex failed\n");
  210. return -RT_ENOSYS;
  211. }
  212. rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
  213. if(rt_spi_device == RT_NULL)
  214. {
  215. FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
  216. return -RT_ENOSYS;
  217. }
  218. spi_flash_device.rt_spi_device = rt_spi_device;
  219. /* config spi */
  220. {
  221. struct rt_spi_configuration cfg;
  222. cfg.data_width = 8;
  223. cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
  224. cfg.max_hz = 50 * 1000 * 1000; /* 50M */
  225. rt_spi_configure(spi_flash_device.rt_spi_device, &cfg);
  226. }
  227. /* init flash */
  228. {
  229. rt_uint8_t cmd;
  230. rt_uint8_t id_recv[3];
  231. uint16_t memory_type_capacity;
  232. flash_lock(&spi_flash_device);
  233. cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
  234. rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
  235. cmd = CMD_WRDI;
  236. rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
  237. /* read flash id */
  238. cmd = CMD_JEDEC_ID;
  239. rt_spi_send_then_recv(spi_flash_device.rt_spi_device, &cmd, 1, id_recv, 3);
  240. flash_unlock(&spi_flash_device);
  241. if(id_recv[0] != MF_ID && id_recv[0] != GD_ID)
  242. {
  243. FLASH_TRACE("Manufacturers ID error!\r\n");
  244. FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
  245. return -RT_ENOSYS;
  246. }
  247. spi_flash_device.geometry.bytes_per_sector = 4096;
  248. spi_flash_device.geometry.block_size = 4096; /* block erase: 4k */
  249. /* get memory type and capacity */
  250. memory_type_capacity = id_recv[1];
  251. memory_type_capacity = (memory_type_capacity << 8) | id_recv[2];
  252. if(memory_type_capacity == MTC_W25Q128_BV)
  253. {
  254. FLASH_TRACE("W25Q128BV detection\r\n");
  255. spi_flash_device.geometry.sector_count = 4096;
  256. }
  257. else if(memory_type_capacity == MTC_W25Q64_BV_CV)
  258. {
  259. FLASH_TRACE("W25Q64BV or W25Q64CV detection\r\n");
  260. spi_flash_device.geometry.sector_count = 2048;
  261. }
  262. else if(memory_type_capacity == MTC_W25Q64_DW)
  263. {
  264. FLASH_TRACE("W25Q64DW detection\r\n");
  265. spi_flash_device.geometry.sector_count = 2048;
  266. }
  267. else if(memory_type_capacity == MTC_W25Q32_BV)
  268. {
  269. FLASH_TRACE("W25Q32BV detection\r\n");
  270. spi_flash_device.geometry.sector_count = 1024;
  271. }
  272. else if(memory_type_capacity == MTC_W25Q32_DW)
  273. {
  274. FLASH_TRACE("W25Q32DW detection\r\n");
  275. spi_flash_device.geometry.sector_count = 1024;
  276. }
  277. else if(memory_type_capacity == MTC_W25Q16_BV_CL_CV)
  278. {
  279. FLASH_TRACE("W25Q16BV or W25Q16CL or W25Q16CV detection\r\n");
  280. spi_flash_device.geometry.sector_count = 512;
  281. }
  282. else if(memory_type_capacity == MTC_W25Q16_DW)
  283. {
  284. FLASH_TRACE("W25Q16DW detection\r\n");
  285. spi_flash_device.geometry.sector_count = 512;
  286. }
  287. else if(memory_type_capacity == MTC_W25Q80_BV)
  288. {
  289. FLASH_TRACE("W25Q80BV detection\r\n");
  290. spi_flash_device.geometry.sector_count = 256;
  291. }
  292. else
  293. {
  294. FLASH_TRACE("Memory Capacity error!\r\n");
  295. return -RT_ENOSYS;
  296. }
  297. }
  298. /* register device */
  299. spi_flash_device.flash_device.type = RT_Device_Class_Block;
  300. spi_flash_device.flash_device.init = w25qxx_flash_init;
  301. spi_flash_device.flash_device.open = w25qxx_flash_open;
  302. spi_flash_device.flash_device.close = w25qxx_flash_close;
  303. spi_flash_device.flash_device.read = w25qxx_flash_read;
  304. spi_flash_device.flash_device.write = w25qxx_flash_write;
  305. spi_flash_device.flash_device.control = w25qxx_flash_control;
  306. /* no private */
  307. spi_flash_device.flash_device.user_data = RT_NULL;
  308. rt_device_register(&spi_flash_device.flash_device, flash_device_name,
  309. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
  310. return RT_EOK;
  311. }