stm32f10x_rcc.c 48 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f10x_rcc.c
  4. * @author MCD Application Team
  5. * @version V3.1.2
  6. * @date 09/28/2009
  7. * @brief This file provides all the RCC firmware functions.
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
  19. */
  20. /* Includes ------------------------------------------------------------------*/
  21. #include "stm32f10x_rcc.h"
  22. /** @addtogroup STM32F10x_StdPeriph_Driver
  23. * @{
  24. */
  25. /** @defgroup RCC
  26. * @brief RCC driver modules
  27. * @{
  28. */
  29. /** @defgroup RCC_Private_TypesDefinitions
  30. * @{
  31. */
  32. /**
  33. * @}
  34. */
  35. /** @defgroup RCC_Private_Defines
  36. * @{
  37. */
  38. /* ------------ RCC registers bit address in the alias region ----------- */
  39. #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
  40. /* --- CR Register ---*/
  41. /* Alias word address of HSION bit */
  42. #define CR_OFFSET (RCC_OFFSET + 0x00)
  43. #define HSION_BitNumber 0x00
  44. #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
  45. /* Alias word address of PLLON bit */
  46. #define PLLON_BitNumber 0x18
  47. #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
  48. #ifdef STM32F10X_CL
  49. /* Alias word address of PLL2ON bit */
  50. #define PLL2ON_BitNumber 0x1A
  51. #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
  52. /* Alias word address of PLL3ON bit */
  53. #define PLL3ON_BitNumber 0x1C
  54. #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
  55. #endif /* STM32F10X_CL */
  56. /* Alias word address of CSSON bit */
  57. #define CSSON_BitNumber 0x13
  58. #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
  59. /* --- CFGR Register ---*/
  60. /* Alias word address of USBPRE bit */
  61. #define CFGR_OFFSET (RCC_OFFSET + 0x04)
  62. #ifndef STM32F10X_CL
  63. #define USBPRE_BitNumber 0x16
  64. #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
  65. #else
  66. #define OTGFSPRE_BitNumber 0x16
  67. #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
  68. #endif /* STM32F10X_CL */
  69. /* --- BDCR Register ---*/
  70. /* Alias word address of RTCEN bit */
  71. #define BDCR_OFFSET (RCC_OFFSET + 0x20)
  72. #define RTCEN_BitNumber 0x0F
  73. #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
  74. /* Alias word address of BDRST bit */
  75. #define BDRST_BitNumber 0x10
  76. #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
  77. /* --- CSR Register ---*/
  78. /* Alias word address of LSION bit */
  79. #define CSR_OFFSET (RCC_OFFSET + 0x24)
  80. #define LSION_BitNumber 0x00
  81. #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
  82. #ifdef STM32F10X_CL
  83. /* --- CFGR2 Register ---*/
  84. /* Alias word address of I2S2SRC bit */
  85. #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
  86. #define I2S2SRC_BitNumber 0x11
  87. #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
  88. /* Alias word address of I2S3SRC bit */
  89. #define I2S3SRC_BitNumber 0x12
  90. #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
  91. #endif /* STM32F10X_CL */
  92. /* ---------------------- RCC registers bit mask ------------------------ */
  93. /* CR register bit mask */
  94. #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
  95. #define CR_HSEBYP_Set ((uint32_t)0x00040000)
  96. #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
  97. #define CR_HSEON_Set ((uint32_t)0x00010000)
  98. #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
  99. /* CFGR register bit mask */
  100. #ifndef STM32F10X_CL
  101. #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
  102. #else
  103. #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
  104. #endif /* STM32F10X_CL */
  105. #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
  106. #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
  107. #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
  108. #define CFGR_SWS_Mask ((uint32_t)0x0000000C)
  109. #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
  110. #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
  111. #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
  112. #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
  113. #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
  114. #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
  115. #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
  116. #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
  117. #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
  118. /* CSR register bit mask */
  119. #define CSR_RMVF_Set ((uint32_t)0x01000000)
  120. #ifdef STM32F10X_CL
  121. /* CFGR2 register bit mask */
  122. #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
  123. #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
  124. #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
  125. #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
  126. #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
  127. #endif /* STM32F10X_CL */
  128. /* RCC Flag Mask */
  129. #define FLAG_Mask ((uint8_t)0x1F)
  130. #ifndef HSI_Value
  131. /* Typical Value of the HSI in Hz */
  132. #define HSI_Value ((uint32_t)8000000)
  133. #endif /* HSI_Value */
  134. /* CIR register byte 2 (Bits[15:8]) base address */
  135. #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
  136. /* CIR register byte 3 (Bits[23:16]) base address */
  137. #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
  138. /* CFGR register byte 4 (Bits[31:24]) base address */
  139. #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
  140. /* BDCR register base address */
  141. #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
  142. #ifndef HSEStartUp_TimeOut
  143. /* Time out for HSE start up */
  144. #define HSEStartUp_TimeOut ((uint16_t)0x0500)
  145. #endif /* HSEStartUp_TimeOut */
  146. /**
  147. * @}
  148. */
  149. /** @defgroup RCC_Private_Macros
  150. * @{
  151. */
  152. /**
  153. * @}
  154. */
  155. /** @defgroup RCC_Private_Variables
  156. * @{
  157. */
  158. static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
  159. static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
  160. /**
  161. * @}
  162. */
  163. /** @defgroup RCC_Private_FunctionPrototypes
  164. * @{
  165. */
  166. /**
  167. * @}
  168. */
  169. /** @defgroup RCC_Private_Functions
  170. * @{
  171. */
  172. /**
  173. * @brief Resets the RCC clock configuration to the default reset state.
  174. * @param None
  175. * @retval None
  176. */
  177. void RCC_DeInit(void)
  178. {
  179. /* Set HSION bit */
  180. RCC->CR |= (uint32_t)0x00000001;
  181. /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
  182. #ifndef STM32F10X_CL
  183. RCC->CFGR &= (uint32_t)0xF8FF0000;
  184. #else
  185. RCC->CFGR &= (uint32_t)0xF0FF0000;
  186. #endif /* STM32F10X_CL */
  187. /* Reset HSEON, CSSON and PLLON bits */
  188. RCC->CR &= (uint32_t)0xFEF6FFFF;
  189. /* Reset HSEBYP bit */
  190. RCC->CR &= (uint32_t)0xFFFBFFFF;
  191. /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  192. RCC->CFGR &= (uint32_t)0xFF80FFFF;
  193. #ifndef STM32F10X_CL
  194. /* Disable all interrupts and clear pending bits */
  195. RCC->CIR = 0x009F0000;
  196. #else
  197. /* Reset PLL2ON and PLL3ON bits */
  198. RCC->CR &= (uint32_t)0xEBFFFFFF;
  199. /* Disable all interrupts and clear pending bits */
  200. RCC->CIR = 0x00FF0000;
  201. /* Reset CFGR2 register */
  202. RCC->CFGR2 = 0x00000000;
  203. #endif /* STM32F10X_CL */
  204. }
  205. /**
  206. * @brief Configures the External High Speed oscillator (HSE).
  207. * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
  208. * @param RCC_HSE: specifies the new state of the HSE.
  209. * This parameter can be one of the following values:
  210. * @arg RCC_HSE_OFF: HSE oscillator OFF
  211. * @arg RCC_HSE_ON: HSE oscillator ON
  212. * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
  213. * @retval None
  214. */
  215. void RCC_HSEConfig(uint32_t RCC_HSE)
  216. {
  217. /* Check the parameters */
  218. assert_param(IS_RCC_HSE(RCC_HSE));
  219. /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
  220. /* Reset HSEON bit */
  221. RCC->CR &= CR_HSEON_Reset;
  222. /* Reset HSEBYP bit */
  223. RCC->CR &= CR_HSEBYP_Reset;
  224. /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
  225. switch(RCC_HSE)
  226. {
  227. case RCC_HSE_ON:
  228. /* Set HSEON bit */
  229. RCC->CR |= CR_HSEON_Set;
  230. break;
  231. case RCC_HSE_Bypass:
  232. /* Set HSEBYP and HSEON bits */
  233. RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
  234. break;
  235. default:
  236. break;
  237. }
  238. }
  239. /**
  240. * @brief Waits for HSE start-up.
  241. * @param None
  242. * @retval An ErrorStatus enumuration value:
  243. * - SUCCESS: HSE oscillator is stable and ready to use
  244. * - ERROR: HSE oscillator not yet ready
  245. */
  246. ErrorStatus RCC_WaitForHSEStartUp(void)
  247. {
  248. __IO uint32_t StartUpCounter = 0;
  249. ErrorStatus status = ERROR;
  250. FlagStatus HSEStatus = RESET;
  251. /* Wait till HSE is ready and if Time out is reached exit */
  252. do
  253. {
  254. HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
  255. StartUpCounter++;
  256. } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET));
  257. if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
  258. {
  259. status = SUCCESS;
  260. }
  261. else
  262. {
  263. status = ERROR;
  264. }
  265. return (status);
  266. }
  267. /**
  268. * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
  269. * @param HSICalibrationValue: specifies the calibration trimming value.
  270. * This parameter must be a number between 0 and 0x1F.
  271. * @retval None
  272. */
  273. void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
  274. {
  275. uint32_t tmpreg = 0;
  276. /* Check the parameters */
  277. assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
  278. tmpreg = RCC->CR;
  279. /* Clear HSITRIM[4:0] bits */
  280. tmpreg &= CR_HSITRIM_Mask;
  281. /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
  282. tmpreg |= (uint32_t)HSICalibrationValue << 3;
  283. /* Store the new value */
  284. RCC->CR = tmpreg;
  285. }
  286. /**
  287. * @brief Enables or disables the Internal High Speed oscillator (HSI).
  288. * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
  289. * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
  290. * @retval None
  291. */
  292. void RCC_HSICmd(FunctionalState NewState)
  293. {
  294. /* Check the parameters */
  295. assert_param(IS_FUNCTIONAL_STATE(NewState));
  296. *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
  297. }
  298. /**
  299. * @brief Configures the PLL clock source and multiplication factor.
  300. * @note This function must be used only when the PLL is disabled.
  301. * @param RCC_PLLSource: specifies the PLL entry clock source.
  302. * For @b STM32_Connectivity_line_devices, this parameter can be one of the
  303. * following values:
  304. * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
  305. * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
  306. * For @b other_STM32_devices, this parameter can be one of the following values:
  307. * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
  308. * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
  309. * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
  310. * @param RCC_PLLMul: specifies the PLL multiplication factor.
  311. * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
  312. * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
  313. * @retval None
  314. */
  315. void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
  316. {
  317. uint32_t tmpreg = 0;
  318. /* Check the parameters */
  319. assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
  320. assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
  321. tmpreg = RCC->CFGR;
  322. /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
  323. tmpreg &= CFGR_PLL_Mask;
  324. /* Set the PLL configuration bits */
  325. tmpreg |= RCC_PLLSource | RCC_PLLMul;
  326. /* Store the new value */
  327. RCC->CFGR = tmpreg;
  328. }
  329. /**
  330. * @brief Enables or disables the PLL.
  331. * @note The PLL can not be disabled if it is used as system clock.
  332. * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
  333. * @retval None
  334. */
  335. void RCC_PLLCmd(FunctionalState NewState)
  336. {
  337. /* Check the parameters */
  338. assert_param(IS_FUNCTIONAL_STATE(NewState));
  339. *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
  340. }
  341. #ifdef STM32F10X_CL
  342. /**
  343. * @brief Configures the PREDIV1 division factor.
  344. * @note
  345. * - This function must be used only when the PLL is disabled.
  346. * - This function applies only to STM32 Connectivity line devices.
  347. * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
  348. * This parameter can be one of the following values:
  349. * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
  350. * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
  351. * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
  352. * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
  353. * @retval None
  354. */
  355. void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
  356. {
  357. uint32_t tmpreg = 0;
  358. /* Check the parameters */
  359. assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
  360. assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
  361. tmpreg = RCC->CFGR2;
  362. /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
  363. tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
  364. /* Set the PREDIV1 clock source and division factor */
  365. tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
  366. /* Store the new value */
  367. RCC->CFGR2 = tmpreg;
  368. }
  369. /**
  370. * @brief Configures the PREDIV2 division factor.
  371. * @note
  372. * - This function must be used only when both PLL2 and PLL3 are disabled.
  373. * - This function applies only to STM32 Connectivity line devices.
  374. * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
  375. * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
  376. * @retval None
  377. */
  378. void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
  379. {
  380. uint32_t tmpreg = 0;
  381. /* Check the parameters */
  382. assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
  383. tmpreg = RCC->CFGR2;
  384. /* Clear PREDIV2[3:0] bits */
  385. tmpreg &= ~CFGR2_PREDIV2;
  386. /* Set the PREDIV2 division factor */
  387. tmpreg |= RCC_PREDIV2_Div;
  388. /* Store the new value */
  389. RCC->CFGR2 = tmpreg;
  390. }
  391. /**
  392. * @brief Configures the PLL2 multiplication factor.
  393. * @note
  394. * - This function must be used only when the PLL2 is disabled.
  395. * - This function applies only to STM32 Connectivity line devices.
  396. * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
  397. * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
  398. * @retval None
  399. */
  400. void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
  401. {
  402. uint32_t tmpreg = 0;
  403. /* Check the parameters */
  404. assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
  405. tmpreg = RCC->CFGR2;
  406. /* Clear PLL2Mul[3:0] bits */
  407. tmpreg &= ~CFGR2_PLL2MUL;
  408. /* Set the PLL2 configuration bits */
  409. tmpreg |= RCC_PLL2Mul;
  410. /* Store the new value */
  411. RCC->CFGR2 = tmpreg;
  412. }
  413. /**
  414. * @brief Enables or disables the PLL2.
  415. * @note
  416. * - The PLL2 can not be disabled if it is used indirectly as system clock
  417. * (i.e. it is used as PLL clock entry that is used as System clock).
  418. * - This function applies only to STM32 Connectivity line devices.
  419. * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
  420. * @retval None
  421. */
  422. void RCC_PLL2Cmd(FunctionalState NewState)
  423. {
  424. /* Check the parameters */
  425. assert_param(IS_FUNCTIONAL_STATE(NewState));
  426. *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
  427. }
  428. /**
  429. * @brief Configures the PLL3 multiplication factor.
  430. * @note
  431. * - This function must be used only when the PLL3 is disabled.
  432. * - This function applies only to STM32 Connectivity line devices.
  433. * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
  434. * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
  435. * @retval None
  436. */
  437. void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
  438. {
  439. uint32_t tmpreg = 0;
  440. /* Check the parameters */
  441. assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
  442. tmpreg = RCC->CFGR2;
  443. /* Clear PLL3Mul[3:0] bits */
  444. tmpreg &= ~CFGR2_PLL3MUL;
  445. /* Set the PLL3 configuration bits */
  446. tmpreg |= RCC_PLL3Mul;
  447. /* Store the new value */
  448. RCC->CFGR2 = tmpreg;
  449. }
  450. /**
  451. * @brief Enables or disables the PLL3.
  452. * @note This function applies only to STM32 Connectivity line devices.
  453. * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
  454. * @retval None
  455. */
  456. void RCC_PLL3Cmd(FunctionalState NewState)
  457. {
  458. /* Check the parameters */
  459. assert_param(IS_FUNCTIONAL_STATE(NewState));
  460. *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
  461. }
  462. #endif /* STM32F10X_CL */
  463. /**
  464. * @brief Configures the system clock (SYSCLK).
  465. * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
  466. * This parameter can be one of the following values:
  467. * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
  468. * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
  469. * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
  470. * @retval None
  471. */
  472. void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
  473. {
  474. uint32_t tmpreg = 0;
  475. /* Check the parameters */
  476. assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
  477. tmpreg = RCC->CFGR;
  478. /* Clear SW[1:0] bits */
  479. tmpreg &= CFGR_SW_Mask;
  480. /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
  481. tmpreg |= RCC_SYSCLKSource;
  482. /* Store the new value */
  483. RCC->CFGR = tmpreg;
  484. }
  485. /**
  486. * @brief Returns the clock source used as system clock.
  487. * @param None
  488. * @retval The clock source used as system clock. The returned value can
  489. * be one of the following:
  490. * - 0x00: HSI used as system clock
  491. * - 0x04: HSE used as system clock
  492. * - 0x08: PLL used as system clock
  493. */
  494. uint8_t RCC_GetSYSCLKSource(void)
  495. {
  496. return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
  497. }
  498. /**
  499. * @brief Configures the AHB clock (HCLK).
  500. * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
  501. * the system clock (SYSCLK).
  502. * This parameter can be one of the following values:
  503. * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
  504. * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  505. * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  506. * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  507. * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  508. * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  509. * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  510. * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  511. * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
  512. * @retval None
  513. */
  514. void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
  515. {
  516. uint32_t tmpreg = 0;
  517. /* Check the parameters */
  518. assert_param(IS_RCC_HCLK(RCC_SYSCLK));
  519. tmpreg = RCC->CFGR;
  520. /* Clear HPRE[3:0] bits */
  521. tmpreg &= CFGR_HPRE_Reset_Mask;
  522. /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
  523. tmpreg |= RCC_SYSCLK;
  524. /* Store the new value */
  525. RCC->CFGR = tmpreg;
  526. }
  527. /**
  528. * @brief Configures the Low Speed APB clock (PCLK1).
  529. * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
  530. * the AHB clock (HCLK).
  531. * This parameter can be one of the following values:
  532. * @arg RCC_HCLK_Div1: APB1 clock = HCLK
  533. * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
  534. * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
  535. * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
  536. * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
  537. * @retval None
  538. */
  539. void RCC_PCLK1Config(uint32_t RCC_HCLK)
  540. {
  541. uint32_t tmpreg = 0;
  542. /* Check the parameters */
  543. assert_param(IS_RCC_PCLK(RCC_HCLK));
  544. tmpreg = RCC->CFGR;
  545. /* Clear PPRE1[2:0] bits */
  546. tmpreg &= CFGR_PPRE1_Reset_Mask;
  547. /* Set PPRE1[2:0] bits according to RCC_HCLK value */
  548. tmpreg |= RCC_HCLK;
  549. /* Store the new value */
  550. RCC->CFGR = tmpreg;
  551. }
  552. /**
  553. * @brief Configures the High Speed APB clock (PCLK2).
  554. * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
  555. * the AHB clock (HCLK).
  556. * This parameter can be one of the following values:
  557. * @arg RCC_HCLK_Div1: APB2 clock = HCLK
  558. * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
  559. * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
  560. * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
  561. * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
  562. * @retval None
  563. */
  564. void RCC_PCLK2Config(uint32_t RCC_HCLK)
  565. {
  566. uint32_t tmpreg = 0;
  567. /* Check the parameters */
  568. assert_param(IS_RCC_PCLK(RCC_HCLK));
  569. tmpreg = RCC->CFGR;
  570. /* Clear PPRE2[2:0] bits */
  571. tmpreg &= CFGR_PPRE2_Reset_Mask;
  572. /* Set PPRE2[2:0] bits according to RCC_HCLK value */
  573. tmpreg |= RCC_HCLK << 3;
  574. /* Store the new value */
  575. RCC->CFGR = tmpreg;
  576. }
  577. /**
  578. * @brief Enables or disables the specified RCC interrupts.
  579. * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
  580. *
  581. * For @b STM32_Connectivity_line_devices, this parameter can be any combination
  582. * of the following values
  583. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  584. * @arg RCC_IT_LSERDY: LSE ready interrupt
  585. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  586. * @arg RCC_IT_HSERDY: HSE ready interrupt
  587. * @arg RCC_IT_PLLRDY: PLL ready interrupt
  588. * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
  589. * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
  590. *
  591. * For @b other_STM32_devices, this parameter can be any combination of the
  592. * following values
  593. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  594. * @arg RCC_IT_LSERDY: LSE ready interrupt
  595. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  596. * @arg RCC_IT_HSERDY: HSE ready interrupt
  597. * @arg RCC_IT_PLLRDY: PLL ready interrupt
  598. *
  599. * @param NewState: new state of the specified RCC interrupts.
  600. * This parameter can be: ENABLE or DISABLE.
  601. * @retval None
  602. */
  603. void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
  604. {
  605. /* Check the parameters */
  606. assert_param(IS_RCC_IT(RCC_IT));
  607. assert_param(IS_FUNCTIONAL_STATE(NewState));
  608. if (NewState != DISABLE)
  609. {
  610. /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
  611. *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
  612. }
  613. else
  614. {
  615. /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
  616. *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
  617. }
  618. }
  619. #ifndef STM32F10X_CL
  620. /**
  621. * @brief Configures the USB clock (USBCLK).
  622. * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
  623. * derived from the PLL output.
  624. * This parameter can be one of the following values:
  625. * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
  626. * clock source
  627. * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
  628. * @retval None
  629. */
  630. void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
  631. {
  632. /* Check the parameters */
  633. assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
  634. *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
  635. }
  636. #else
  637. /**
  638. * @brief Configures the USB OTG FS clock (OTGFSCLK).
  639. * This function applies only to STM32 Connectivity line devices.
  640. * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
  641. * This clock is derived from the PLL output.
  642. * This parameter can be one of the following values:
  643. * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
  644. * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
  645. * @retval None
  646. */
  647. void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
  648. {
  649. /* Check the parameters */
  650. assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
  651. *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
  652. }
  653. #endif /* STM32F10X_CL */
  654. /**
  655. * @brief Configures the ADC clock (ADCCLK).
  656. * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
  657. * the APB2 clock (PCLK2).
  658. * This parameter can be one of the following values:
  659. * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
  660. * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
  661. * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
  662. * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
  663. * @retval None
  664. */
  665. void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
  666. {
  667. uint32_t tmpreg = 0;
  668. /* Check the parameters */
  669. assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
  670. tmpreg = RCC->CFGR;
  671. /* Clear ADCPRE[1:0] bits */
  672. tmpreg &= CFGR_ADCPRE_Reset_Mask;
  673. /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
  674. tmpreg |= RCC_PCLK2;
  675. /* Store the new value */
  676. RCC->CFGR = tmpreg;
  677. }
  678. #ifdef STM32F10X_CL
  679. /**
  680. * @brief Configures the I2S2 clock source(I2S2CLK).
  681. * @note
  682. * - This function must be called before enabling I2S2 APB clock.
  683. * - This function applies only to STM32 Connectivity line devices.
  684. * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
  685. * This parameter can be one of the following values:
  686. * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
  687. * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
  688. * @retval None
  689. */
  690. void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
  691. {
  692. /* Check the parameters */
  693. assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
  694. *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
  695. }
  696. /**
  697. * @brief Configures the I2S3 clock source(I2S2CLK).
  698. * @note
  699. * - This function must be called before enabling I2S3 APB clock.
  700. * - This function applies only to STM32 Connectivity line devices.
  701. * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
  702. * This parameter can be one of the following values:
  703. * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
  704. * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
  705. * @retval None
  706. */
  707. void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
  708. {
  709. /* Check the parameters */
  710. assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
  711. *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
  712. }
  713. #endif /* STM32F10X_CL */
  714. /**
  715. * @brief Configures the External Low Speed oscillator (LSE).
  716. * @param RCC_LSE: specifies the new state of the LSE.
  717. * This parameter can be one of the following values:
  718. * @arg RCC_LSE_OFF: LSE oscillator OFF
  719. * @arg RCC_LSE_ON: LSE oscillator ON
  720. * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
  721. * @retval None
  722. */
  723. void RCC_LSEConfig(uint8_t RCC_LSE)
  724. {
  725. /* Check the parameters */
  726. assert_param(IS_RCC_LSE(RCC_LSE));
  727. /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
  728. /* Reset LSEON bit */
  729. *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
  730. /* Reset LSEBYP bit */
  731. *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
  732. /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
  733. switch(RCC_LSE)
  734. {
  735. case RCC_LSE_ON:
  736. /* Set LSEON bit */
  737. *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
  738. break;
  739. case RCC_LSE_Bypass:
  740. /* Set LSEBYP and LSEON bits */
  741. *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
  742. break;
  743. default:
  744. break;
  745. }
  746. }
  747. /**
  748. * @brief Enables or disables the Internal Low Speed oscillator (LSI).
  749. * @note LSI can not be disabled if the IWDG is running.
  750. * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
  751. * @retval None
  752. */
  753. void RCC_LSICmd(FunctionalState NewState)
  754. {
  755. /* Check the parameters */
  756. assert_param(IS_FUNCTIONAL_STATE(NewState));
  757. *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
  758. }
  759. /**
  760. * @brief Configures the RTC clock (RTCCLK).
  761. * @note Once the RTC clock is selected it can’t be changed unless the Backup domain is reset.
  762. * @param RCC_RTCCLKSource: specifies the RTC clock source.
  763. * This parameter can be one of the following values:
  764. * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  765. * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  766. * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
  767. * @retval None
  768. */
  769. void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
  770. {
  771. /* Check the parameters */
  772. assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
  773. /* Select the RTC clock source */
  774. RCC->BDCR |= RCC_RTCCLKSource;
  775. }
  776. /**
  777. * @brief Enables or disables the RTC clock.
  778. * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
  779. * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
  780. * @retval None
  781. */
  782. void RCC_RTCCLKCmd(FunctionalState NewState)
  783. {
  784. /* Check the parameters */
  785. assert_param(IS_FUNCTIONAL_STATE(NewState));
  786. *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
  787. }
  788. /**
  789. * @brief Returns the frequencies of different on chip clocks.
  790. * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
  791. * the clocks frequencies.
  792. * @retval None
  793. */
  794. void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
  795. {
  796. uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
  797. #ifdef STM32F10X_CL
  798. uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
  799. #endif /* STM32F10X_CL */
  800. /* Get SYSCLK source -------------------------------------------------------*/
  801. tmp = RCC->CFGR & CFGR_SWS_Mask;
  802. switch (tmp)
  803. {
  804. case 0x00: /* HSI used as system clock */
  805. RCC_Clocks->SYSCLK_Frequency = HSI_Value;
  806. break;
  807. case 0x04: /* HSE used as system clock */
  808. RCC_Clocks->SYSCLK_Frequency = HSE_Value;
  809. break;
  810. case 0x08: /* PLL used as system clock */
  811. /* Get PLL clock source and multiplication factor ----------------------*/
  812. pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
  813. pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
  814. #ifndef STM32F10X_CL
  815. pllmull = ( pllmull >> 18) + 2;
  816. if (pllsource == 0x00)
  817. {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
  818. RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
  819. }
  820. else
  821. {/* HSE selected as PLL clock entry */
  822. if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
  823. {/* HSE oscillator clock divided by 2 */
  824. RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
  825. }
  826. else
  827. {
  828. RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
  829. }
  830. }
  831. #else
  832. pllmull = pllmull >> 18;
  833. if (pllmull != 0x0D)
  834. {
  835. pllmull += 2;
  836. }
  837. else
  838. { /* PLL multiplication factor = PLL input clock * 6.5 */
  839. pllmull = 13 / 2;
  840. }
  841. if (pllsource == 0x00)
  842. {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
  843. RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
  844. }
  845. else
  846. {/* PREDIV1 selected as PLL clock entry */
  847. /* Get PREDIV1 clock source and division factor */
  848. prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
  849. prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
  850. if (prediv1source == 0)
  851. { /* HSE oscillator clock selected as PREDIV1 clock entry */
  852. RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull;
  853. }
  854. else
  855. {/* PLL2 clock selected as PREDIV1 clock entry */
  856. /* Get PREDIV2 division factor and PLL2 multiplication factor */
  857. prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
  858. pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
  859. RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
  860. }
  861. }
  862. #endif /* STM32F10X_CL */
  863. break;
  864. default:
  865. RCC_Clocks->SYSCLK_Frequency = HSI_Value;
  866. break;
  867. }
  868. /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
  869. /* Get HCLK prescaler */
  870. tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
  871. tmp = tmp >> 4;
  872. presc = APBAHBPrescTable[tmp];
  873. /* HCLK clock frequency */
  874. RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
  875. /* Get PCLK1 prescaler */
  876. tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
  877. tmp = tmp >> 8;
  878. presc = APBAHBPrescTable[tmp];
  879. /* PCLK1 clock frequency */
  880. RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  881. /* Get PCLK2 prescaler */
  882. tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
  883. tmp = tmp >> 11;
  884. presc = APBAHBPrescTable[tmp];
  885. /* PCLK2 clock frequency */
  886. RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  887. /* Get ADCCLK prescaler */
  888. tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
  889. tmp = tmp >> 14;
  890. presc = ADCPrescTable[tmp];
  891. /* ADCCLK clock frequency */
  892. RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
  893. }
  894. /**
  895. * @brief Enables or disables the AHB peripheral clock.
  896. * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
  897. *
  898. * For @b STM32_Connectivity_line_devices, this parameter can be any combination
  899. * of the following values:
  900. * @arg RCC_AHBPeriph_DMA1
  901. * @arg RCC_AHBPeriph_DMA2
  902. * @arg RCC_AHBPeriph_SRAM
  903. * @arg RCC_AHBPeriph_FLITF
  904. * @arg RCC_AHBPeriph_CRC
  905. * @arg RCC_AHBPeriph_OTG_FS
  906. * @arg RCC_AHBPeriph_ETH_MAC
  907. * @arg RCC_AHBPeriph_ETH_MAC_Tx
  908. * @arg RCC_AHBPeriph_ETH_MAC_Rx
  909. *
  910. * For @b other_STM32_devices, this parameter can be any combination of the
  911. * following values:
  912. * @arg RCC_AHBPeriph_DMA1
  913. * @arg RCC_AHBPeriph_DMA2
  914. * @arg RCC_AHBPeriph_SRAM
  915. * @arg RCC_AHBPeriph_FLITF
  916. * @arg RCC_AHBPeriph_CRC
  917. * @arg RCC_AHBPeriph_FSMC
  918. * @arg RCC_AHBPeriph_SDIO
  919. *
  920. * @note SRAM and FLITF clock can be disabled only during sleep mode.
  921. * @param NewState: new state of the specified peripheral clock.
  922. * This parameter can be: ENABLE or DISABLE.
  923. * @retval None
  924. */
  925. void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
  926. {
  927. /* Check the parameters */
  928. assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
  929. assert_param(IS_FUNCTIONAL_STATE(NewState));
  930. if (NewState != DISABLE)
  931. {
  932. RCC->AHBENR |= RCC_AHBPeriph;
  933. }
  934. else
  935. {
  936. RCC->AHBENR &= ~RCC_AHBPeriph;
  937. }
  938. }
  939. /**
  940. * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
  941. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
  942. * This parameter can be any combination of the following values:
  943. * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
  944. * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
  945. * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
  946. * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
  947. * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
  948. * @param NewState: new state of the specified peripheral clock.
  949. * This parameter can be: ENABLE or DISABLE.
  950. * @retval None
  951. */
  952. void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
  953. {
  954. /* Check the parameters */
  955. assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  956. assert_param(IS_FUNCTIONAL_STATE(NewState));
  957. if (NewState != DISABLE)
  958. {
  959. RCC->APB2ENR |= RCC_APB2Periph;
  960. }
  961. else
  962. {
  963. RCC->APB2ENR &= ~RCC_APB2Periph;
  964. }
  965. }
  966. /**
  967. * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
  968. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
  969. * This parameter can be any combination of the following values:
  970. * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
  971. * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
  972. * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
  973. * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
  974. * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
  975. * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
  976. * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
  977. * @param NewState: new state of the specified peripheral clock.
  978. * This parameter can be: ENABLE or DISABLE.
  979. * @retval None
  980. */
  981. void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
  982. {
  983. /* Check the parameters */
  984. assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  985. assert_param(IS_FUNCTIONAL_STATE(NewState));
  986. if (NewState != DISABLE)
  987. {
  988. RCC->APB1ENR |= RCC_APB1Periph;
  989. }
  990. else
  991. {
  992. RCC->APB1ENR &= ~RCC_APB1Periph;
  993. }
  994. }
  995. #ifdef STM32F10X_CL
  996. /**
  997. * @brief Forces or releases AHB peripheral reset.
  998. * @note This function applies only to STM32 Connectivity line devices.
  999. * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
  1000. * This parameter can be any combination of the following values:
  1001. * @arg RCC_AHBPeriph_OTG_FS
  1002. * @arg RCC_AHBPeriph_ETH_MAC
  1003. * @param NewState: new state of the specified peripheral reset.
  1004. * This parameter can be: ENABLE or DISABLE.
  1005. * @retval None
  1006. */
  1007. void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
  1008. {
  1009. /* Check the parameters */
  1010. assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
  1011. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1012. if (NewState != DISABLE)
  1013. {
  1014. RCC->AHBRSTR |= RCC_AHBPeriph;
  1015. }
  1016. else
  1017. {
  1018. RCC->AHBRSTR &= ~RCC_AHBPeriph;
  1019. }
  1020. }
  1021. #endif /* STM32F10X_CL */
  1022. /**
  1023. * @brief Forces or releases High Speed APB (APB2) peripheral reset.
  1024. * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
  1025. * This parameter can be any combination of the following values:
  1026. * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
  1027. * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
  1028. * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
  1029. * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
  1030. * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
  1031. * @param NewState: new state of the specified peripheral reset.
  1032. * This parameter can be: ENABLE or DISABLE.
  1033. * @retval None
  1034. */
  1035. void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
  1036. {
  1037. /* Check the parameters */
  1038. assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  1039. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1040. if (NewState != DISABLE)
  1041. {
  1042. RCC->APB2RSTR |= RCC_APB2Periph;
  1043. }
  1044. else
  1045. {
  1046. RCC->APB2RSTR &= ~RCC_APB2Periph;
  1047. }
  1048. }
  1049. /**
  1050. * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
  1051. * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
  1052. * This parameter can be any combination of the following values:
  1053. * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
  1054. * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
  1055. * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
  1056. * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
  1057. * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
  1058. * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
  1059. * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
  1060. * @param NewState: new state of the specified peripheral clock.
  1061. * This parameter can be: ENABLE or DISABLE.
  1062. * @retval None
  1063. */
  1064. void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
  1065. {
  1066. /* Check the parameters */
  1067. assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  1068. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1069. if (NewState != DISABLE)
  1070. {
  1071. RCC->APB1RSTR |= RCC_APB1Periph;
  1072. }
  1073. else
  1074. {
  1075. RCC->APB1RSTR &= ~RCC_APB1Periph;
  1076. }
  1077. }
  1078. /**
  1079. * @brief Forces or releases the Backup domain reset.
  1080. * @param NewState: new state of the Backup domain reset.
  1081. * This parameter can be: ENABLE or DISABLE.
  1082. * @retval None
  1083. */
  1084. void RCC_BackupResetCmd(FunctionalState NewState)
  1085. {
  1086. /* Check the parameters */
  1087. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1088. *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
  1089. }
  1090. /**
  1091. * @brief Enables or disables the Clock Security System.
  1092. * @param NewState: new state of the Clock Security System..
  1093. * This parameter can be: ENABLE or DISABLE.
  1094. * @retval None
  1095. */
  1096. void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
  1097. {
  1098. /* Check the parameters */
  1099. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1100. *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
  1101. }
  1102. /**
  1103. * @brief Selects the clock source to output on MCO pin.
  1104. * @param RCC_MCO: specifies the clock source to output.
  1105. *
  1106. * For @b STM32_Connectivity_line_devices, this parameter can be one of the
  1107. * following values:
  1108. * @arg RCC_MCO_NoClock: No clock selected
  1109. * @arg RCC_MCO_SYSCLK: System clock selected
  1110. * @arg RCC_MCO_HSI: HSI oscillator clock selected
  1111. * @arg RCC_MCO_HSE: HSE oscillator clock selected
  1112. * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
  1113. * @arg RCC_MCO_PLL2CLK: PLL2 clock selected
  1114. * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
  1115. * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
  1116. * @arg RCC_MCO_PLL3CLK: PLL3 clock selected
  1117. *
  1118. * For @b other_STM32_devices, this parameter can be one of the following values:
  1119. * @arg RCC_MCO_NoClock: No clock selected
  1120. * @arg RCC_MCO_SYSCLK: System clock selected
  1121. * @arg RCC_MCO_HSI: HSI oscillator clock selected
  1122. * @arg RCC_MCO_HSE: HSE oscillator clock selected
  1123. * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
  1124. *
  1125. * @retval None
  1126. */
  1127. void RCC_MCOConfig(uint8_t RCC_MCO)
  1128. {
  1129. /* Check the parameters */
  1130. assert_param(IS_RCC_MCO(RCC_MCO));
  1131. /* Perform Byte access to MCO bits to select the MCO source */
  1132. *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
  1133. }
  1134. /**
  1135. * @brief Checks whether the specified RCC flag is set or not.
  1136. * @param RCC_FLAG: specifies the flag to check.
  1137. *
  1138. * For @b STM32_Connectivity_line_devices, this parameter can be one of the
  1139. * following values:
  1140. * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
  1141. * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
  1142. * @arg RCC_FLAG_PLLRDY: PLL clock ready
  1143. * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
  1144. * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
  1145. * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
  1146. * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
  1147. * @arg RCC_FLAG_PINRST: Pin reset
  1148. * @arg RCC_FLAG_PORRST: POR/PDR reset
  1149. * @arg RCC_FLAG_SFTRST: Software reset
  1150. * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
  1151. * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
  1152. * @arg RCC_FLAG_LPWRRST: Low Power reset
  1153. *
  1154. * For @b other_STM32_devices, this parameter can be one of the following values:
  1155. * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
  1156. * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
  1157. * @arg RCC_FLAG_PLLRDY: PLL clock ready
  1158. * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
  1159. * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
  1160. * @arg RCC_FLAG_PINRST: Pin reset
  1161. * @arg RCC_FLAG_PORRST: POR/PDR reset
  1162. * @arg RCC_FLAG_SFTRST: Software reset
  1163. * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
  1164. * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
  1165. * @arg RCC_FLAG_LPWRRST: Low Power reset
  1166. *
  1167. * @retval The new state of RCC_FLAG (SET or RESET).
  1168. */
  1169. FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
  1170. {
  1171. uint32_t tmp = 0;
  1172. uint32_t statusreg = 0;
  1173. FlagStatus bitstatus = RESET;
  1174. /* Check the parameters */
  1175. assert_param(IS_RCC_FLAG(RCC_FLAG));
  1176. /* Get the RCC register index */
  1177. tmp = RCC_FLAG >> 5;
  1178. if (tmp == 1) /* The flag to check is in CR register */
  1179. {
  1180. statusreg = RCC->CR;
  1181. }
  1182. else if (tmp == 2) /* The flag to check is in BDCR register */
  1183. {
  1184. statusreg = RCC->BDCR;
  1185. }
  1186. else /* The flag to check is in CSR register */
  1187. {
  1188. statusreg = RCC->CSR;
  1189. }
  1190. /* Get the flag position */
  1191. tmp = RCC_FLAG & FLAG_Mask;
  1192. if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
  1193. {
  1194. bitstatus = SET;
  1195. }
  1196. else
  1197. {
  1198. bitstatus = RESET;
  1199. }
  1200. /* Return the flag status */
  1201. return bitstatus;
  1202. }
  1203. /**
  1204. * @brief Clears the RCC reset flags.
  1205. * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
  1206. * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
  1207. * @param None
  1208. * @retval None
  1209. */
  1210. void RCC_ClearFlag(void)
  1211. {
  1212. /* Set RMVF bit to clear the reset flags */
  1213. RCC->CSR |= CSR_RMVF_Set;
  1214. }
  1215. /**
  1216. * @brief Checks whether the specified RCC interrupt has occurred or not.
  1217. * @param RCC_IT: specifies the RCC interrupt source to check.
  1218. *
  1219. * For @b STM32_Connectivity_line_devices, this parameter can be one of the
  1220. * following values:
  1221. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  1222. * @arg RCC_IT_LSERDY: LSE ready interrupt
  1223. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  1224. * @arg RCC_IT_HSERDY: HSE ready interrupt
  1225. * @arg RCC_IT_PLLRDY: PLL ready interrupt
  1226. * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
  1227. * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
  1228. * @arg RCC_IT_CSS: Clock Security System interrupt
  1229. *
  1230. * For @b other_STM32_devices, this parameter can be one of the following values:
  1231. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  1232. * @arg RCC_IT_LSERDY: LSE ready interrupt
  1233. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  1234. * @arg RCC_IT_HSERDY: HSE ready interrupt
  1235. * @arg RCC_IT_PLLRDY: PLL ready interrupt
  1236. * @arg RCC_IT_CSS: Clock Security System interrupt
  1237. *
  1238. * @retval The new state of RCC_IT (SET or RESET).
  1239. */
  1240. ITStatus RCC_GetITStatus(uint8_t RCC_IT)
  1241. {
  1242. ITStatus bitstatus = RESET;
  1243. /* Check the parameters */
  1244. assert_param(IS_RCC_GET_IT(RCC_IT));
  1245. /* Check the status of the specified RCC interrupt */
  1246. if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
  1247. {
  1248. bitstatus = SET;
  1249. }
  1250. else
  1251. {
  1252. bitstatus = RESET;
  1253. }
  1254. /* Return the RCC_IT status */
  1255. return bitstatus;
  1256. }
  1257. /**
  1258. * @brief Clears the RCC’s interrupt pending bits.
  1259. * @param RCC_IT: specifies the interrupt pending bit to clear.
  1260. *
  1261. * For @b STM32_Connectivity_line_devices, this parameter can be any combination
  1262. * of the following values:
  1263. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  1264. * @arg RCC_IT_LSERDY: LSE ready interrupt
  1265. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  1266. * @arg RCC_IT_HSERDY: HSE ready interrupt
  1267. * @arg RCC_IT_PLLRDY: PLL ready interrupt
  1268. * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
  1269. * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
  1270. * @arg RCC_IT_CSS: Clock Security System interrupt
  1271. *
  1272. * For @b other_STM32_devices, this parameter can be any combination of the
  1273. * following values:
  1274. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  1275. * @arg RCC_IT_LSERDY: LSE ready interrupt
  1276. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  1277. * @arg RCC_IT_HSERDY: HSE ready interrupt
  1278. * @arg RCC_IT_PLLRDY: PLL ready interrupt
  1279. *
  1280. * @arg RCC_IT_CSS: Clock Security System interrupt
  1281. * @retval None
  1282. */
  1283. void RCC_ClearITPendingBit(uint8_t RCC_IT)
  1284. {
  1285. /* Check the parameters */
  1286. assert_param(IS_RCC_CLEAR_IT(RCC_IT));
  1287. /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
  1288. pending bits */
  1289. *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
  1290. }
  1291. /**
  1292. * @}
  1293. */
  1294. /**
  1295. * @}
  1296. */
  1297. /**
  1298. * @}
  1299. */
  1300. /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/