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gicv3.h

gicv3.h 9.4 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2006-2023, RT-Thread Development Team
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  *
    6. 

  6.  * Change Logs:
    7. 

  7.  * Date           Author       Notes
    8. 

  8.  * 2013-07-20     Bernard      first version
    9. 

  9.  * 2014-04-03     Grissiom     many enhancements
    10. 

  10.  * 2018-11-22     Jesven       add rt_hw_ipi_send()
    11. 

  11.  *                             add rt_hw_ipi_handler_install()
    12. 

  12.  */
    13. 

  13. 

  14. #ifndef __GICV3_H__
    15. 

  15. #define __GICV3_H__
    16. 

  16. 

  17. #include <rtdef.h>
    18. 

  18. 

  19. #if defined(BSP_USING_GIC) && defined(BSP_USING_GICV3)
    20. 

  20. 

  21. 

  22. #ifndef ARM_GIC_CPU_NUM
    23. 

  23. #define ARM_GIC_CPU_NUM RT_CPUS_NR
    24. 

  24. #endif
    25. 

  25. 

  26. #define GICV3_ROUTED_TO_ALL   1UL
    27. 

  27. #define GICV3_ROUTED_TO_SPEC  0UL
    28. 

  28. #define GET_GICV3_REG(reg, out) __asm__ volatile ("mrs %0, " reg:"=r"(out)::"memory");
    29. 

  29. #define SET_GICV3_REG(reg, in)  __asm__ volatile ("msr " reg ", %0"::"r"(in):"memory");
    30. 

  30. 

  31. /* AArch64 System register interface to GICv3 */
    32. 

  32. #define ICC_IAR0_EL1    "S3_0_C12_C8_0"
    33. 

  33. #define ICC_IAR1_EL1    "S3_0_C12_C12_0"
    34. 

  34. #define ICC_EOIR0_EL1   "S3_0_C12_C8_1"
    35. 

  35. #define ICC_EOIR1_EL1   "S3_0_C12_C12_1"
    36. 

  36. #define ICC_HPPIR0_EL1  "S3_0_C12_C8_2"
    37. 

  37. #define ICC_HPPIR1_EL1  "S3_0_C12_C12_2"
    38. 

  38. #define ICC_BPR0_EL1    "S3_0_C12_C8_3"
    39. 

  39. #define ICC_BPR1_EL1    "S3_0_C12_C12_3"
    40. 

  40. #define ICC_DIR_EL1     "S3_0_C12_C11_1"
    41. 

  41. #define ICC_PMR_EL1     "S3_0_C4_C6_0"
    42. 

  42. #define ICC_RPR_EL1     "S3_0_C12_C11_3"
    43. 

  43. #define ICC_CTLR_EL1    "S3_0_C12_C12_4"
    44. 

  44. #define ICC_CTLR_EL3    "S3_6_C12_C12_4"
    45. 

  45. #define ICC_SRE_EL1     "S3_0_C12_C12_5"
    46. 

  46. #define ICC_SRE_EL2     "S3_4_C12_C9_5"
    47. 

  47. #define ICC_SRE_EL3     "S3_6_C12_C12_5"
    48. 

  48. #define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6"
    49. 

  49. #define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7"
    50. 

  50. #define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7"
    51. 

  51. #define ICC_SGI0R_EL1   "S3_0_C12_C11_7"
    52. 

  52. #define ICC_SGI1R_EL1   "S3_0_C12_C11_5"
    53. 

  53. #define ICC_ASGI1R_EL1  "S3_0_C12_C11_6"
    54. 

  54. 

  55. /* Macro to access the Distributor Control Register (GICD_CTLR) */
    56. 

  56. #define GICD_CTLR_RWP       (1U << 31)
    57. 

  57. #define GICD_CTLR_E1NWF     (1U << 7)
    58. 

  58. #define GICD_CTLR_DS        (1U << 6)
    59. 

  59. #define GICD_CTLR_ARE_NS    (1U << 5)
    60. 

  60. #define GICD_CTLR_ARE_S     (1U << 4)
    61. 

  61. #define GICD_CTLR_ENGRP1S   (1U << 2)
    62. 

  62. #define GICD_CTLR_ENGRP1NS  (1U << 1)
    63. 

  63. #define GICD_CTLR_ENGRP0    (1U << 0)
    64. 

  64. 

  65. /* Macro to access the Redistributor Control Register (GICR_CTLR) */
    66. 

  66. #define GICR_CTLR_UWP       (1U << 31)
    67. 

  67. #define GICR_CTLR_DPG1S     (1U << 26)
    68. 

  68. #define GICR_CTLR_DPG1NS    (1U << 25)
    69. 

  69. #define GICR_CTLR_DPG0      (1U << 24)
    70. 

  70. #define GICR_CTLR_RWP       (1U << 3)
    71. 

  71. #define GICR_CTLR_IR        (1U << 2)
    72. 

  72. #define GICR_CTLR_CES       (1U << 1)
    73. 

  73. #define GICR_CTLR_EnableLPI (1U << 0)
    74. 

  74. 

  75. /* Macro to access the Generic Interrupt Controller Interface (GICC) */
    76. 

  76. #define GIC_CPU_CTRL(hw_base)               HWREG32((hw_base) + 0x00U)
    77. 

  77. #define GIC_CPU_PRIMASK(hw_base)            HWREG32((hw_base) + 0x04U)
    78. 

  78. #define GIC_CPU_BINPOINT(hw_base)           HWREG32((hw_base) + 0x08U)
    79. 

  79. #define GIC_CPU_INTACK(hw_base)             HWREG32((hw_base) + 0x0cU)
    80. 

  80. #define GIC_CPU_EOI(hw_base)                HWREG32((hw_base) + 0x10U)
    81. 

  81. #define GIC_CPU_RUNNINGPRI(hw_base)         HWREG32((hw_base) + 0x14U)
    82. 

  82. #define GIC_CPU_HIGHPRI(hw_base)            HWREG32((hw_base) + 0x18U)
    83. 

  83. #define GIC_CPU_IIDR(hw_base)               HWREG32((hw_base) + 0xFCU)
    84. 

  84. 

  85. /* Macro to access the Generic Interrupt Controller Distributor (GICD) */
    86. 

  86. #define GIC_DIST_CTRL(hw_base)              HWREG32((hw_base) + 0x000U)
    87. 

  87. #define GIC_DIST_TYPE(hw_base)              HWREG32((hw_base) + 0x004U)
    88. 

  88. #define GIC_DIST_IIDR(hw_base)              HWREG32((hw_base) + 0x008U)
    89. 

  89. #define GIC_DIST_IGROUP(hw_base, n)         HWREG32((hw_base) + 0x080U + ((n) / 32U) * 4U)
    90. 

  90. #define GIC_DIST_ENABLE_SET(hw_base, n)     HWREG32((hw_base) + 0x100U + ((n) / 32U) * 4U)
    91. 

  91. #define GIC_DIST_ENABLE_CLEAR(hw_base, n)   HWREG32((hw_base) + 0x180U + ((n) / 32U) * 4U)
    92. 

  92. #define GIC_DIST_PENDING_SET(hw_base, n)    HWREG32((hw_base) + 0x200U + ((n) / 32U) * 4U)
    93. 

  93. #define GIC_DIST_PENDING_CLEAR(hw_base, n)  HWREG32((hw_base) + 0x280U + ((n) / 32U) * 4U)
    94. 

  94. #define GIC_DIST_ACTIVE_SET(hw_base, n)     HWREG32((hw_base) + 0x300U + ((n) / 32U) * 4U)
    95. 

  95. #define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   HWREG32((hw_base) + 0x380U + ((n) / 32U) * 4U)
    96. 

  96. #define GIC_DIST_PRI(hw_base, n)            HWREG32((hw_base) + 0x400U + ((n) / 4U) * 4U)
    97. 

  97. #define GIC_DIST_TARGET(hw_base, n)         HWREG32((hw_base) + 0x800U + ((n) / 4U) * 4U)
    98. 

  98. #define GIC_DIST_CONFIG(hw_base, n)         HWREG32((hw_base) + 0xc00U + ((n) / 16U) * 4U)
    99. 

  99. #define GIC_DIST_SOFTINT(hw_base)           HWREG32((hw_base) + 0xf00U)
    100. 

  100. #define GIC_DIST_CPENDSGI(hw_base, n)       HWREG32((hw_base) + 0xf10U + ((n) / 4U) * 4U)
    101. 

  101. #define GIC_DIST_SPENDSGI(hw_base, n)       HWREG32((hw_base) + 0xf20U + ((n) / 4U) * 4U)
    102. 

  102. #define GIC_DIST_ICPIDR2(hw_base)           HWREG32((hw_base) + 0xfe8U)
    103. 

  103. #define GIC_DIST_IROUTER(hw_base, n)        HWREG64((hw_base) + 0x6000U + (n) * 8U)
    104. 

  104. 

  105. /* SGI base address is at 64K offset from Redistributor base address */
    106. 

  106. #define GIC_RSGI_OFFSET 0x10000
    107. 

  107. 

  108. /* Macro to access the Generic Interrupt Controller Redistributor (GICR) */
    109. 

  109. #define GIC_RDIST_CTRL(hw_base)             HWREG32((hw_base) + 0x000U)
    110. 

  110. #define GIC_RDIST_IIDR(hw_base)             HWREG32((hw_base) + 0x004U)
    111. 

  111. #define GIC_RDIST_TYPER(hw_base)            HWREG64((hw_base) + 0x008U)
    112. 

  112. #define GIC_RDIST_TSTATUSR(hw_base)         HWREG32((hw_base) + 0x010U)
    113. 

  113. #define GIC_RDIST_WAKER(hw_base)            HWREG32((hw_base) + 0x014U)
    114. 

  114. #define GIC_RDIST_SETLPIR(hw_base)          HWREG32((hw_base) + 0x040U)
    115. 

  115. #define GIC_RDIST_CLRLPIR(hw_base)          HWREG32((hw_base) + 0x048U)
    116. 

  116. #define GIC_RDIST_PROPBASER(hw_base)        HWREG32((hw_base) + 0x070U)
    117. 

  117. #define GIC_RDIST_PENDBASER(hw_base)        HWREG32((hw_base) + 0x078U)
    118. 

  118. #define GIC_RDIST_INVLPIR(hw_base)          HWREG32((hw_base) + 0x0A0U)
    119. 

  119. #define GIC_RDIST_INVALLR(hw_base)          HWREG32((hw_base) + 0x0B0U)
    120. 

  120. #define GIC_RDIST_SYNCR(hw_base)            HWREG32((hw_base) + 0x0C0U)
    121. 

  121. 

  122. #define GIC_RDISTSGI_IGROUPR0(hw_base, n)   HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n) * 4U)
    123. 

  123. #define GIC_RDISTSGI_ISENABLER0(hw_base)    HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x100U)
    124. 

  124. #define GIC_RDISTSGI_ICENABLER0(hw_base)    HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x180U)
    125. 

  125. #define GIC_RDISTSGI_ISPENDR0(hw_base)      HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x200U)
    126. 

  126. #define GIC_RDISTSGI_ICPENDR0(hw_base)      HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x280U)
    127. 

  127. #define GIC_RDISTSGI_ISACTIVER0(hw_base)    HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x300U)
    128. 

  128. #define GIC_RDISTSGI_ICACTIVER0(hw_base)    HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x380U)
    129. 

  129. #define GIC_RDISTSGI_IPRIORITYR(hw_base, n) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U)
    130. 

  130. #define GIC_RDISTSGI_ICFGR0(hw_base)        HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U)
    131. 

  131. #define GIC_RDISTSGI_ICFGR1(hw_base)        HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U)
    132. 

  132. #define GIC_RDISTSGI_IGRPMODR0(hw_base, n)  HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n) * 4)
    133. 

  133. #define GIC_RDISTSGI_NSACR(hw_base)         HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U)
    134. 

  134. 

  135. struct arm_gic
    136. 

  136. {
    137. 

  137.     rt_uint64_t offset;                     /* the first interrupt index in the vector table */
    138. 

  138.     rt_uint64_t redist_hw_base[ARM_GIC_CPU_NUM]; /* the pointer of the gic redistributor */
    139. 

  139.     rt_uint64_t dist_hw_base;               /* the base address of the gic distributor */
    140. 

  140.     rt_uint64_t cpu_hw_base[ARM_GIC_CPU_NUM];    /* the base address of the gic cpu interface */
    141. 

  141. };
    142. 

  142. 

  143. int arm_gic_get_active_irq(rt_uint64_t index);
    144. 

  144. void arm_gic_ack(rt_uint64_t index, int irq);
    145. 

  145. 

  146. void arm_gic_mask(rt_uint64_t index, int irq);
    147. 

  147. void arm_gic_umask(rt_uint64_t index, int irq);
    148. 

  148. 

  149. rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq);
    150. 

  150. void arm_gic_set_pending_irq(rt_uint64_t index, int irq);
    151. 

  151. void arm_gic_clear_pending_irq(rt_uint64_t index, int irq);
    152. 

  152. 

  153. void arm_gic_set_configuration(rt_uint64_t index, int irq, rt_uint32_t config);
    154. 

  154. rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq);
    155. 

  155. 

  156. void arm_gic_clear_active(rt_uint64_t index, int irq);
    157. 

  157. 

  158. void arm_gic_set_router_cpu(rt_uint64_t index, int irq, rt_uint64_t aff);
    159. 

  159. void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask);
    160. 

  160. rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq);
    161. 

  161. 

  162. void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority);
    163. 

  163. rt_uint64_t arm_gic_get_priority(rt_uint64_t index, int irq);
    164. 

  164. 

  165. void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority);
    166. 

  166. rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index);
    167. 

  167. 

  168. void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point);
    169. 

  169. rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
    170. 

  170. 

  171. rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq);
    172. 

  172. 

  173. #if defined(RT_USING_SMP) || defined(RT_USING_AMP)
    174. 

  174. void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint32_t cpu_masks[], rt_uint64_t routing_mode);
    175. 

  175. #endif
    176. 

  176. 

  177. rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index);
    178. 

  178. 

  179. rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index);
    180. 

  180. 

  181. void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group);
    182. 

  182. rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq);
    183. 

  183. 

  184. int arm_gic_redist_address_set(rt_uint64_t index, rt_uint64_t redist_addr, int cpu_id);
    185. 

  185. int arm_gic_cpu_interface_address_set(rt_uint64_t index, rt_uint64_t interface_addr, int cpu_id);
    186. 

  186. 

  187. int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start);
    188. 

  188. int arm_gic_redist_init(rt_uint64_t index, rt_uint64_t redist_base);
    189. 

  189. int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base);
    190. 

  190. 

  191. rt_uint64_t *arm_gic_get_gic_table_addr(void);
    192. 

  192. void arm_gic_dump_type(rt_uint64_t index);
    193. 

  193. void arm_gic_dump(rt_uint64_t index);
    194. 

  194. 

  195. #endif /* defined(BSP_USING_GIC) && defined(BSP_USING_GICV3) */
    196. 

  196. 

  197. #endif
    198. 

  198.