drv_sdio.c 23 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-06-22 tyx first
  9. * 2018-12-12 balanceTWK change to new framework
  10. */
  11. #include "board.h"
  12. #include "drv_sdio.h"
  13. #include "drv_config.h"
  14. #ifdef BSP_USING_SDIO
  15. //#define DRV_DEBUG
  16. #define LOG_TAG "drv.sdio"
  17. #include <drv_log.h>
  18. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4)
  19. #define SDCARD_INSTANCE SDIO
  20. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
  21. #define SDCARD_INSTANCE SDMMC1
  22. #endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) */
  23. static struct stm32_sdio_config sdio_config = SDIO_BUS_CONFIG;
  24. static struct stm32_sdio_class sdio_obj;
  25. static struct rt_mmcsd_host *host;
  26. #define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000)
  27. #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
  28. #define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
  29. struct sdio_pkg
  30. {
  31. struct rt_mmcsd_cmd *cmd;
  32. void *buff;
  33. rt_uint32_t flag;
  34. };
  35. struct rthw_sdio
  36. {
  37. struct rt_mmcsd_host *host;
  38. struct stm32_sdio_des sdio_des;
  39. struct rt_event event;
  40. struct rt_mutex mutex;
  41. struct sdio_pkg *pkg;
  42. };
  43. ALIGN(SDIO_ALIGN_LEN)
  44. static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
  45. static rt_uint32_t stm32_sdio_clk_get(struct stm32_sdio *hw_sdio)
  46. {
  47. return SDIO_CLOCK_FREQ;
  48. }
  49. /**
  50. * @brief This function get order from sdio.
  51. * @param data
  52. * @retval sdio order
  53. */
  54. static int get_order(rt_uint32_t data)
  55. {
  56. int order = 0;
  57. switch (data)
  58. {
  59. case 1:
  60. order = 0;
  61. break;
  62. case 2:
  63. order = 1;
  64. break;
  65. case 4:
  66. order = 2;
  67. break;
  68. case 8:
  69. order = 3;
  70. break;
  71. case 16:
  72. order = 4;
  73. break;
  74. case 32:
  75. order = 5;
  76. break;
  77. case 64:
  78. order = 6;
  79. break;
  80. case 128:
  81. order = 7;
  82. break;
  83. case 256:
  84. order = 8;
  85. break;
  86. case 512:
  87. order = 9;
  88. break;
  89. case 1024:
  90. order = 10;
  91. break;
  92. case 2048:
  93. order = 11;
  94. break;
  95. case 4096:
  96. order = 12;
  97. break;
  98. case 8192:
  99. order = 13;
  100. break;
  101. case 16384:
  102. order = 14;
  103. break;
  104. default :
  105. order = 0;
  106. break;
  107. }
  108. return order;
  109. }
  110. /**
  111. * @brief This function wait sdio completed.
  112. * @param sdio rthw_sdio
  113. * @retval None
  114. */
  115. static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
  116. {
  117. rt_uint32_t status;
  118. struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
  119. struct rt_mmcsd_data *data = cmd->data;
  120. struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
  121. if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
  122. rt_tick_from_millisecond(5000), &status) != RT_EOK)
  123. {
  124. LOG_E("wait completed timeout");
  125. cmd->err = -RT_ETIMEOUT;
  126. return;
  127. }
  128. if (sdio->pkg == RT_NULL)
  129. {
  130. return;
  131. }
  132. cmd->resp[0] = hw_sdio->resp1;
  133. cmd->resp[1] = hw_sdio->resp2;
  134. cmd->resp[2] = hw_sdio->resp3;
  135. cmd->resp[3] = hw_sdio->resp4;
  136. if (status & HW_SDIO_ERRORS)
  137. {
  138. if ((status & HW_SDIO_IT_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
  139. {
  140. cmd->err = RT_EOK;
  141. }
  142. else
  143. {
  144. cmd->err = -RT_ERROR;
  145. }
  146. if (status & HW_SDIO_IT_CTIMEOUT)
  147. {
  148. cmd->err = -RT_ETIMEOUT;
  149. }
  150. if (status & HW_SDIO_IT_DCRCFAIL)
  151. {
  152. data->err = -RT_ERROR;
  153. }
  154. if (status & HW_SDIO_IT_DTIMEOUT)
  155. {
  156. data->err = -RT_ETIMEOUT;
  157. }
  158. if (cmd->err == RT_EOK)
  159. {
  160. LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
  161. }
  162. else
  163. {
  164. LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
  165. status,
  166. status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "",
  167. status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "",
  168. status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "",
  169. status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "",
  170. status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "",
  171. status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "",
  172. status == 0 ? "NULL" : "",
  173. cmd->cmd_code,
  174. cmd->arg,
  175. data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
  176. data ? data->blks * data->blksize : 0,
  177. data ? data->blksize : 0
  178. );
  179. }
  180. }
  181. else
  182. {
  183. cmd->err = RT_EOK;
  184. LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
  185. }
  186. }
  187. /**
  188. * @brief This function transfer data by dma.
  189. * @param sdio rthw_sdio
  190. * @param pkg sdio package
  191. * @retval None
  192. */
  193. static void rthw_sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
  194. {
  195. struct rt_mmcsd_data *data;
  196. int size;
  197. void *buff;
  198. struct stm32_sdio *hw_sdio;
  199. if ((RT_NULL == pkg) || (RT_NULL == sdio))
  200. {
  201. LOG_E("rthw_sdio_transfer_by_dma invalid args");
  202. return;
  203. }
  204. data = pkg->cmd->data;
  205. if (RT_NULL == data)
  206. {
  207. LOG_E("rthw_sdio_transfer_by_dma invalid args");
  208. return;
  209. }
  210. buff = pkg->buff;
  211. if (RT_NULL == buff)
  212. {
  213. LOG_E("rthw_sdio_transfer_by_dma invalid args");
  214. return;
  215. }
  216. hw_sdio = sdio->sdio_des.hw_sdio;
  217. size = data->blks * data->blksize;
  218. if (data->flags & DATA_DIR_WRITE)
  219. {
  220. sdio->sdio_des.txconfig((rt_uint32_t *)buff, (rt_uint32_t *)&hw_sdio->fifo, size);
  221. hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE;
  222. }
  223. else if (data->flags & DATA_DIR_READ)
  224. {
  225. sdio->sdio_des.rxconfig((rt_uint32_t *)&hw_sdio->fifo, (rt_uint32_t *)buff, size);
  226. hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE | HW_SDIO_DPSM_ENABLE;
  227. }
  228. }
  229. /**
  230. * @brief This function send command.
  231. * @param sdio rthw_sdio
  232. * @param pkg sdio package
  233. * @retval None
  234. */
  235. static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
  236. {
  237. struct rt_mmcsd_cmd *cmd = pkg->cmd;
  238. struct rt_mmcsd_data *data = cmd->data;
  239. struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
  240. rt_uint32_t reg_cmd;
  241. /* save pkg */
  242. sdio->pkg = pkg;
  243. LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d",
  244. cmd->cmd_code,
  245. cmd->arg,
  246. resp_type(cmd) == RESP_NONE ? "NONE" : "",
  247. resp_type(cmd) == RESP_R1 ? "R1" : "",
  248. resp_type(cmd) == RESP_R1B ? "R1B" : "",
  249. resp_type(cmd) == RESP_R2 ? "R2" : "",
  250. resp_type(cmd) == RESP_R3 ? "R3" : "",
  251. resp_type(cmd) == RESP_R4 ? "R4" : "",
  252. resp_type(cmd) == RESP_R5 ? "R5" : "",
  253. resp_type(cmd) == RESP_R6 ? "R6" : "",
  254. resp_type(cmd) == RESP_R7 ? "R7" : "",
  255. data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
  256. data ? data->blks * data->blksize : 0,
  257. data ? data->blksize : 0
  258. );
  259. /* config cmd reg */
  260. reg_cmd = cmd->cmd_code | HW_SDIO_CPSM_ENABLE;
  261. if (resp_type(cmd) == RESP_NONE)
  262. reg_cmd |= HW_SDIO_RESPONSE_NO;
  263. else if (resp_type(cmd) == RESP_R2)
  264. reg_cmd |= HW_SDIO_RESPONSE_LONG;
  265. else
  266. reg_cmd |= HW_SDIO_RESPONSE_SHORT;
  267. /* config data reg */
  268. if (data != RT_NULL)
  269. {
  270. rt_uint32_t dir = 0;
  271. rt_uint32_t size = data->blks * data->blksize;
  272. int order;
  273. hw_sdio->dctrl = 0;
  274. hw_sdio->dtimer = HW_SDIO_DATATIMEOUT;
  275. hw_sdio->dlen = size;
  276. order = get_order(data->blksize);
  277. dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0;
  278. hw_sdio->dctrl = HW_SDIO_IO_ENABLE | (order << 4) | dir;
  279. }
  280. /* transfer config */
  281. if (data != RT_NULL)
  282. {
  283. rthw_sdio_transfer_by_dma(sdio, pkg);
  284. }
  285. /* open irq */
  286. hw_sdio->mask |= HW_SDIO_IT_CMDSENT | HW_SDIO_IT_CMDREND | HW_SDIO_ERRORS;
  287. if (data != RT_NULL)
  288. {
  289. hw_sdio->mask |= HW_SDIO_IT_DATAEND;
  290. }
  291. /* send cmd */
  292. hw_sdio->arg = cmd->arg;
  293. hw_sdio->cmd = reg_cmd;
  294. /* wait completed */
  295. rthw_sdio_wait_completed(sdio);
  296. /* Waiting for data to be sent to completion */
  297. if (data != RT_NULL)
  298. {
  299. volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
  300. while (count && (hw_sdio->sta & (HW_SDIO_IT_TXACT | HW_SDIO_IT_RXACT)))
  301. {
  302. count--;
  303. }
  304. if ((count == 0) || (hw_sdio->sta & HW_SDIO_ERRORS))
  305. {
  306. cmd->err = -RT_ERROR;
  307. }
  308. }
  309. /* close irq, keep sdio irq */
  310. hw_sdio->mask = hw_sdio->mask & HW_SDIO_IT_SDIOIT ? HW_SDIO_IT_SDIOIT : 0x00;
  311. /* clear pkg */
  312. sdio->pkg = RT_NULL;
  313. }
  314. /**
  315. * @brief This function send sdio request.
  316. * @param sdio rthw_sdio
  317. * @param req request
  318. * @retval None
  319. */
  320. static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  321. {
  322. struct sdio_pkg pkg;
  323. struct rthw_sdio *sdio = host->private_data;
  324. struct rt_mmcsd_data *data;
  325. RTHW_SDIO_LOCK(sdio);
  326. if (req->cmd != RT_NULL)
  327. {
  328. memset(&pkg, 0, sizeof(pkg));
  329. data = req->cmd->data;
  330. pkg.cmd = req->cmd;
  331. if (data != RT_NULL)
  332. {
  333. rt_uint32_t size = data->blks * data->blksize;
  334. RT_ASSERT(size <= SDIO_BUFF_SIZE);
  335. pkg.buff = data->buf;
  336. if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
  337. {
  338. pkg.buff = cache_buf;
  339. if (data->flags & DATA_DIR_WRITE)
  340. {
  341. memcpy(cache_buf, data->buf, size);
  342. }
  343. }
  344. }
  345. rthw_sdio_send_command(sdio, &pkg);
  346. if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
  347. {
  348. memcpy(data->buf, cache_buf, data->blksize * data->blks);
  349. }
  350. }
  351. if (req->stop != RT_NULL)
  352. {
  353. memset(&pkg, 0, sizeof(pkg));
  354. pkg.cmd = req->stop;
  355. rthw_sdio_send_command(sdio, &pkg);
  356. }
  357. RTHW_SDIO_UNLOCK(sdio);
  358. mmcsd_req_complete(sdio->host);
  359. }
  360. /**
  361. * @brief This function config sdio.
  362. * @param host rt_mmcsd_host
  363. * @param io_cfg rt_mmcsd_io_cfg
  364. * @retval None
  365. */
  366. static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
  367. {
  368. rt_uint32_t clkcr, div, clk_src;
  369. rt_uint32_t clk = io_cfg->clock;
  370. struct rthw_sdio *sdio = host->private_data;
  371. struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
  372. clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
  373. if (clk_src < 400 * 1000)
  374. {
  375. LOG_E("The clock rate is too low! rata:%d", clk_src);
  376. return;
  377. }
  378. if (clk > host->freq_max) clk = host->freq_max;
  379. if (clk > clk_src)
  380. {
  381. LOG_W("Setting rate is greater than clock source rate.");
  382. clk = clk_src;
  383. }
  384. LOG_D("clk:%d width:%s%s%s power:%s%s%s",
  385. clk,
  386. io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
  387. io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
  388. io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
  389. io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
  390. io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
  391. io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
  392. );
  393. RTHW_SDIO_LOCK(sdio);
  394. div = clk_src / clk;
  395. if ((clk == 0) || (div == 0))
  396. {
  397. clkcr = 0;
  398. }
  399. else
  400. {
  401. if (div < 2)
  402. {
  403. div = 2;
  404. }
  405. else if (div > 0xFF)
  406. {
  407. div = 0xFF;
  408. }
  409. div -= 2;
  410. clkcr = div | HW_SDIO_CLK_ENABLE;
  411. }
  412. if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
  413. {
  414. clkcr |= HW_SDIO_BUSWIDE_8B;
  415. }
  416. else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
  417. {
  418. clkcr |= HW_SDIO_BUSWIDE_4B;
  419. }
  420. else
  421. {
  422. clkcr |= HW_SDIO_BUSWIDE_1B;
  423. }
  424. hw_sdio->clkcr = clkcr;
  425. switch (io_cfg->power_mode)
  426. {
  427. case MMCSD_POWER_OFF:
  428. hw_sdio->power = HW_SDIO_POWER_OFF;
  429. break;
  430. case MMCSD_POWER_UP:
  431. hw_sdio->power = HW_SDIO_POWER_UP;
  432. break;
  433. case MMCSD_POWER_ON:
  434. hw_sdio->power = HW_SDIO_POWER_ON;
  435. break;
  436. default:
  437. LOG_W("unknown power_mode %d", io_cfg->power_mode);
  438. break;
  439. }
  440. RTHW_SDIO_UNLOCK(sdio);
  441. }
  442. /**
  443. * @brief This function update sdio interrupt.
  444. * @param host rt_mmcsd_host
  445. * @param enable
  446. * @retval None
  447. */
  448. void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
  449. {
  450. struct rthw_sdio *sdio = host->private_data;
  451. struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
  452. if (enable)
  453. {
  454. LOG_D("enable sdio irq");
  455. hw_sdio->mask |= HW_SDIO_IT_SDIOIT;
  456. }
  457. else
  458. {
  459. LOG_D("disable sdio irq");
  460. hw_sdio->mask &= ~HW_SDIO_IT_SDIOIT;
  461. }
  462. }
  463. /**
  464. * @brief This function delect sdcard.
  465. * @param host rt_mmcsd_host
  466. * @retval 0x01
  467. */
  468. static rt_int32_t rthw_sd_delect(struct rt_mmcsd_host *host)
  469. {
  470. LOG_D("try to detect device");
  471. return 0x01;
  472. }
  473. /**
  474. * @brief This function interrupt process function.
  475. * @param host rt_mmcsd_host
  476. * @retval None
  477. */
  478. void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
  479. {
  480. int complete = 0;
  481. struct rthw_sdio *sdio = host->private_data;
  482. struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
  483. rt_uint32_t intstatus = hw_sdio->sta;
  484. if (intstatus & HW_SDIO_ERRORS)
  485. {
  486. hw_sdio->icr = HW_SDIO_ERRORS;
  487. complete = 1;
  488. }
  489. else
  490. {
  491. if (intstatus & HW_SDIO_IT_CMDREND)
  492. {
  493. hw_sdio->icr = HW_SDIO_IT_CMDREND;
  494. if (sdio->pkg != RT_NULL)
  495. {
  496. if (!sdio->pkg->cmd->data)
  497. {
  498. complete = 1;
  499. }
  500. else if ((sdio->pkg->cmd->data->flags & DATA_DIR_WRITE))
  501. {
  502. hw_sdio->dctrl |= HW_SDIO_DPSM_ENABLE;
  503. }
  504. }
  505. }
  506. if (intstatus & HW_SDIO_IT_CMDSENT)
  507. {
  508. hw_sdio->icr = HW_SDIO_IT_CMDSENT;
  509. if (resp_type(sdio->pkg->cmd) == RESP_NONE)
  510. {
  511. complete = 1;
  512. }
  513. }
  514. if (intstatus & HW_SDIO_IT_DATAEND)
  515. {
  516. hw_sdio->icr = HW_SDIO_IT_DATAEND;
  517. complete = 1;
  518. }
  519. }
  520. if ((intstatus & HW_SDIO_IT_SDIOIT) && (hw_sdio->mask & HW_SDIO_IT_SDIOIT))
  521. {
  522. hw_sdio->icr = HW_SDIO_IT_SDIOIT;
  523. sdio_irq_wakeup(host);
  524. }
  525. if (complete)
  526. {
  527. hw_sdio->mask &= ~HW_SDIO_ERRORS;
  528. rt_event_send(&sdio->event, intstatus);
  529. }
  530. }
  531. static const struct rt_mmcsd_host_ops ops =
  532. {
  533. rthw_sdio_request,
  534. rthw_sdio_iocfg,
  535. rthw_sd_delect,
  536. rthw_sdio_irq_update,
  537. };
  538. /**
  539. * @brief This function create mmcsd host.
  540. * @param sdio_des stm32_sdio_des
  541. * @retval rt_mmcsd_host
  542. */
  543. struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
  544. {
  545. struct rt_mmcsd_host *host;
  546. struct rthw_sdio *sdio = RT_NULL;
  547. if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
  548. {
  549. LOG_E("L:%d F:%s %s %s %s",
  550. (sdio_des == RT_NULL ? "sdio_des is NULL" : ""),
  551. (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""),
  552. (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")
  553. );
  554. return RT_NULL;
  555. }
  556. sdio = rt_malloc(sizeof(struct rthw_sdio));
  557. if (sdio == RT_NULL)
  558. {
  559. LOG_E("L:%d F:%s malloc rthw_sdio fail");
  560. return RT_NULL;
  561. }
  562. rt_memset(sdio, 0, sizeof(struct rthw_sdio));
  563. host = mmcsd_alloc_host();
  564. if (host == RT_NULL)
  565. {
  566. LOG_E("L:%d F:%s mmcsd alloc host fail");
  567. rt_free(sdio);
  568. return RT_NULL;
  569. }
  570. rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
  571. sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? (struct stm32_sdio *)SDIO_BASE_ADDRESS : sdio_des->hw_sdio);
  572. sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? stm32_sdio_clk_get : sdio_des->clk_get);
  573. rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
  574. rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
  575. /* set host defautl attributes */
  576. host->ops = &ops;
  577. host->freq_min = 400 * 1000;
  578. host->freq_max = SDIO_MAX_FREQ;
  579. host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
  580. #ifndef SDIO_USING_1_BIT
  581. host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
  582. #else
  583. host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
  584. #endif
  585. host->max_seg_size = SDIO_BUFF_SIZE;
  586. host->max_dma_segs = 1;
  587. host->max_blk_size = 512;
  588. host->max_blk_count = 512;
  589. /* link up host and sdio */
  590. sdio->host = host;
  591. host->private_data = sdio;
  592. rthw_sdio_irq_update(host, 1);
  593. /* ready to change */
  594. mmcsd_change(host);
  595. return host;
  596. }
  597. /**
  598. * @brief This function configures the DMATX.
  599. * @param BufferSRC: pointer to the source buffer
  600. * @param BufferSize: buffer size
  601. * @retval None
  602. */
  603. void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
  604. {
  605. #if defined(SOC_SERIES_STM32F1)
  606. static uint32_t size = 0;
  607. size += BufferSize * 4;
  608. sdio_obj.cfg = &sdio_config;
  609. sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance;
  610. sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
  611. sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
  612. sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
  613. sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
  614. sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  615. sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
  616. /* DMA_PFCTRL */
  617. HAL_DMA_DeInit(&sdio_obj.dma.handle_tx);
  618. HAL_DMA_Init(&sdio_obj.dma.handle_tx);
  619. HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize);
  620. #else
  621. static uint32_t size = 0;
  622. size += BufferSize * 4;
  623. sdio_obj.cfg = &sdio_config;
  624. sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance;
  625. sdio_obj.dma.handle_tx.Init.Channel = sdio_config.dma_tx.channel;
  626. sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
  627. sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  628. sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
  629. sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
  630. sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
  631. sdio_obj.dma.handle_tx.Init.Mode = DMA_PFCTRL;
  632. sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
  633. sdio_obj.dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
  634. sdio_obj.dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
  635. sdio_obj.dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
  636. sdio_obj.dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
  637. /* DMA_PFCTRL */
  638. HAL_DMA_DeInit(&sdio_obj.dma.handle_tx);
  639. HAL_DMA_Init(&sdio_obj.dma.handle_tx);
  640. HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize);
  641. #endif
  642. }
  643. /**
  644. * @brief This function configures the DMARX.
  645. * @param BufferDST: pointer to the destination buffer
  646. * @param BufferSize: buffer size
  647. * @retval None
  648. */
  649. void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
  650. {
  651. #if defined(SOC_SERIES_STM32F1)
  652. sdio_obj.cfg = &sdio_config;
  653. sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance;
  654. sdio_obj.dma.handle_tx.Init.Direction = DMA_PERIPH_TO_MEMORY;
  655. sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
  656. sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
  657. sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
  658. sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  659. sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
  660. HAL_DMA_DeInit(&sdio_obj.dma.handle_tx);
  661. HAL_DMA_Init(&sdio_obj.dma.handle_tx);
  662. HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize);
  663. #else
  664. sdio_obj.cfg = &sdio_config;
  665. sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance;
  666. sdio_obj.dma.handle_tx.Init.Channel = sdio_config.dma_tx.channel;
  667. sdio_obj.dma.handle_tx.Init.Direction = DMA_PERIPH_TO_MEMORY;
  668. sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  669. sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
  670. sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
  671. sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
  672. sdio_obj.dma.handle_tx.Init.Mode = DMA_PFCTRL;
  673. sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
  674. sdio_obj.dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
  675. sdio_obj.dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
  676. sdio_obj.dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
  677. sdio_obj.dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
  678. HAL_DMA_DeInit(&sdio_obj.dma.handle_tx);
  679. HAL_DMA_Init(&sdio_obj.dma.handle_tx);
  680. HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize);
  681. #endif
  682. }
  683. /**
  684. * @brief This function get stm32 sdio clock.
  685. * @param hw_sdio: stm32_sdio
  686. * @retval PCLK2Freq
  687. */
  688. static rt_uint32_t stm32_sdio_clock_get(struct stm32_sdio *hw_sdio)
  689. {
  690. return HAL_RCC_GetPCLK2Freq();
  691. }
  692. static rt_err_t DMA_TxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size)
  693. {
  694. SD_LowLevel_DMA_TxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4);
  695. return RT_EOK;
  696. }
  697. static rt_err_t DMA_RxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size)
  698. {
  699. SD_LowLevel_DMA_RxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4);
  700. return RT_EOK;
  701. }
  702. void SDIO_IRQHandler(void)
  703. {
  704. /* enter interrupt */
  705. rt_interrupt_enter();
  706. /* Process All SDIO Interrupt Sources */
  707. rthw_sdio_irq_process(host);
  708. /* leave interrupt */
  709. rt_interrupt_leave();
  710. }
  711. int rt_hw_sdio_init(void)
  712. {
  713. struct stm32_sdio_des sdio_des;
  714. SD_HandleTypeDef hsd;
  715. hsd.Instance = SDCARD_INSTANCE;
  716. {
  717. rt_uint32_t tmpreg = 0x00U;
  718. #if defined(SOC_SERIES_STM32F1)
  719. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  720. SET_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc);
  721. tmpreg = READ_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc);
  722. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
  723. SET_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc);
  724. /* Delay after an RCC peripheral clock enabling */
  725. tmpreg = READ_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc);
  726. #endif
  727. UNUSED(tmpreg); /* To avoid compiler warnings */
  728. }
  729. HAL_NVIC_SetPriority(SDIO_IRQn, 2, 0);
  730. HAL_NVIC_EnableIRQ(SDIO_IRQn);
  731. HAL_SD_MspInit(&hsd);
  732. sdio_des.clk_get = stm32_sdio_clock_get;
  733. sdio_des.hw_sdio = (struct stm32_sdio *)SDCARD_INSTANCE;
  734. sdio_des.rxconfig = DMA_RxConfig;
  735. sdio_des.txconfig = DMA_TxConfig;
  736. host = sdio_host_create(&sdio_des);
  737. if (host == RT_NULL)
  738. {
  739. LOG_E("host create fail");
  740. return -1;
  741. }
  742. return 0;
  743. }
  744. INIT_DEVICE_EXPORT(rt_hw_sdio_init);
  745. #endif