board.c 21 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2009-01-05 Bernard first implementation
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "board.h"
  13. #include "pin_mux.h"
  14. #include "fsl_iomuxc.h"
  15. #include "fsl_gpio.h"
  16. #ifdef BSP_USING_DMA
  17. #include "fsl_dmamux.h"
  18. #include "fsl_edma.h"
  19. #endif
  20. #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
  21. 4 bits for subpriority */
  22. #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
  23. 3 bits for subpriority */
  24. #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
  25. 2 bits for subpriority */
  26. #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
  27. 1 bits for subpriority */
  28. #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
  29. 0 bits for subpriority */
  30. /* MPU configuration. */
  31. static void BOARD_ConfigMPU(void)
  32. {
  33. /* Disable I cache and D cache */
  34. SCB_DisableICache();
  35. SCB_DisableDCache();
  36. /* Disable MPU */
  37. ARM_MPU_Disable();
  38. /* Region 0 setting */
  39. MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
  40. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  41. /* Region 1 setting */
  42. MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
  43. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
  44. /* Region 2 setting */
  45. // spi flash: normal type, cacheable, no bufferable, no shareable
  46. MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
  47. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  48. /* Region 3 setting */
  49. MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
  50. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
  51. /* Region 4 setting */
  52. MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
  53. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
  54. /* Region 5 setting */
  55. MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
  56. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
  57. /* Region 6 setting */
  58. MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
  59. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
  60. #if defined(BSP_USING_SDRAM)
  61. /* Region 7 setting */
  62. MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
  63. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
  64. /* Region 8 setting */
  65. MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
  66. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
  67. #endif
  68. /* Enable MPU */
  69. ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
  70. /* Enable I cache and D cache */
  71. SCB_EnableDCache();
  72. SCB_EnableICache();
  73. }
  74. /* This is the timer interrupt service routine. */
  75. void SysTick_Handler(void)
  76. {
  77. /* enter interrupt */
  78. rt_interrupt_enter();
  79. rt_tick_increase();
  80. /* leave interrupt */
  81. rt_interrupt_leave();
  82. }
  83. #ifdef BSP_USING_DMA
  84. void imxrt_dma_init(void)
  85. {
  86. edma_config_t config;
  87. DMAMUX_Init(DMAMUX);
  88. EDMA_GetDefaultConfig(&config);
  89. EDMA_Init(DMA0, &config);
  90. }
  91. #endif
  92. #ifdef BSP_USING_LPUART
  93. void imxrt_uart_pins_init(void)
  94. {
  95. #ifdef BSP_USING_LPUART1
  96. IOMUXC_SetPinMux(
  97. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
  98. 0U); /* Software Input On Field: Input Path is determined by functionality */
  99. IOMUXC_SetPinMux(
  100. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
  101. 0U); /* Software Input On Field: Input Path is determined by functionality */
  102. IOMUXC_SetPinConfig(
  103. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
  104. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  105. Drive Strength Field: R0/6
  106. Speed Field: medium(100MHz)
  107. Open Drain Enable Field: Open Drain Disabled
  108. Pull / Keep Enable Field: Pull/Keeper Enabled
  109. Pull / Keep Select Field: Keeper
  110. Pull Up / Down Config. Field: 100K Ohm Pull Down
  111. Hyst. Enable Field: Hysteresis Disabled */
  112. IOMUXC_SetPinConfig(
  113. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
  114. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  115. Drive Strength Field: R0/6
  116. Speed Field: medium(100MHz)
  117. Open Drain Enable Field: Open Drain Disabled
  118. Pull / Keep Enable Field: Pull/Keeper Enabled
  119. Pull / Keep Select Field: Keeper
  120. Pull Up / Down Config. Field: 100K Ohm Pull Down
  121. Hyst. Enable Field: Hysteresis Disabled */
  122. #endif
  123. #ifdef BSP_USING_LPUART2
  124. IOMUXC_SetPinMux(
  125. IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
  126. 0U);
  127. IOMUXC_SetPinMux(
  128. IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
  129. 0U);
  130. IOMUXC_SetPinConfig(
  131. IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
  132. 0x10B0u);
  133. IOMUXC_SetPinConfig(
  134. IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
  135. 0x10B0u);
  136. #endif
  137. #ifdef BSP_USING_LPUART3
  138. IOMUXC_SetPinMux(
  139. IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
  140. 0U);
  141. IOMUXC_SetPinMux(
  142. IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
  143. 0U);
  144. IOMUXC_SetPinConfig(
  145. IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
  146. 0x10B0u);
  147. IOMUXC_SetPinConfig(
  148. IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
  149. 0x10B0u);
  150. #endif
  151. #ifdef BSP_USING_LPUART4
  152. IOMUXC_SetPinMux(
  153. IOMUXC_GPIO_B1_00_LPUART4_TX,
  154. 0U);
  155. IOMUXC_SetPinMux(
  156. IOMUXC_GPIO_B1_01_LPUART4_RX,
  157. 0U);
  158. IOMUXC_SetPinConfig(
  159. IOMUXC_GPIO_B1_00_LPUART4_TX,
  160. 0x10B0u);
  161. IOMUXC_SetPinConfig(
  162. IOMUXC_GPIO_B1_01_LPUART4_RX,
  163. 0x10B0u);
  164. #endif
  165. #ifdef BSP_USING_LPUART5
  166. IOMUXC_SetPinMux(
  167. IOMUXC_GPIO_B1_12_LPUART5_TX,
  168. 0U);
  169. IOMUXC_SetPinMux(
  170. IOMUXC_GPIO_B1_13_LPUART5_RX,
  171. 0U);
  172. IOMUXC_SetPinConfig(
  173. IOMUXC_GPIO_B1_12_LPUART5_TX,
  174. 0x10B0u);
  175. IOMUXC_SetPinConfig(
  176. IOMUXC_GPIO_B1_13_LPUART5_RX,
  177. 0x10B0u);
  178. #endif
  179. #ifdef BSP_USING_LPUART6
  180. IOMUXC_SetPinMux(
  181. IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
  182. 0U);
  183. IOMUXC_SetPinMux(
  184. IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
  185. 0U);
  186. IOMUXC_SetPinConfig(
  187. IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
  188. 0x10B0u);
  189. IOMUXC_SetPinConfig(
  190. IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
  191. 0x10B0u);
  192. #endif
  193. #ifdef BSP_USING_LPUART7
  194. IOMUXC_SetPinMux(
  195. IOMUXC_GPIO_EMC_31_LPUART7_TX,
  196. 0U);
  197. IOMUXC_SetPinMux(
  198. IOMUXC_GPIO_EMC_32_LPUART7_RX,
  199. 0U);
  200. IOMUXC_SetPinConfig(
  201. IOMUXC_GPIO_EMC_31_LPUART7_TX,
  202. 0x10B0u);
  203. IOMUXC_SetPinConfig(
  204. IOMUXC_GPIO_EMC_32_LPUART7_RX,
  205. 0x10B0u);
  206. #endif
  207. #ifdef BSP_USING_LPUART8
  208. IOMUXC_SetPinMux(
  209. IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
  210. 0U);
  211. IOMUXC_SetPinMux(
  212. IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
  213. 0U);
  214. IOMUXC_SetPinConfig(
  215. IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
  216. 0x10B0u);
  217. IOMUXC_SetPinConfig(
  218. IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
  219. 0x10B0u);
  220. #endif
  221. }
  222. #endif /* BSP_USING_LPUART */
  223. #ifdef BSP_USING_ETH
  224. void imxrt_enet_pins_init(void)
  225. {
  226. CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
  227. IOMUXC_SetPinMux(
  228. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
  229. 0U); /* Software Input On Field: Input Path is determined by functionality */
  230. IOMUXC_SetPinMux(
  231. IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
  232. 0U);
  233. IOMUXC_SetPinMux(
  234. IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
  235. 0U); /* Software Input On Field: Input Path is determined by functionality */
  236. IOMUXC_SetPinMux(
  237. IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
  238. 0U); /* Software Input On Field: Input Path is determined by functionality */
  239. IOMUXC_SetPinMux(
  240. IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
  241. 0U); /* Software Input On Field: Input Path is determined by functionality */
  242. IOMUXC_SetPinMux(
  243. IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
  244. 0U); /* Software Input On Field: Input Path is determined by functionality */
  245. IOMUXC_SetPinMux(
  246. IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
  247. 0U); /* Software Input On Field: Input Path is determined by functionality */
  248. IOMUXC_SetPinMux(
  249. IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
  250. 0U); /* Software Input On Field: Input Path is determined by functionality */
  251. IOMUXC_SetPinMux(
  252. IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
  253. 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
  254. IOMUXC_SetPinMux(
  255. IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
  256. 0U); /* Software Input On Field: Input Path is determined by functionality */
  257. IOMUXC_SetPinMux(
  258. IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
  259. 0U); /* Software Input On Field: Input Path is determined by functionality */
  260. IOMUXC_SetPinMux(
  261. IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
  262. 0U); /* Software Input On Field: Input Path is determined by functionality */
  263. IOMUXC_SetPinConfig(
  264. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
  265. 0xB0A9u); /* Slew Rate Field: Fast Slew Rate
  266. Drive Strength Field: R0/5
  267. Speed Field: medium(100MHz)
  268. Open Drain Enable Field: Open Drain Disabled
  269. Pull / Keep Enable Field: Pull/Keeper Enabled
  270. Pull / Keep Select Field: Pull
  271. Pull Up / Down Config. Field: 100K Ohm Pull Up
  272. Hyst. Enable Field: Hysteresis Disabled */
  273. IOMUXC_SetPinConfig(
  274. IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
  275. 0xB0A9u); /* Slew Rate Field: Fast Slew Rate
  276. Drive Strength Field: R0/5
  277. Speed Field: medium(100MHz)
  278. Open Drain Enable Field: Open Drain Disabled
  279. Pull / Keep Enable Field: Pull/Keeper Enabled
  280. Pull / Keep Select Field: Pull
  281. Pull Up / Down Config. Field: 100K Ohm Pull Up
  282. Hyst. Enable Field: Hysteresis Disabled */
  283. IOMUXC_SetPinConfig(
  284. IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
  285. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  286. Drive Strength Field: R0/5
  287. Speed Field: max(200MHz)
  288. Open Drain Enable Field: Open Drain Disabled
  289. Pull / Keep Enable Field: Pull/Keeper Enabled
  290. Pull / Keep Select Field: Pull
  291. Pull Up / Down Config. Field: 100K Ohm Pull Up
  292. Hyst. Enable Field: Hysteresis Disabled */
  293. IOMUXC_SetPinConfig(
  294. IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
  295. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  296. Drive Strength Field: R0/5
  297. Speed Field: max(200MHz)
  298. Open Drain Enable Field: Open Drain Disabled
  299. Pull / Keep Enable Field: Pull/Keeper Enabled
  300. Pull / Keep Select Field: Pull
  301. Pull Up / Down Config. Field: 100K Ohm Pull Up
  302. Hyst. Enable Field: Hysteresis Disabled */
  303. IOMUXC_SetPinConfig(
  304. IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
  305. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  306. Drive Strength Field: R0/5
  307. Speed Field: max(200MHz)
  308. Open Drain Enable Field: Open Drain Disabled
  309. Pull / Keep Enable Field: Pull/Keeper Enabled
  310. Pull / Keep Select Field: Pull
  311. Pull Up / Down Config. Field: 100K Ohm Pull Up
  312. Hyst. Enable Field: Hysteresis Disabled */
  313. IOMUXC_SetPinConfig(
  314. IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
  315. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  316. Drive Strength Field: R0/5
  317. Speed Field: max(200MHz)
  318. Open Drain Enable Field: Open Drain Disabled
  319. Pull / Keep Enable Field: Pull/Keeper Enabled
  320. Pull / Keep Select Field: Pull
  321. Pull Up / Down Config. Field: 100K Ohm Pull Up
  322. Hyst. Enable Field: Hysteresis Disabled */
  323. IOMUXC_SetPinConfig(
  324. IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
  325. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  326. Drive Strength Field: R0/5
  327. Speed Field: max(200MHz)
  328. Open Drain Enable Field: Open Drain Disabled
  329. Pull / Keep Enable Field: Pull/Keeper Enabled
  330. Pull / Keep Select Field: Pull
  331. Pull Up / Down Config. Field: 100K Ohm Pull Up
  332. Hyst. Enable Field: Hysteresis Disabled */
  333. IOMUXC_SetPinConfig(
  334. IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
  335. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  336. Drive Strength Field: R0/5
  337. Speed Field: max(200MHz)
  338. Open Drain Enable Field: Open Drain Disabled
  339. Pull / Keep Enable Field: Pull/Keeper Enabled
  340. Pull / Keep Select Field: Pull
  341. Pull Up / Down Config. Field: 100K Ohm Pull Up
  342. Hyst. Enable Field: Hysteresis Disabled */
  343. IOMUXC_SetPinConfig(
  344. IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
  345. 0x31u); /* Slew Rate Field: Fast Slew Rate
  346. Drive Strength Field: R0/6
  347. Speed Field: low(50MHz)
  348. Open Drain Enable Field: Open Drain Disabled
  349. Pull / Keep Enable Field: Pull/Keeper Disabled
  350. Pull / Keep Select Field: Keeper
  351. Pull Up / Down Config. Field: 100K Ohm Pull Down
  352. Hyst. Enable Field: Hysteresis Disabled */
  353. IOMUXC_SetPinConfig(
  354. IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
  355. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  356. Drive Strength Field: R0/5
  357. Speed Field: max(200MHz)
  358. Open Drain Enable Field: Open Drain Disabled
  359. Pull / Keep Enable Field: Pull/Keeper Enabled
  360. Pull / Keep Select Field: Pull
  361. Pull Up / Down Config. Field: 100K Ohm Pull Up
  362. Hyst. Enable Field: Hysteresis Disabled */
  363. IOMUXC_SetPinConfig(
  364. IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
  365. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  366. Drive Strength Field: R0/5
  367. Speed Field: max(200MHz)
  368. Open Drain Enable Field: Open Drain Disabled
  369. Pull / Keep Enable Field: Pull/Keeper Enabled
  370. Pull / Keep Select Field: Pull
  371. Pull Up / Down Config. Field: 100K Ohm Pull Up
  372. Hyst. Enable Field: Hysteresis Disabled */
  373. IOMUXC_SetPinConfig(
  374. IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
  375. 0xB829u); /* Slew Rate Field: Fast Slew Rate
  376. Drive Strength Field: R0/5
  377. Speed Field: low(50MHz)
  378. Open Drain Enable Field: Open Drain Enabled
  379. Pull / Keep Enable Field: Pull/Keeper Enabled
  380. Pull / Keep Select Field: Pull
  381. Pull Up / Down Config. Field: 100K Ohm Pull Up
  382. Hyst. Enable Field: Hysteresis Disabled */
  383. }
  384. void imxrt_enet_phy_reset_by_gpio(void)
  385. {
  386. gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
  387. GPIO_PinInit(GPIO1, 9, &gpio_config);
  388. GPIO_PinInit(GPIO1, 10, &gpio_config);
  389. /* pull up the ENET_INT before RESET. */
  390. GPIO_WritePinOutput(GPIO1, 10, 1);
  391. GPIO_WritePinOutput(GPIO1, 9, 0);
  392. rt_thread_delay(100);
  393. GPIO_WritePinOutput(GPIO1, 9, 1);
  394. }
  395. #endif /* BSP_USING_ETH */
  396. /**
  397. * This function will initial rt1050 board.
  398. */
  399. void rt_hw_board_init()
  400. {
  401. BOARD_ConfigMPU();
  402. BOARD_InitPins();
  403. BOARD_BootClockRUN();
  404. NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  405. SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  406. #ifdef BSP_USING_LPUART
  407. imxrt_uart_pins_init();
  408. #endif
  409. #ifdef BSP_USING_ETH
  410. imxrt_enet_pins_init();
  411. #endif
  412. #ifdef BSP_USING_DMA
  413. imxrt_dma_init();
  414. #endif
  415. #ifdef RT_USING_HEAP
  416. rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
  417. #endif
  418. #ifdef RT_USING_COMPONENTS_INIT
  419. rt_components_board_init();
  420. #endif
  421. #ifdef RT_USING_CONSOLE
  422. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  423. #endif
  424. }