board.c 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126
  1. /*
  2. * File : board.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2009 RT-Thread Develop Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2009-01-05 Bernard first implementation
  13. */
  14. #include <stdint.h>
  15. #include <rthw.h>
  16. #include <rtthread.h>
  17. #include "board.h"
  18. #include "usart.h"
  19. /* ARM PLL configuration for RUN mode */
  20. const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U };
  21. /* SYS PLL configuration for RUN mode */
  22. const clock_sys_pll_config_t sysPllConfig = { .loopDivider = 1U };
  23. /* USB1 PLL configuration for RUN mode */
  24. const clock_usb_pll_config_t usb1PllConfig = { .loopDivider = 0U };
  25. static void BOARD_BootClockGate(void)
  26. {
  27. /* Disable all unused peripheral clock */
  28. CCM->CCGR0 = 0x00C0000FU;
  29. CCM->CCGR1 = 0x30000000U;
  30. CCM->CCGR2 = 0x003F0030U;
  31. CCM->CCGR3 = 0xF0000330U;
  32. CCM->CCGR4 = 0x0000FF3CU;
  33. CCM->CCGR5 = 0xF000330FU;
  34. CCM->CCGR6 = 0x00FC0300U;
  35. }
  36. static void BOARD_BootClockRUN(void)
  37. {
  38. /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */
  39. CLOCK_SetXtalFreq(24000000U);
  40. CLOCK_SetRtcXtalFreq(32768U);
  41. CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */
  42. CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
  43. /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */
  44. DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
  45. CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
  46. #ifndef SKIP_SYSCLK_INIT
  47. CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
  48. #endif
  49. #ifndef SKIP_USB_PLL_INIT
  50. CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
  51. #endif
  52. CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */
  53. CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
  54. CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */
  55. CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */
  56. CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
  57. /* Disable unused clock */
  58. BOARD_BootClockGate();
  59. /* Power down all unused PLL */
  60. CLOCK_DeinitAudioPll();
  61. CLOCK_DeinitVideoPll();
  62. CLOCK_DeinitEnetPll();
  63. CLOCK_DeinitUsb2Pll();
  64. /* Configure UART divider to default */
  65. CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
  66. CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
  67. /* Update core clock */
  68. SystemCoreClockUpdate();
  69. }
  70. /**
  71. * This is the timer interrupt service routine.
  72. *
  73. */
  74. void SysTick_Handler(void)
  75. {
  76. /* enter interrupt */
  77. rt_interrupt_enter();
  78. rt_tick_increase();
  79. /* leave interrupt */
  80. rt_interrupt_leave();
  81. }
  82. /**
  83. * This function will initial LPC8XX board.
  84. */
  85. void rt_hw_board_init()
  86. {
  87. BOARD_BootClockRUN();
  88. SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  89. extern int imxrt_hw_usart_init(void);
  90. imxrt_hw_usart_init();
  91. #ifdef RT_USING_COMPONENTS_INIT
  92. rt_components_board_init();
  93. #endif
  94. #ifdef RT_USING_CONSOLE
  95. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  96. #endif
  97. #ifdef RT_USING_HEAP
  98. rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
  99. #endif
  100. }
  101. /*@}*/