i2c-bit-ops.c 9.8 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2012-04-25 weety first version
  9. */
  10. #include <rtdevice.h>
  11. #ifdef RT_I2C_BIT_DEBUG
  12. #define bit_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
  13. #else
  14. #define bit_dbg(fmt, ...)
  15. #endif
  16. #define SET_SDA(ops, val) ops->set_sda(ops->data, val)
  17. #define SET_SCL(ops, val) ops->set_scl(ops->data, val)
  18. #define GET_SDA(ops) ops->get_sda(ops->data)
  19. #define GET_SCL(ops) ops->get_scl(ops->data)
  20. rt_inline void i2c_delay(struct rt_i2c_bit_ops *ops)
  21. {
  22. ops->udelay((ops->delay_us + 1) >> 1);
  23. }
  24. rt_inline void i2c_delay2(struct rt_i2c_bit_ops *ops)
  25. {
  26. ops->udelay(ops->delay_us);
  27. }
  28. #define SDA_L(ops) SET_SDA(ops, 0)
  29. #define SDA_H(ops) SET_SDA(ops, 1)
  30. #define SCL_L(ops) SET_SCL(ops, 0)
  31. /**
  32. * release scl line, and wait scl line to high.
  33. */
  34. static rt_err_t SCL_H(struct rt_i2c_bit_ops *ops)
  35. {
  36. rt_tick_t start;
  37. SET_SCL(ops, 1);
  38. if (!ops->get_scl)
  39. goto done;
  40. start = rt_tick_get();
  41. while (!GET_SCL(ops))
  42. {
  43. if ((rt_tick_get() - start) > ops->timeout)
  44. return -RT_ETIMEOUT;
  45. rt_thread_delay((ops->timeout + 1) >> 1);
  46. }
  47. #ifdef RT_I2C_BIT_DEBUG
  48. if (rt_tick_get() != start)
  49. {
  50. bit_dbg("wait %ld tick for SCL line to go high\n",
  51. rt_tick_get() - start);
  52. }
  53. #endif
  54. done:
  55. i2c_delay(ops);
  56. return RT_EOK;
  57. }
  58. static void i2c_start(struct rt_i2c_bit_ops *ops)
  59. {
  60. #ifdef RT_I2C_BIT_DEBUG
  61. if (ops->get_scl && !GET_SCL(ops))
  62. {
  63. bit_dbg("I2C bus error, SCL line low\n");
  64. }
  65. if (ops->get_sda && !GET_SDA(ops))
  66. {
  67. bit_dbg("I2C bus error, SDA line low\n");
  68. }
  69. #endif
  70. SDA_L(ops);
  71. i2c_delay(ops);
  72. SCL_L(ops);
  73. }
  74. static void i2c_restart(struct rt_i2c_bit_ops *ops)
  75. {
  76. SDA_H(ops);
  77. SCL_H(ops);
  78. i2c_delay(ops);
  79. SDA_L(ops);
  80. i2c_delay(ops);
  81. SCL_L(ops);
  82. }
  83. static void i2c_stop(struct rt_i2c_bit_ops *ops)
  84. {
  85. SDA_L(ops);
  86. i2c_delay(ops);
  87. SCL_H(ops);
  88. i2c_delay(ops);
  89. SDA_H(ops);
  90. i2c_delay2(ops);
  91. }
  92. rt_inline rt_bool_t i2c_waitack(struct rt_i2c_bit_ops *ops)
  93. {
  94. rt_bool_t ack;
  95. SDA_H(ops);
  96. i2c_delay(ops);
  97. if (SCL_H(ops) < 0)
  98. {
  99. bit_dbg("wait ack timeout\n");
  100. return -RT_ETIMEOUT;
  101. }
  102. ack = !GET_SDA(ops); /* ACK : SDA pin is pulled low */
  103. bit_dbg("%s\n", ack ? "ACK" : "NACK");
  104. SCL_L(ops);
  105. return ack;
  106. }
  107. static rt_int32_t i2c_writeb(struct rt_i2c_bus_device *bus, rt_uint8_t data)
  108. {
  109. rt_int32_t i;
  110. rt_uint8_t bit;
  111. struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
  112. for (i = 7; i >= 0; i--)
  113. {
  114. SCL_L(ops);
  115. bit = (data >> i) & 1;
  116. SET_SDA(ops, bit);
  117. i2c_delay(ops);
  118. if (SCL_H(ops) < 0)
  119. {
  120. bit_dbg("i2c_writeb: 0x%02x, "
  121. "wait scl pin high timeout at bit %d\n",
  122. data, i);
  123. return -RT_ETIMEOUT;
  124. }
  125. }
  126. SCL_L(ops);
  127. i2c_delay(ops);
  128. return i2c_waitack(ops);
  129. }
  130. static rt_int32_t i2c_readb(struct rt_i2c_bus_device *bus)
  131. {
  132. rt_uint8_t i;
  133. rt_uint8_t data = 0;
  134. struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
  135. SDA_H(ops);
  136. i2c_delay(ops);
  137. for (i = 0; i < 8; i++)
  138. {
  139. data <<= 1;
  140. if (SCL_H(ops) < 0)
  141. {
  142. bit_dbg("i2c_readb: wait scl pin high "
  143. "timeout at bit %d\n", 7 - i);
  144. return -RT_ETIMEOUT;
  145. }
  146. if (GET_SDA(ops))
  147. data |= 1;
  148. SCL_L(ops);
  149. i2c_delay2(ops);
  150. }
  151. return data;
  152. }
  153. static rt_size_t i2c_send_bytes(struct rt_i2c_bus_device *bus,
  154. struct rt_i2c_msg *msg)
  155. {
  156. rt_int32_t ret;
  157. rt_size_t bytes = 0;
  158. const rt_uint8_t *ptr = msg->buf;
  159. rt_int32_t count = msg->len;
  160. rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
  161. while (count > 0)
  162. {
  163. ret = i2c_writeb(bus, *ptr);
  164. if ((ret > 0) || (ignore_nack && (ret == 0)))
  165. {
  166. count --;
  167. ptr ++;
  168. bytes ++;
  169. }
  170. else if (ret == 0)
  171. {
  172. i2c_dbg("send bytes: NACK.\n");
  173. return 0;
  174. }
  175. else
  176. {
  177. i2c_dbg("send bytes: error %d\n", ret);
  178. return ret;
  179. }
  180. }
  181. return bytes;
  182. }
  183. static rt_err_t i2c_send_ack_or_nack(struct rt_i2c_bus_device *bus, int ack)
  184. {
  185. struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
  186. if (ack)
  187. SET_SDA(ops, 0);
  188. i2c_delay(ops);
  189. if (SCL_H(ops) < 0)
  190. {
  191. bit_dbg("ACK or NACK timeout\n");
  192. return -RT_ETIMEOUT;
  193. }
  194. SCL_L(ops);
  195. return RT_EOK;
  196. }
  197. static rt_size_t i2c_recv_bytes(struct rt_i2c_bus_device *bus,
  198. struct rt_i2c_msg *msg)
  199. {
  200. rt_int32_t val;
  201. rt_int32_t bytes = 0; /* actual bytes */
  202. rt_uint8_t *ptr = msg->buf;
  203. rt_int32_t count = msg->len;
  204. const rt_uint32_t flags = msg->flags;
  205. while (count > 0)
  206. {
  207. val = i2c_readb(bus);
  208. if (val >= 0)
  209. {
  210. *ptr = val;
  211. bytes ++;
  212. }
  213. else
  214. {
  215. break;
  216. }
  217. ptr ++;
  218. count --;
  219. bit_dbg("recieve bytes: 0x%02x, %s\n",
  220. val, (flags & RT_I2C_NO_READ_ACK) ?
  221. "(No ACK/NACK)" : (count ? "ACK" : "NACK"));
  222. if (!(flags & RT_I2C_NO_READ_ACK))
  223. {
  224. val = i2c_send_ack_or_nack(bus, count);
  225. if (val < 0)
  226. return val;
  227. }
  228. }
  229. return bytes;
  230. }
  231. static rt_int32_t i2c_send_address(struct rt_i2c_bus_device *bus,
  232. rt_uint8_t addr,
  233. rt_int32_t retries)
  234. {
  235. struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
  236. rt_int32_t i;
  237. rt_err_t ret = 0;
  238. for (i = 0; i <= retries; i++)
  239. {
  240. ret = i2c_writeb(bus, addr);
  241. if (ret == 1 || i == retries)
  242. break;
  243. bit_dbg("send stop condition\n");
  244. i2c_stop(ops);
  245. i2c_delay2(ops);
  246. bit_dbg("send start condition\n");
  247. i2c_start(ops);
  248. }
  249. return ret;
  250. }
  251. static rt_err_t i2c_bit_send_address(struct rt_i2c_bus_device *bus,
  252. struct rt_i2c_msg *msg)
  253. {
  254. rt_uint16_t flags = msg->flags;
  255. rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
  256. struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
  257. rt_uint8_t addr1, addr2;
  258. rt_int32_t retries;
  259. rt_err_t ret;
  260. retries = ignore_nack ? 0 : bus->retries;
  261. if (flags & RT_I2C_ADDR_10BIT)
  262. {
  263. addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
  264. addr2 = msg->addr & 0xff;
  265. bit_dbg("addr1: %d, addr2: %d\n", addr1, addr2);
  266. ret = i2c_send_address(bus, addr1, retries);
  267. if ((ret != 1) && !ignore_nack)
  268. {
  269. bit_dbg("NACK: sending first addr\n");
  270. return -RT_EIO;
  271. }
  272. ret = i2c_writeb(bus, addr2);
  273. if ((ret != 1) && !ignore_nack)
  274. {
  275. bit_dbg("NACK: sending second addr\n");
  276. return -RT_EIO;
  277. }
  278. if (flags & RT_I2C_RD)
  279. {
  280. bit_dbg("send repeated start condition\n");
  281. i2c_restart(ops);
  282. addr1 |= 0x01;
  283. ret = i2c_send_address(bus, addr1, retries);
  284. if ((ret != 1) && !ignore_nack)
  285. {
  286. bit_dbg("NACK: sending repeated addr\n");
  287. return -RT_EIO;
  288. }
  289. }
  290. }
  291. else
  292. {
  293. /* 7-bit addr */
  294. addr1 = msg->addr << 1;
  295. if (flags & RT_I2C_RD)
  296. addr1 |= 1;
  297. ret = i2c_send_address(bus, addr1, retries);
  298. if ((ret != 1) && !ignore_nack)
  299. return -RT_EIO;
  300. }
  301. return RT_EOK;
  302. }
  303. static rt_size_t i2c_bit_xfer(struct rt_i2c_bus_device *bus,
  304. struct rt_i2c_msg msgs[],
  305. rt_uint32_t num)
  306. {
  307. struct rt_i2c_msg *msg;
  308. struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
  309. rt_int32_t i, ret;
  310. rt_uint16_t ignore_nack;
  311. bit_dbg("send start condition\n");
  312. i2c_start(ops);
  313. for (i = 0; i < num; i++)
  314. {
  315. msg = &msgs[i];
  316. ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
  317. if (!(msg->flags & RT_I2C_NO_START))
  318. {
  319. if (i)
  320. {
  321. i2c_restart(ops);
  322. }
  323. ret = i2c_bit_send_address(bus, msg);
  324. if ((ret != RT_EOK) && !ignore_nack)
  325. {
  326. bit_dbg("receive NACK from device addr 0x%02x msg %d\n",
  327. msgs[i].addr, i);
  328. goto out;
  329. }
  330. }
  331. if (msg->flags & RT_I2C_RD)
  332. {
  333. ret = i2c_recv_bytes(bus, msg);
  334. if (ret >= 1)
  335. bit_dbg("read %d byte%s\n", ret, ret == 1 ? "" : "s");
  336. if (ret < msg->len)
  337. {
  338. if (ret >= 0)
  339. ret = -RT_EIO;
  340. goto out;
  341. }
  342. }
  343. else
  344. {
  345. ret = i2c_send_bytes(bus, msg);
  346. if (ret >= 1)
  347. bit_dbg("write %d byte%s\n", ret, ret == 1 ? "" : "s");
  348. if (ret < msg->len)
  349. {
  350. if (ret >= 0)
  351. ret = -RT_ERROR;
  352. goto out;
  353. }
  354. }
  355. }
  356. ret = i;
  357. out:
  358. bit_dbg("send stop condition\n");
  359. i2c_stop(ops);
  360. return ret;
  361. }
  362. static const struct rt_i2c_bus_device_ops i2c_bit_bus_ops =
  363. {
  364. i2c_bit_xfer,
  365. RT_NULL,
  366. RT_NULL
  367. };
  368. rt_err_t rt_i2c_bit_add_bus(struct rt_i2c_bus_device *bus,
  369. const char *bus_name)
  370. {
  371. bus->ops = &i2c_bit_bus_ops;
  372. return rt_i2c_bus_device_register(bus, bus_name);
  373. }