macb.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695
  1. /*
  2. * File : macb.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006, RT-Thread Develop Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2011-03-18 weety first version
  13. */
  14. #include <rtthread.h>
  15. #include <netif/ethernetif.h>
  16. #include "lwipopts.h"
  17. #include <at91sam926x.h>
  18. #include "macb.h"
  19. #define CONFIG_RMII
  20. #define MACB_RX_BUFFER_SIZE 4096*4
  21. #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
  22. #define MACB_TX_RING_SIZE 16
  23. #define MACB_TX_TIMEOUT 1000
  24. #define MACB_AUTONEG_TIMEOUT 5000000
  25. #define MACB_LINK_TIMEOUT 500000
  26. struct macb_dma_desc {
  27. rt_uint32_t addr;
  28. rt_uint32_t ctrl;
  29. };
  30. #define RXADDR_USED 0x00000001
  31. #define RXADDR_WRAP 0x00000002
  32. #define RXBUF_FRMLEN_MASK 0x00000fff
  33. #define RXBUF_FRAME_START 0x00004000
  34. #define RXBUF_FRAME_END 0x00008000
  35. #define RXBUF_TYPEID_MATCH 0x00400000
  36. #define RXBUF_ADDR4_MATCH 0x00800000
  37. #define RXBUF_ADDR3_MATCH 0x01000000
  38. #define RXBUF_ADDR2_MATCH 0x02000000
  39. #define RXBUF_ADDR1_MATCH 0x04000000
  40. #define RXBUF_BROADCAST 0x80000000
  41. #define TXBUF_FRMLEN_MASK 0x000007ff
  42. #define TXBUF_FRAME_END 0x00008000
  43. #define TXBUF_NOCRC 0x00010000
  44. #define TXBUF_EXHAUSTED 0x08000000
  45. #define TXBUF_UNDERRUN 0x10000000
  46. #define TXBUF_MAXRETRY 0x20000000
  47. #define TXBUF_WRAP 0x40000000
  48. #define TXBUF_USED 0x80000000
  49. #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
  50. | MACB_BIT(ISR_ROVR))
  51. /* Duplex, half or full. */
  52. #define DUPLEX_HALF 0x00
  53. #define DUPLEX_FULL 0x01
  54. #define MAX_ADDR_LEN 6
  55. struct rt_macb_eth
  56. {
  57. /* inherit from ethernet device */
  58. struct eth_device parent;
  59. unsigned int regs;
  60. unsigned int rx_tail;
  61. unsigned int tx_head;
  62. unsigned int tx_tail;
  63. void *rx_buffer;
  64. void *tx_buffer;
  65. struct macb_dma_desc *rx_ring;
  66. struct macb_dma_desc *tx_ring;
  67. unsigned long rx_buffer_dma;
  68. unsigned long rx_ring_dma;
  69. unsigned long tx_ring_dma;
  70. /* interface address info. */
  71. rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
  72. unsigned short phy_addr;
  73. struct rt_semaphore mdio_bus_lock;
  74. rt_uint32_t speed;
  75. rt_uint32_t duplex;
  76. rt_uint32_t link;
  77. struct rt_timer timer;
  78. };
  79. static struct rt_macb_eth macb_device;
  80. static struct rt_semaphore sem_ack, sem_lock;
  81. static void udelay(rt_uint32_t us)
  82. {
  83. rt_uint32_t len;
  84. for (;us > 0; us --)
  85. for (len = 0; len < 10; len++ );
  86. }
  87. static void rt_macb_isr(int irq)
  88. {
  89. struct rt_macb_eth *macb = &macb_device;
  90. rt_device_t dev = &(macb->parent.parent);
  91. rt_uint32_t status, rsr, tsr;
  92. status = macb_readl(macb, ISR);
  93. while (status) {
  94. if (status & MACB_RX_INT_FLAGS) {
  95. rsr = macb_readl(macb, RSR);
  96. macb_writel(macb, RSR, rsr);
  97. /* a frame has been received */
  98. eth_device_ready(&(macb_device.parent));
  99. }
  100. if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
  101. MACB_BIT(ISR_RLE)))
  102. {
  103. tsr = macb_readl(macb, TSR);
  104. macb_writel(macb, TSR, tsr);
  105. /* One packet sent complete */
  106. rt_sem_release(&sem_ack);
  107. }
  108. /*
  109. * Link change detection isn't possible with RMII, so we'll
  110. * add that if/when we get our hands on a full-blown MII PHY.
  111. */
  112. if (status & MACB_BIT(HRESP)) {
  113. /*
  114. * TODO: Reset the hardware, and maybe move the printk
  115. * to a lower-priority context as well (work queue?)
  116. */
  117. rt_kprintf("%s: DMA bus error: HRESP not OK\n",
  118. dev->parent.name);
  119. }
  120. status = macb_readl(macb, ISR);
  121. }
  122. }
  123. static void macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value)
  124. {
  125. unsigned long netctl;
  126. unsigned long netstat;
  127. unsigned long frame;
  128. rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
  129. netctl = macb_readl(macb, NCR);
  130. netctl |= MACB_BIT(MPE);
  131. macb_writel(macb, NCR, netctl);
  132. frame = (MACB_BF(SOF, 1)
  133. | MACB_BF(RW, 1)
  134. | MACB_BF(PHYA, macb->phy_addr)
  135. | MACB_BF(REGA, reg)
  136. | MACB_BF(CODE, 2)
  137. | MACB_BF(DATA, value));
  138. macb_writel(macb, MAN, frame);
  139. do {
  140. netstat = macb_readl(macb, NSR);
  141. } while (!(netstat & MACB_BIT(IDLE)));
  142. netctl = macb_readl(macb, NCR);
  143. netctl &= ~MACB_BIT(MPE);
  144. macb_writel(macb, NCR, netctl);
  145. rt_sem_release(&macb->mdio_bus_lock);
  146. }
  147. static rt_uint16_t macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg)
  148. {
  149. unsigned long netctl;
  150. unsigned long netstat;
  151. unsigned long frame;
  152. rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
  153. netctl = macb_readl(macb, NCR);
  154. netctl |= MACB_BIT(MPE);
  155. macb_writel(macb, NCR, netctl);
  156. frame = (MACB_BF(SOF, 1)
  157. | MACB_BF(RW, 2)
  158. | MACB_BF(PHYA, macb->phy_addr)
  159. | MACB_BF(REGA, reg)
  160. | MACB_BF(CODE, 2));
  161. macb_writel(macb, MAN, frame);
  162. do {
  163. netstat = macb_readl(macb, NSR);
  164. } while (!(netstat & MACB_BIT(IDLE)));
  165. frame = macb_readl(macb, MAN);
  166. netctl = macb_readl(macb, NCR);
  167. netctl &= ~MACB_BIT(MPE);
  168. macb_writel(macb, NCR, netctl);
  169. rt_sem_release(&macb->mdio_bus_lock);
  170. return MACB_BFEXT(DATA, frame);
  171. }
  172. static void macb_phy_reset(rt_device_t dev)
  173. {
  174. int i;
  175. rt_uint16_t status, adv;
  176. struct rt_macb_eth *macb = dev->user_data;;
  177. adv = ADVERTISE_CSMA | ADVERTISE_ALL;
  178. macb_mdio_write(macb, MII_ADVERTISE, adv);
  179. rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name);
  180. macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
  181. | BMCR_ANRESTART));
  182. for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
  183. status = macb_mdio_read(macb, MII_BMSR);
  184. if (status & BMSR_ANEGCOMPLETE)
  185. break;
  186. udelay(100);
  187. }
  188. if (status & BMSR_ANEGCOMPLETE)
  189. rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name);
  190. else
  191. rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n",
  192. dev->parent.name, status);
  193. }
  194. static int macb_phy_init(rt_device_t dev)
  195. {
  196. struct rt_macb_eth *macb = dev->user_data;
  197. rt_uint32_t ncfgr;
  198. rt_uint16_t phy_id, status, adv, lpa;
  199. int media, speed, duplex;
  200. int i;
  201. /* Check if the PHY is up to snuff... */
  202. phy_id = macb_mdio_read(macb, MII_PHYSID1);
  203. if (phy_id == 0xffff) {
  204. rt_kprintf("%s: No PHY present\n", dev->parent.name);
  205. return 0;
  206. }
  207. status = macb_mdio_read(macb, MII_BMSR);
  208. if (!(status & BMSR_LSTATUS)) {
  209. /* Try to re-negotiate if we don't have link already. */
  210. macb_phy_reset(dev);
  211. for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) {
  212. status = macb_mdio_read(macb, MII_BMSR);
  213. if (status & BMSR_LSTATUS)
  214. break;
  215. udelay(100);
  216. }
  217. }
  218. if (!(status & BMSR_LSTATUS)) {
  219. rt_kprintf("%s: link down (status: 0x%04x)\n",
  220. dev->parent.name, status);
  221. return 0;
  222. } else {
  223. adv = macb_mdio_read(macb, MII_ADVERTISE);
  224. lpa = macb_mdio_read(macb, MII_LPA);
  225. media = mii_nway_result(lpa & adv);
  226. speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  227. ? 1 : 0);
  228. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  229. rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
  230. dev->parent.name,
  231. speed ? "100" : "10",
  232. duplex ? "full" : "half",
  233. lpa);
  234. ncfgr = macb_readl(macb, NCFGR);
  235. ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  236. if (speed)
  237. ncfgr |= MACB_BIT(SPD);
  238. if (duplex)
  239. ncfgr |= MACB_BIT(FD);
  240. macb_writel(macb, NCFGR, ncfgr);
  241. return 1;
  242. }
  243. }
  244. void macb_update_link(struct rt_macb_eth *macb)
  245. {
  246. rt_device_t dev = &macb->parent.parent;
  247. rt_uint32_t status, status_change = 0;
  248. rt_uint32_t link;
  249. rt_uint32_t media;
  250. rt_uint16_t adv, lpa;
  251. status = macb_mdio_read(macb, MII_BMSR);
  252. if ((status & BMSR_LSTATUS) == 0)
  253. link = 0;
  254. else
  255. link = 1;
  256. if (link != macb->link) {
  257. macb->link = link;
  258. status_change = 1;
  259. }
  260. if (status_change) {
  261. if (macb->link) {
  262. adv = macb_mdio_read(macb, MII_ADVERTISE);
  263. lpa = macb_mdio_read(macb, MII_LPA);
  264. media = mii_nway_result(lpa & adv);
  265. macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  266. ? 100 : 10);
  267. macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  268. rt_kprintf("%s: link up (%dMbps/%s-duplex)\n",
  269. dev->parent.name, macb->speed,
  270. DUPLEX_FULL == macb->duplex ? "Full":"Half");
  271. eth_device_linkchange(&macb->parent, RT_TRUE);
  272. } else {
  273. rt_kprintf("%s: link down\n", dev->parent.name);
  274. eth_device_linkchange(&macb->parent, RT_FALSE);
  275. }
  276. }
  277. }
  278. /* RT-Thread Device Interface */
  279. /* initialize the interface */
  280. static rt_err_t rt_macb_init(rt_device_t dev)
  281. {
  282. struct rt_macb_eth *macb = dev->user_data;
  283. unsigned long paddr;
  284. rt_uint32_t hwaddr_bottom;
  285. rt_uint16_t hwaddr_top;
  286. int i;
  287. /*
  288. * macb_halt should have been called at some point before now,
  289. * so we'll assume the controller is idle.
  290. */
  291. /* initialize DMA descriptors */
  292. paddr = macb->rx_buffer_dma;
  293. for (i = 0; i < MACB_RX_RING_SIZE; i++) {
  294. if (i == (MACB_RX_RING_SIZE - 1))
  295. paddr |= RXADDR_WRAP;
  296. macb->rx_ring[i].addr = paddr;
  297. macb->rx_ring[i].ctrl = 0;
  298. paddr += 128;
  299. }
  300. for (i = 0; i < MACB_TX_RING_SIZE; i++) {
  301. macb->tx_ring[i].addr = 0;
  302. if (i == (MACB_TX_RING_SIZE - 1))
  303. macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
  304. else
  305. macb->tx_ring[i].ctrl = TXBUF_USED;
  306. }
  307. macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
  308. macb_writel(macb, RBQP, macb->rx_ring_dma);
  309. macb_writel(macb, TBQP, macb->tx_ring_dma);
  310. /* set hardware address */
  311. hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr));
  312. macb_writel(macb, SA1B, hwaddr_bottom);
  313. hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4)));
  314. macb_writel(macb, SA1T, hwaddr_top);
  315. /* choose RMII or MII mode. This depends on the board */
  316. #ifdef CONFIG_RMII
  317. macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
  318. #else
  319. macb_writel(macb, USRIO, MACB_BIT(CLKEN));
  320. #endif /* CONFIG_RMII */
  321. if (!macb_phy_init(dev))
  322. return -RT_ERROR;
  323. /* Enable TX and RX */
  324. macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE));
  325. /* Enable interrupts */
  326. macb_writel(macb, IER, (MACB_BIT(RCOMP)
  327. | MACB_BIT(RXUBR)
  328. | MACB_BIT(ISR_TUND)
  329. | MACB_BIT(ISR_RLE)
  330. | MACB_BIT(TXERR)
  331. | MACB_BIT(TCOMP)
  332. | MACB_BIT(ISR_ROVR)
  333. | MACB_BIT(HRESP)));
  334. /* instal interrupt */
  335. rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, RT_NULL);
  336. rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC);
  337. rt_timer_init(&macb->timer, "link_timer",
  338. macb_update_link,
  339. macb,
  340. RT_TICK_PER_SECOND,
  341. RT_TIMER_FLAG_PERIODIC);
  342. rt_timer_start(&macb->timer);
  343. return RT_EOK;
  344. }
  345. static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag)
  346. {
  347. return RT_EOK;
  348. }
  349. static rt_err_t rt_macb_close(rt_device_t dev)
  350. {
  351. return RT_EOK;
  352. }
  353. static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
  354. {
  355. rt_set_errno(-RT_ENOSYS);
  356. return 0;
  357. }
  358. static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
  359. {
  360. rt_set_errno(-RT_ENOSYS);
  361. return 0;
  362. }
  363. static rt_err_t rt_macb_control(rt_device_t dev, rt_uint8_t cmd, void *args)
  364. {
  365. switch(cmd)
  366. {
  367. case NIOCTL_GADDR:
  368. /* get mac address */
  369. if(args) rt_memcpy(args, macb_device.dev_addr, 6);
  370. else return -RT_ERROR;
  371. break;
  372. default :
  373. break;
  374. }
  375. return RT_EOK;
  376. }
  377. /* ethernet device interface */
  378. /* transmit packet. */
  379. rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p)
  380. {
  381. struct pbuf* q;
  382. rt_uint8_t* bufptr, *buf = RT_NULL;
  383. unsigned long ctrl;
  384. struct rt_macb_eth *macb = dev->user_data;
  385. unsigned int tx_head = macb->tx_head;
  386. /* lock macb device */
  387. rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
  388. buf = rt_malloc(p->tot_len);
  389. if (!buf) {
  390. rt_kprintf("%s:alloc buf failed\n", __func__);
  391. return NULL;
  392. }
  393. bufptr = buf;
  394. for (q = p; q != NULL; q = q->next)
  395. {
  396. memcpy(bufptr, q->payload, q->len);
  397. bufptr += q->len;
  398. }
  399. ctrl = p->tot_len & TXBUF_FRMLEN_MASK;
  400. ctrl |= TXBUF_FRAME_END;
  401. if (tx_head == (MACB_TX_RING_SIZE - 1)) {
  402. ctrl |= TXBUF_WRAP;
  403. macb->tx_head = 0;
  404. } else
  405. macb->tx_head++;
  406. macb->tx_ring[tx_head].ctrl = ctrl;
  407. macb->tx_ring[tx_head].addr = (rt_uint32_t)buf;
  408. macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
  409. /* unlock macb device */
  410. rt_sem_release(&sem_lock);
  411. /* wait ack */
  412. rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
  413. rt_free(buf);
  414. return RT_EOK;
  415. }
  416. static void reclaim_rx_buffers(struct rt_macb_eth *macb,
  417. unsigned int new_tail)
  418. {
  419. unsigned int i;
  420. i = macb->rx_tail;
  421. while (i > new_tail) {
  422. macb->rx_ring[i].addr &= ~RXADDR_USED;
  423. i++;
  424. if (i > MACB_RX_RING_SIZE)
  425. i = 0;
  426. }
  427. while (i < new_tail) {
  428. macb->rx_ring[i].addr &= ~RXADDR_USED;
  429. i++;
  430. }
  431. macb->rx_tail = new_tail;
  432. }
  433. /* reception packet. */
  434. struct pbuf *rt_macb_rx(rt_device_t dev)
  435. {
  436. struct rt_macb_eth *macb = dev->user_data;
  437. struct pbuf* p = RT_NULL;
  438. rt_uint32_t len;
  439. unsigned int rx_tail = macb->rx_tail;
  440. void *buffer;
  441. int wrapped = 0;
  442. rt_uint32_t status;
  443. struct pbuf* q;
  444. rt_uint8_t *buf = RT_NULL;
  445. /* lock macb device */
  446. rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
  447. for (;;) {
  448. if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
  449. break;
  450. status = macb->rx_ring[rx_tail].ctrl;
  451. if (status & RXBUF_FRAME_START) {
  452. if (rx_tail != macb->rx_tail)
  453. reclaim_rx_buffers(macb, rx_tail);
  454. wrapped = 0;
  455. }
  456. if (status & RXBUF_FRAME_END) {
  457. buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail);
  458. len = status & RXBUF_FRMLEN_MASK;
  459. p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
  460. if (!p)
  461. {
  462. rt_kprintf("alloc pbuf failed\n");
  463. break;
  464. }
  465. if (wrapped) {
  466. unsigned int headlen, taillen;
  467. buf = rt_malloc(len);
  468. if (!buf)
  469. {
  470. rt_kprintf("%s:alloc memory failed\n", __func__);
  471. pbuf_free(p);
  472. p = RT_NULL;
  473. break;
  474. }
  475. headlen = 128 * (MACB_RX_RING_SIZE
  476. - macb->rx_tail);
  477. taillen = len - headlen;
  478. memcpy((void *)buf,
  479. buffer, headlen);
  480. memcpy((void *)((unsigned int)buf + headlen),
  481. macb->rx_buffer, taillen);
  482. buffer = (void *)buf;
  483. for (q = p; q != RT_NULL; q= q->next)
  484. {
  485. /* read data from device */
  486. memcpy((void *)q->payload, buffer, q->len);
  487. buffer = (void *)((unsigned int)buffer + q->len);
  488. }
  489. rt_free(buf);
  490. buf = RT_NULL;
  491. } else {
  492. for (q = p; q != RT_NULL; q= q->next)
  493. {
  494. /* read data from device */
  495. memcpy((void *)q->payload, buffer, q->len);
  496. buffer = (void *)((unsigned int)buffer + q->len);
  497. }
  498. }
  499. if (++rx_tail >= MACB_RX_RING_SIZE)
  500. rx_tail = 0;
  501. reclaim_rx_buffers(macb, rx_tail);
  502. break;
  503. } else {
  504. if (++rx_tail >= MACB_RX_RING_SIZE) {
  505. wrapped = 1;
  506. rx_tail = 0;
  507. }
  508. }
  509. }
  510. /* unlock macb device */
  511. rt_sem_release(&sem_lock);
  512. return p;
  513. }
  514. void macb_gpio_init()
  515. {
  516. /* Pins used for MII and RMII */
  517. at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20));
  518. at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20));
  519. #ifndef GONFIG_RMII
  520. at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29));
  521. at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29));
  522. #endif
  523. }
  524. void macb_initialize()
  525. {
  526. struct rt_macb_eth *macb = &macb_device;
  527. unsigned long macb_hz;
  528. rt_uint32_t ncfgr;
  529. macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE);
  530. macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
  531. macb->tx_ring = rt_malloc(MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
  532. macb->rx_buffer_dma = (unsigned long)macb->rx_buffer;
  533. macb->rx_ring_dma = (unsigned long)macb->rx_ring;
  534. macb->tx_ring_dma = (unsigned long)macb->tx_ring;
  535. macb->regs = AT91SAM9260_BASE_EMAC;
  536. macb->phy_addr = 0x00;
  537. /*
  538. * Do some basic initialization so that we at least can talk
  539. * to the PHY
  540. */
  541. macb_hz = clk_get_rate(clk_get("mck"));
  542. if (macb_hz < 20000000)
  543. ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
  544. else if (macb_hz < 40000000)
  545. ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
  546. else if (macb_hz < 80000000)
  547. ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
  548. else
  549. ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
  550. macb_writel(macb, NCFGR, ncfgr);
  551. }
  552. void rt_hw_macb_init()
  553. {
  554. at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock
  555. macb_gpio_init();
  556. rt_memset(&macb_device, 0, sizeof(macb_device));
  557. macb_initialize();
  558. rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
  559. rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
  560. macb_device.dev_addr[0] = 0x00;
  561. macb_device.dev_addr[1] = 0x60;
  562. macb_device.dev_addr[2] = 0x6E;
  563. macb_device.dev_addr[3] = 0x11;
  564. macb_device.dev_addr[4] = 0x22;
  565. macb_device.dev_addr[5] = 0x33;
  566. macb_device.parent.parent.init = rt_macb_init;
  567. macb_device.parent.parent.open = rt_macb_open;
  568. macb_device.parent.parent.close = rt_macb_close;
  569. macb_device.parent.parent.read = rt_macb_read;
  570. macb_device.parent.parent.write = rt_macb_write;
  571. macb_device.parent.parent.control = rt_macb_control;
  572. macb_device.parent.parent.user_data = &macb_device;
  573. macb_device.parent.eth_rx = rt_macb_rx;
  574. macb_device.parent.eth_tx = rt_macb_tx;
  575. rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO);
  576. eth_device_init(&(macb_device.parent), "e0");
  577. }