drv_pwm.c 16 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-13 zylx first version
  9. * 2021-01-23 thread-liu Fix the timer clock frequency doubling problem
  10. */
  11. #include <board.h>
  12. #ifdef BSP_USING_PWM
  13. #include "drv_config.h"
  14. #include "drv_tim.h"
  15. #include <drivers/rt_drv_pwm.h>
  16. //#define DRV_DEBUG
  17. #define LOG_TAG "drv.pwm"
  18. #include <drv_log.h>
  19. #define MAX_PERIOD 65535
  20. #define MIN_PERIOD 3
  21. #define MIN_PULSE 2
  22. extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
  23. enum
  24. {
  25. #ifdef BSP_USING_PWM1
  26. PWM1_INDEX,
  27. #endif
  28. #ifdef BSP_USING_PWM2
  29. PWM2_INDEX,
  30. #endif
  31. #ifdef BSP_USING_PWM3
  32. PWM3_INDEX,
  33. #endif
  34. #ifdef BSP_USING_PWM4
  35. PWM4_INDEX,
  36. #endif
  37. #ifdef BSP_USING_PWM5
  38. PWM5_INDEX,
  39. #endif
  40. #ifdef BSP_USING_PWM6
  41. PWM6_INDEX,
  42. #endif
  43. #ifdef BSP_USING_PWM7
  44. PWM7_INDEX,
  45. #endif
  46. #ifdef BSP_USING_PWM8
  47. PWM8_INDEX,
  48. #endif
  49. #ifdef BSP_USING_PWM9
  50. PWM9_INDEX,
  51. #endif
  52. #ifdef BSP_USING_PWM10
  53. PWM10_INDEX,
  54. #endif
  55. #ifdef BSP_USING_PWM11
  56. PWM11_INDEX,
  57. #endif
  58. #ifdef BSP_USING_PWM12
  59. PWM12_INDEX,
  60. #endif
  61. #ifdef BSP_USING_PWM13
  62. PWM13_INDEX,
  63. #endif
  64. #ifdef BSP_USING_PWM14
  65. PWM14_INDEX,
  66. #endif
  67. #ifdef BSP_USING_PWM15
  68. PWM15_INDEX,
  69. #endif
  70. #ifdef BSP_USING_PWM16
  71. PWM16_INDEX,
  72. #endif
  73. #ifdef BSP_USING_PWM17
  74. PWM17_INDEX,
  75. #endif
  76. };
  77. struct stm32_pwm
  78. {
  79. struct rt_device_pwm pwm_device;
  80. TIM_HandleTypeDef tim_handle;
  81. rt_uint8_t channel;
  82. char *name;
  83. };
  84. static struct stm32_pwm stm32_pwm_obj[] =
  85. {
  86. #ifdef BSP_USING_PWM1
  87. PWM1_CONFIG,
  88. #endif
  89. #ifdef BSP_USING_PWM2
  90. PWM2_CONFIG,
  91. #endif
  92. #ifdef BSP_USING_PWM3
  93. PWM3_CONFIG,
  94. #endif
  95. #ifdef BSP_USING_PWM4
  96. PWM4_CONFIG,
  97. #endif
  98. #ifdef BSP_USING_PWM5
  99. PWM5_CONFIG,
  100. #endif
  101. #ifdef BSP_USING_PWM6
  102. PWM6_CONFIG,
  103. #endif
  104. #ifdef BSP_USING_PWM7
  105. PWM7_CONFIG,
  106. #endif
  107. #ifdef BSP_USING_PWM8
  108. PWM8_CONFIG,
  109. #endif
  110. #ifdef BSP_USING_PWM9
  111. PWM9_CONFIG,
  112. #endif
  113. #ifdef BSP_USING_PWM10
  114. PWM10_CONFIG,
  115. #endif
  116. #ifdef BSP_USING_PWM11
  117. PWM11_CONFIG,
  118. #endif
  119. #ifdef BSP_USING_PWM12
  120. PWM12_CONFIG,
  121. #endif
  122. #ifdef BSP_USING_PWM13
  123. PWM13_CONFIG,
  124. #endif
  125. #ifdef BSP_USING_PWM14
  126. PWM14_CONFIG,
  127. #endif
  128. #ifdef BSP_USING_PWM15
  129. PWM15_CONFIG,
  130. #endif
  131. #ifdef BSP_USING_PWM16
  132. PWM16_CONFIG,
  133. #endif
  134. #ifdef BSP_USING_PWM17
  135. PWM17_CONFIG,
  136. #endif
  137. };
  138. static rt_uint64_t tim_clock_get(TIM_HandleTypeDef *htim)
  139. {
  140. rt_uint32_t pclk1_doubler, pclk2_doubler;
  141. rt_uint64_t tim_clock;
  142. stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  143. /* Some series may only have APBPERIPH_BASE, don't have HAL_RCC_GetPCLK2Freq */
  144. #if defined(APBPERIPH_BASE)
  145. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  146. #elif defined(APB1PERIPH_BASE) || defined(APB2PERIPH_BASE)
  147. if ((rt_uint32_t)htim->Instance >= APB2PERIPH_BASE)
  148. {
  149. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler);
  150. }
  151. else
  152. {
  153. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  154. }
  155. #endif
  156. return tim_clock;
  157. }
  158. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
  159. static struct rt_pwm_ops drv_ops =
  160. {
  161. drv_pwm_control
  162. };
  163. static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
  164. {
  165. /* Converts the channel number to the channel number of Hal library */
  166. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  167. if (!configuration->complementary)
  168. {
  169. if (!enable)
  170. {
  171. HAL_TIM_PWM_Stop(htim, channel);
  172. }
  173. else
  174. {
  175. HAL_TIM_PWM_Start(htim, channel);
  176. }
  177. }
  178. else if (configuration->complementary)
  179. {
  180. if (!enable)
  181. {
  182. HAL_TIMEx_PWMN_Stop(htim, channel);
  183. }
  184. else
  185. {
  186. HAL_TIMEx_PWMN_Start(htim, channel);
  187. }
  188. }
  189. return RT_EOK;
  190. }
  191. static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  192. {
  193. /* Converts the channel number to the channel number of Hal library */
  194. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  195. rt_uint64_t tim_clock;
  196. tim_clock = tim_clock_get(htim);
  197. if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
  198. {
  199. tim_clock = tim_clock / 2;
  200. }
  201. else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
  202. {
  203. tim_clock = tim_clock / 4;
  204. }
  205. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  206. tim_clock /= 1000000UL;
  207. configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  208. configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  209. return RT_EOK;
  210. }
  211. static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  212. {
  213. rt_uint32_t period, pulse;
  214. rt_uint64_t tim_clock, psc;
  215. /* Converts the channel number to the channel number of Hal library */
  216. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  217. tim_clock = tim_clock_get(htim);
  218. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  219. tim_clock /= 1000000UL;
  220. period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL ;
  221. psc = period / MAX_PERIOD + 1;
  222. period = period / psc;
  223. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  224. if (period < MIN_PERIOD)
  225. {
  226. period = MIN_PERIOD;
  227. }
  228. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  229. pulse = (rt_uint64_t)configuration->pulse * tim_clock / psc / 1000ULL;
  230. if (pulse < MIN_PULSE)
  231. {
  232. pulse = MIN_PULSE;
  233. }
  234. /*To determine user input, output high level is required*/
  235. else if (pulse >= period)
  236. {
  237. pulse = period + 1;
  238. }
  239. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  240. /* If you want the PWM setting to take effect immediately,
  241. please uncommon the following code, but it will cause the last PWM cycle not complete. */
  242. //__HAL_TIM_SET_COUNTER(htim, 0);
  243. //HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE); /* Update frequency value */
  244. return RT_EOK;
  245. }
  246. static rt_err_t drv_pwm_set_period(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  247. {
  248. rt_uint32_t period;
  249. rt_uint64_t tim_clock, psc;
  250. tim_clock = tim_clock_get(htim);
  251. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  252. tim_clock /= 1000000UL;
  253. period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL ;
  254. psc = period / MAX_PERIOD + 1;
  255. period = period / psc;
  256. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  257. if (period < MIN_PERIOD)
  258. {
  259. period = MIN_PERIOD;
  260. }
  261. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  262. return RT_EOK;
  263. }
  264. static rt_err_t drv_pwm_set_pulse(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  265. {
  266. rt_uint32_t period, pulse;
  267. rt_uint64_t tim_clock;
  268. /* Converts the channel number to the channel number of Hal library */
  269. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  270. tim_clock = tim_clock_get(htim);
  271. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  272. tim_clock /= 1000000UL;
  273. period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  274. pulse = (rt_uint64_t)configuration->pulse * (__HAL_TIM_GET_AUTORELOAD(htim) + 1) / period;
  275. if (pulse < MIN_PULSE)
  276. {
  277. pulse = MIN_PULSE;
  278. }
  279. else if (pulse > period)
  280. {
  281. pulse = period;
  282. }
  283. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  284. return RT_EOK;
  285. }
  286. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
  287. {
  288. struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
  289. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
  290. switch (cmd)
  291. {
  292. case PWM_CMD_ENABLE:
  293. return drv_pwm_enable(htim, configuration, RT_TRUE);
  294. case PWM_CMD_DISABLE:
  295. return drv_pwm_enable(htim, configuration, RT_FALSE);
  296. case PWM_CMD_SET:
  297. return drv_pwm_set(htim, configuration);
  298. case PWM_CMD_SET_PERIOD:
  299. return drv_pwm_set_period(htim, configuration);
  300. case PWM_CMD_SET_PULSE:
  301. return drv_pwm_set_pulse(htim, configuration);
  302. case PWM_CMD_GET:
  303. return drv_pwm_get(htim, configuration);
  304. default:
  305. return -RT_EINVAL;
  306. }
  307. }
  308. static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
  309. {
  310. rt_err_t result = RT_EOK;
  311. TIM_HandleTypeDef *tim = RT_NULL;
  312. TIM_OC_InitTypeDef oc_config = {0};
  313. TIM_MasterConfigTypeDef master_config = {0};
  314. TIM_ClockConfigTypeDef clock_config = {0};
  315. RT_ASSERT(device != RT_NULL);
  316. tim = (TIM_HandleTypeDef *)&device->tim_handle;
  317. /* configure the timer to pwm mode */
  318. tim->Init.Prescaler = 0;
  319. tim->Init.CounterMode = TIM_COUNTERMODE_UP;
  320. tim->Init.Period = 0;
  321. tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  322. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
  323. tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  324. #endif
  325. if (HAL_TIM_Base_Init(tim) != HAL_OK)
  326. {
  327. LOG_E("%s pwm init failed", device->name);
  328. result = -RT_ERROR;
  329. goto __exit;
  330. }
  331. if (HAL_TIM_PWM_Init(tim) != HAL_OK)
  332. {
  333. LOG_E("%s pwm init failed", device->name);
  334. result = -RT_ERROR;
  335. goto __exit;
  336. }
  337. clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  338. if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
  339. {
  340. LOG_E("%s clock init failed", device->name);
  341. result = -RT_ERROR;
  342. goto __exit;
  343. }
  344. if(IS_TIM_MASTER_INSTANCE(tim->Instance))
  345. {
  346. master_config.MasterOutputTrigger = TIM_TRGO_RESET;
  347. master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  348. if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
  349. {
  350. LOG_E("%s master config failed", device->name);
  351. result = -RT_ERROR;
  352. goto __exit;
  353. }
  354. }
  355. oc_config.OCMode = TIM_OCMODE_PWM1;
  356. oc_config.Pulse = 0;
  357. oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
  358. oc_config.OCFastMode = TIM_OCFAST_DISABLE;
  359. oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  360. oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
  361. /* config pwm channel */
  362. if (device->channel & 0x01)
  363. {
  364. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
  365. {
  366. LOG_E("%s channel1 config failed", device->name);
  367. result = -RT_ERROR;
  368. goto __exit;
  369. }
  370. }
  371. if (device->channel & 0x02)
  372. {
  373. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
  374. {
  375. LOG_E("%s channel2 config failed", device->name);
  376. result = -RT_ERROR;
  377. goto __exit;
  378. }
  379. }
  380. if (device->channel & 0x04)
  381. {
  382. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
  383. {
  384. LOG_E("%s channel3 config failed", device->name);
  385. result = -RT_ERROR;
  386. goto __exit;
  387. }
  388. }
  389. if (device->channel & 0x08)
  390. {
  391. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
  392. {
  393. LOG_E("%s channel4 config failed", device->name);
  394. result = -RT_ERROR;
  395. goto __exit;
  396. }
  397. }
  398. /* pwm pin configuration */
  399. HAL_TIM_MspPostInit(tim);
  400. /* enable update request source */
  401. __HAL_TIM_URS_ENABLE(tim);
  402. __exit:
  403. return result;
  404. }
  405. static void pwm_get_channel(void)
  406. {
  407. #ifdef BSP_USING_PWM1_CH1
  408. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
  409. #endif
  410. #ifdef BSP_USING_PWM1_CH2
  411. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
  412. #endif
  413. #ifdef BSP_USING_PWM1_CH3
  414. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
  415. #endif
  416. #ifdef BSP_USING_PWM1_CH4
  417. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
  418. #endif
  419. #ifdef BSP_USING_PWM2_CH1
  420. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
  421. #endif
  422. #ifdef BSP_USING_PWM2_CH2
  423. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
  424. #endif
  425. #ifdef BSP_USING_PWM2_CH3
  426. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
  427. #endif
  428. #ifdef BSP_USING_PWM2_CH4
  429. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
  430. #endif
  431. #ifdef BSP_USING_PWM3_CH1
  432. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
  433. #endif
  434. #ifdef BSP_USING_PWM3_CH2
  435. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
  436. #endif
  437. #ifdef BSP_USING_PWM3_CH3
  438. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
  439. #endif
  440. #ifdef BSP_USING_PWM3_CH4
  441. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
  442. #endif
  443. #ifdef BSP_USING_PWM4_CH1
  444. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
  445. #endif
  446. #ifdef BSP_USING_PWM4_CH2
  447. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
  448. #endif
  449. #ifdef BSP_USING_PWM4_CH3
  450. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
  451. #endif
  452. #ifdef BSP_USING_PWM4_CH4
  453. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
  454. #endif
  455. #ifdef BSP_USING_PWM5_CH1
  456. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
  457. #endif
  458. #ifdef BSP_USING_PWM5_CH2
  459. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
  460. #endif
  461. #ifdef BSP_USING_PWM5_CH3
  462. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
  463. #endif
  464. #ifdef BSP_USING_PWM5_CH4
  465. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
  466. #endif
  467. #ifdef BSP_USING_PWM6_CH1
  468. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
  469. #endif
  470. #ifdef BSP_USING_PWM6_CH2
  471. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
  472. #endif
  473. #ifdef BSP_USING_PWM6_CH3
  474. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
  475. #endif
  476. #ifdef BSP_USING_PWM6_CH4
  477. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
  478. #endif
  479. #ifdef BSP_USING_PWM7_CH1
  480. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
  481. #endif
  482. #ifdef BSP_USING_PWM7_CH2
  483. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
  484. #endif
  485. #ifdef BSP_USING_PWM7_CH3
  486. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
  487. #endif
  488. #ifdef BSP_USING_PWM7_CH4
  489. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
  490. #endif
  491. #ifdef BSP_USING_PWM8_CH1
  492. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
  493. #endif
  494. #ifdef BSP_USING_PWM8_CH2
  495. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
  496. #endif
  497. #ifdef BSP_USING_PWM8_CH3
  498. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
  499. #endif
  500. #ifdef BSP_USING_PWM8_CH4
  501. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
  502. #endif
  503. #ifdef BSP_USING_PWM9_CH1
  504. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
  505. #endif
  506. #ifdef BSP_USING_PWM9_CH2
  507. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
  508. #endif
  509. #ifdef BSP_USING_PWM9_CH3
  510. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
  511. #endif
  512. #ifdef BSP_USING_PWM9_CH4
  513. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
  514. #endif
  515. #ifdef BSP_USING_PWM10_CH1
  516. stm32_pwm_obj[PWM10_INDEX].channel |= 1 << 0;
  517. #endif
  518. #ifdef BSP_USING_PWM11_CH1
  519. stm32_pwm_obj[PWM11_INDEX].channel |= 1 << 0;
  520. #endif
  521. #ifdef BSP_USING_PWM12_CH1
  522. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
  523. #endif
  524. #ifdef BSP_USING_PWM12_CH2
  525. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
  526. #endif
  527. #ifdef BSP_USING_PWM13_CH1
  528. stm32_pwm_obj[PWM13_INDEX].channel |= 1 << 0;
  529. #endif
  530. #ifdef BSP_USING_PWM14_CH1
  531. stm32_pwm_obj[PWM14_INDEX].channel |= 1 << 0;
  532. #endif
  533. #ifdef BSP_USING_PWM15_CH1
  534. stm32_pwm_obj[PWM15_INDEX].channel |= 1 << 0;
  535. #endif
  536. #ifdef BSP_USING_PWM16_CH1
  537. stm32_pwm_obj[PWM16_INDEX].channel |= 1 << 0;
  538. #endif
  539. #ifdef BSP_USING_PWM17_CH1
  540. stm32_pwm_obj[PWM17_INDEX].channel |= 1 << 0;
  541. #endif
  542. }
  543. static int stm32_pwm_init(void)
  544. {
  545. int i = 0;
  546. int result = RT_EOK;
  547. pwm_get_channel();
  548. for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
  549. {
  550. /* pwm init */
  551. if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
  552. {
  553. LOG_E("%s init failed", stm32_pwm_obj[i].name);
  554. result = -RT_ERROR;
  555. goto __exit;
  556. }
  557. else
  558. {
  559. LOG_D("%s init success", stm32_pwm_obj[i].name);
  560. /* register pwm device */
  561. if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
  562. {
  563. LOG_D("%s register success", stm32_pwm_obj[i].name);
  564. }
  565. else
  566. {
  567. LOG_E("%s register failed", stm32_pwm_obj[i].name);
  568. result = -RT_ERROR;
  569. }
  570. }
  571. }
  572. __exit:
  573. return result;
  574. }
  575. INIT_DEVICE_EXPORT(stm32_pwm_init);
  576. #endif /* BSP_USING_PWM */