uart.c 4.9 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-04-09 Jonne Code refactoring for new bsp
  9. */
  10. #include <stddef.h>
  11. #include <rthw.h>
  12. #include <rtdevice.h>
  13. #include <board.h>
  14. #define ULCON_OFS 0x00
  15. #define UCON_OFS 0x04
  16. #define UFCON_OFS 0x08
  17. #define UMCON_OFS 0x0c
  18. #define UTRSTAT_OFS 0x10
  19. #define UERSTAT_OFS 0x14
  20. #define UFSTAT_OFS 0x18
  21. #define UMSTAT_OFS 0x1c
  22. #define UTXH_OFS 0x20
  23. #define URXH_OFS 0x24
  24. #define UBRDIV_OFS 0x28
  25. #define readl(addr) (*(volatile unsigned long *)(addr))
  26. #define writel(addr, value) (*(volatile unsigned long *)(addr) = value)
  27. #define PCLK_HZ 50000000
  28. struct hw_uart_device
  29. {
  30. rt_uint32_t hw_base;
  31. rt_uint32_t irqno;
  32. };
  33. static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  34. {
  35. struct hw_uart_device *uart = serial->parent.user_data;
  36. writel(uart->hw_base + UBRDIV_OFS, PCLK_HZ / (cfg->baud_rate * 16));
  37. writel(uart->hw_base + ULCON_OFS, 0x03);// 8bit data, 1bit stop, No parity
  38. writel(uart->hw_base + UCON_OFS, 0x05);
  39. writel(uart->hw_base + UFCON_OFS, 0x00);
  40. writel(uart->hw_base + UMCON_OFS, 0x00);
  41. return RT_EOK;
  42. }
  43. static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd, void *arg)
  44. {
  45. struct hw_uart_device *uart;
  46. int mask;
  47. RT_ASSERT(serial != RT_NULL);
  48. uart = (struct hw_uart_device *)serial->parent.user_data;
  49. if (uart->irqno == INTUART0)
  50. {
  51. mask = BIT_SUB_RXD0;
  52. }
  53. else if (uart->irqno == INTUART1)
  54. {
  55. mask = BIT_SUB_RXD1;
  56. }
  57. else
  58. {
  59. mask = BIT_SUB_RXD2;
  60. }
  61. switch (cmd)
  62. {
  63. case RT_DEVICE_CTRL_CLR_INT:
  64. /* disable rx irq */
  65. INTSUBMSK |= mask;
  66. break;
  67. case RT_DEVICE_CTRL_SET_INT:
  68. /* enable rx irq */
  69. INTSUBMSK &= ~mask;
  70. break;
  71. }
  72. return RT_EOK;
  73. }
  74. static int s3c2440_putc(struct rt_serial_device *serial, char c)
  75. {
  76. struct hw_uart_device *uart = serial->parent.user_data;
  77. while (!(readl(uart->hw_base + UTRSTAT_OFS) & (1 << 2)))
  78. {
  79. }
  80. writel(uart->hw_base + UTXH_OFS, c);
  81. return 0;
  82. }
  83. static int s3c2440_getc(struct rt_serial_device *serial)
  84. {
  85. struct hw_uart_device *uart = serial->parent.user_data;
  86. int ch = -1;
  87. if (readl(uart->hw_base + UTRSTAT_OFS) & (1 << 0))
  88. {
  89. ch = readl(uart->hw_base + URXH_OFS) & 0x000000FF;
  90. }
  91. return ch;
  92. }
  93. static void rt_hw_uart_isr(int irqno, void *param)
  94. {
  95. struct rt_serial_device *serial = (struct rt_serial_device *)param;
  96. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  97. /*clear SUBSRCPND*/
  98. if (irqno == INTUART0)
  99. {
  100. SUBSRCPND = BIT_SUB_RXD0;
  101. }
  102. else if (irqno == INTUART1)
  103. {
  104. SUBSRCPND = BIT_SUB_RXD1;
  105. }
  106. else
  107. {
  108. SUBSRCPND = BIT_SUB_RXD2;
  109. }
  110. }
  111. static struct rt_uart_ops s3c2440_uart_ops =
  112. {
  113. .configure = s3c2440_serial_configure,
  114. .control = s3c2440_serial_control,
  115. .putc = s3c2440_putc,
  116. .getc = s3c2440_getc
  117. };
  118. static struct rt_serial_device _serial0 =
  119. {
  120. .ops = &s3c2440_uart_ops,
  121. .config = RT_SERIAL_CONFIG_DEFAULT,
  122. .serial_rx = NULL,
  123. .serial_tx = NULL
  124. };
  125. static struct hw_uart_device _hwserial0 =
  126. {
  127. .hw_base = 0x50000000,
  128. .irqno = INTUART0
  129. };
  130. static struct rt_serial_device _serial1 =
  131. {
  132. .ops = &s3c2440_uart_ops,
  133. .config = RT_SERIAL_CONFIG_DEFAULT,
  134. .serial_rx = NULL,
  135. .serial_tx = NULL
  136. };
  137. static struct hw_uart_device _hwserial1 =
  138. {
  139. .hw_base = 0x50004000,
  140. .irqno = INTUART1
  141. };
  142. static struct rt_serial_device _serial2 =
  143. {
  144. .ops = &s3c2440_uart_ops,
  145. .config = RT_SERIAL_CONFIG_DEFAULT,
  146. .serial_rx = NULL,
  147. .serial_tx = NULL
  148. };
  149. static struct hw_uart_device _hwserial2 =
  150. {
  151. .hw_base = 0x50008000,
  152. .irqno = INTUART2
  153. };
  154. int rt_hw_uart_init(void)
  155. {
  156. /* UART0 UART1 UART2 port configure */
  157. GPHCON |= 0xAAAA;
  158. /* PULLUP is disable */
  159. GPHUP |= 0xFFF;
  160. /* register UART0 device */
  161. rt_hw_serial_register(&_serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial0);
  162. rt_hw_interrupt_install(_hwserial0.irqno, rt_hw_uart_isr, &_serial0, "uart0");
  163. rt_hw_interrupt_umask(INTUART0);
  164. /* register UART1 device */
  165. rt_hw_serial_register(&_serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial1);
  166. rt_hw_interrupt_install(_hwserial1.irqno, rt_hw_uart_isr, &_serial1, "uart1");
  167. rt_hw_interrupt_umask(INTUART1);
  168. /* register UART2 device */
  169. rt_hw_serial_register(&_serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial2);
  170. rt_hw_interrupt_install(_hwserial2.irqno, rt_hw_uart_isr, &_serial2, "uart2");
  171. rt_hw_interrupt_umask(INTUART2);
  172. return RT_EOK;
  173. }
  174. INIT_BOARD_EXPORT(rt_hw_uart_init);