soc.h 17 KB

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  1. /*
  2. * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
  3. *
  4. * Licensed under the Apache License, Version 2.0 (the "License");
  5. * you may not use this file except in compliance with the License.
  6. * You may obtain a copy of the License at
  7. *
  8. * http://www.apache.org/licenses/LICENSE-2.0
  9. *
  10. * Unless required by applicable law or agreed to in writing, software
  11. * distributed under the License is distributed on an "AS IS" BASIS,
  12. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13. * See the License for the specific language governing permissions and
  14. * limitations under the License.
  15. */
  16. /**************************************************************************//**
  17. * @file soc.h
  18. * @brief CSI Core Peripheral Access Layer Header File for
  19. * CSKYSOC Device Series
  20. * @version V1.0
  21. * @date 02. June 2017
  22. ******************************************************************************/
  23. #ifndef SOC_H
  24. #define SOC_H
  25. #ifdef __cplusplus
  26. extern "C" {
  27. #endif
  28. #define SYSTEM_CLOCK (20000000)
  29. /* ------------------------- Interrupt Number Definition ------------------------ */
  30. typedef enum IRQn
  31. {
  32. /* ---------------------- CSKYCK801 Specific Interrupt Numbers --------------------- */
  33. GPIOA_IRQn = 0,
  34. CORET_IRQn = 1, /* core Timer Interrupt */
  35. TIMA0_IRQn = 2, /* timerA0 Interrupt */
  36. TIMA1_IRQn = 3, /* timerA1 Interrupt */
  37. WDT_IRQn = 5, /* wdt Interrupt */
  38. UART0_IRQn = 6, /* uart0 Interrupt */
  39. UART1_IRQn = 7, /* uart1 Interrupt */
  40. UART2_IRQn = 8, /* uart2 Interrupt */
  41. I2C0_IRQn = 9, /* i2c0 Interrupt */
  42. I2C1_IRQn = 10, /* i2c1 Interrupt */
  43. SPI1_IRQn = 11, /* spi0 Interrupt */
  44. SPI0_IRQn = 12, /* spi1 Interrupt */
  45. RTC_IRQn = 13, /* rtc Interrupt */
  46. EXTWAK_IRQn = 14, /* extwakeup Interrupt */
  47. DMAC_IRQn = 17, /* dmac Interrupt */
  48. PMU_IRQn = 18, /* pmu Interrupt */
  49. PWM_IRQn = 19, /* pwm Interrupt */
  50. UART3_IRQn = 21, /* uart3 Interrupt */
  51. TIMB0_IRQn = 23, /* timerB0 Interrupt */
  52. TIMB1_IRQn = 24, /* timerB1 Interrupt */
  53. GPIOB_IRQn = 27, /* GPIOB Interrupt */
  54. AES_IRQn = 26, /* aes Interrupt */
  55. RSA_IRQn = 28, /* rsa Interrupt */
  56. SHA_IRQn = 29, /* sha Interrupt */
  57. }
  58. IRQn_Type;
  59. /* ================================================================================ */
  60. /* ================ Processor and Core Peripheral Section ================ */
  61. /* ================================================================================ */
  62. /* -------- Configuration of the CK801 Processor and Core Peripherals ------- */
  63. #define __CK802_REV 0x0000U /* Core revision r0p0 */
  64. #define __MGU_PRESENT 0 /* MGU present or not */
  65. #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
  66. #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
  67. #include "core_ck802.h" /* Processor and core peripherals */
  68. #include "stdint.h"
  69. typedef enum
  70. {
  71. CKENUM_DMA_UART0_RX,
  72. CKENUM_DMA_UART0_TX,
  73. CKENUM_DMA_UART1_RX,
  74. CKENUM_DMA_UART1_TX,
  75. CKENUM_DMA_ADC_RX,
  76. CKENUM_DMA_ADC_TX,
  77. CKENUM_DMA_SPI1_RX,
  78. CKENUM_DMA_SPI1_TX,
  79. CKENUM_DMA_SPI0_RX,
  80. CKENUM_DMA_SPI0_TX,
  81. CKENUM_DMA_IIC_RX,
  82. CKENUM_DMA_IIC_TX,
  83. CKENUM_DMA_IIC1_RX,
  84. CKENUM_DMA_IIC1_TX,
  85. CKENUM_DMA_IIS_RX,
  86. CKENUM_DMA_IIS_TX,
  87. CKENUM_DMA_MEMORY
  88. } ckenum_dma_device_e;
  89. /* ================================================================================ */
  90. /* ================ Device Specific Peripheral Section ================ */
  91. /* ================================================================================ */
  92. #if 0
  93. /* ================================================================================ */
  94. /* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
  95. /* ================================================================================ */
  96. typedef struct
  97. {
  98. union
  99. {
  100. __IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */
  101. __OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */
  102. __IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */
  103. };
  104. union
  105. {
  106. __IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */
  107. __IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */
  108. };
  109. __IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */
  110. __IOM uint32_t LCR; /* Offset: 0x00C (R/W) Transmission control register */
  111. __IOM uint32_t MCR; /* Offset: 0x010 (R/W) Modem control register */
  112. __IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */
  113. __IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */
  114. uint32_t RESERVED1[24];
  115. __IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */
  116. } CSKY_UART_TypeDef;
  117. /* ================================================================================ */
  118. /* ============== Inter-Integrated Circuit (IIC) ============= */
  119. /* ================================================================================ */
  120. typedef struct
  121. {
  122. __IOM uint32_t IC_CON; /* Offset: 0x000 (R/W) Receive buffer register */
  123. __IOM uint32_t IC_TAR; /* Offset: 0x004 (R/W) Transmission hold register */
  124. __IOM uint32_t IC_SAR; /* Offset: 0x008 (R/W) Clock frequency division low section register */
  125. __IOM uint32_t IC_HS_MADDR; /* Offset: 0x00c (R/W) Clock frequency division high section register */
  126. __IOM uint32_t IC_DATA_CMD; /* Offset: 0x010 (R/W) Interrupt enable register */
  127. __IOM uint32_t IC_SS_SCL_HCNT; /* Offset: 0x014 (R/W) Interrupt indicia register */
  128. __IOM uint32_t IC_SS_SCL_LCNT; /* Offset: 0x018 (R/W) Transmission control register */
  129. __IOM uint32_t IC_FS_SCL_HCNT; /* Offset: 0x01c (R/W) Modem control register */
  130. __IOM uint32_t IC_FS_SCL_LCNT; /* Offset: 0x020 (R/W) Transmission state register */
  131. __IOM uint32_t IC_HS_SCL_HCNT; /* Offset: 0x024 (R/W) Transmission state register */
  132. __IOM uint32_t IC_HS_SCL_LCNT; /* Offset: 0x028 (R/W) Transmission state register */
  133. __IOM uint32_t IC_INTR_STAT; /* Offset: 0x02c (R) Transmission state register */
  134. __IOM uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) Transmission state register */
  135. __IOM uint32_t IC_RAW_INTR_STAT; /* Offset: 0x034 (R) Transmission state register */
  136. __IOM uint32_t IC_RX_TL; /* Offset: 0x038 (R/W) Transmission state register */
  137. __IOM uint32_t IC_TX_TL; /* Offset: 0x03c (R/W) Transmission state register */
  138. __IOM uint32_t IC_CLR_INTR; /* Offset: 0x040 (R) Transmission state register */
  139. __IOM uint32_t IC_CLR_RX_UNDER; /* Offset: 0x044 (R) Transmission state register */
  140. __IOM uint32_t IC_CLR_RX_OVER; /* Offset: 0x048 (R) Transmission state register */
  141. __IOM uint32_t IC_CLR_TX_OVER; /* Offset: 0x04c (R) Transmission state register */
  142. __IOM uint32_t IC_CLR_RD_REQ; /* Offset: 0x050 (R) Transmission state register */
  143. __IOM uint32_t IC_CLR_TX_ABRT; /* Offset: 0x054 (R) Transmission state register */
  144. __IOM uint32_t IC_CLR_RX_DONE; /* Offset: 0x058 (R) Transmission state register */
  145. __IOM uint32_t IC_CLR_ACTIVITY; /* Offset: 0x05c (R) Transmission state register */
  146. __IOM uint32_t IC_CLR_STOP_DET; /* Offset: 0x060 (R) Transmission state register */
  147. __IOM uint32_t IC_CLR_START_DET; /* Offset: 0x064 (R) Transmission state register */
  148. __IOM uint32_t IC_CLR_GEN_CALL; /* Offset: 0x068 (R) Transmission state register */
  149. __IOM uint32_t IC_ENABLE; /* Offset: 0x06c (R/W) Transmission state register */
  150. __IOM uint32_t IC_STATUS; /* Offset: 0x070 (R) Transmission state register */
  151. __IOM uint32_t IC_TXFLR; /* Offset: 0x074 (R) Transmission state register */
  152. __IOM uint32_t IC_RXFLR; /* Offset: 0x078 (R) Transmission state register */
  153. uint32_t RESERVED; /* Offset: 0x014 (R/ ) Transmission state register */
  154. __IOM uint32_t IC_TX_ABRT_SOURCE; /* Offset: 0x080 (R/W) Transmission state register */
  155. __IOM uint32_t IC_SAR1; /* Offset: 0x084 (R/W) Transmission state register */
  156. __IOM uint32_t IC_DMA_CR; /* Offset: 0x088 (R/W) Transmission state register */
  157. __IOM uint32_t IC_DMA_TDLR; /* Offset: 0x08c (R/W) Transmission state register */
  158. __IOM uint32_t IC_DMA_RDLR; /* Offset: 0x090 (R/W) Transmission state register */
  159. __IOM uint32_t IC_SAR2; /* Offset: 0x094 (R/W) Transmission state register */
  160. __IOM uint32_t IC_SAR3; /* Offset: 0x098 (R/W) Transmission state register */
  161. __IOM uint32_t IC_MULTI_SLAVE; /* Offset: 0x09c (R/W) Transmission state register */
  162. __IOM uint32_t IC_GEN_CALL_EN; /* Offset: 0x0a0 (R/W) Transmission state register */
  163. } CSKY_IIC_TypeDef;
  164. /* ================================================================================ */
  165. /* ============== TIMER ============= */
  166. /* ================================================================================ */
  167. typedef struct
  168. {
  169. __IOM uint32_t TxLoadCount; /* Offset: 0x000 (R/W) Receive buffer register */
  170. __IOM uint32_t TxCurrentValue; /* Offset: 0x004 (R) Transmission hold register */
  171. __IOM uint32_t TxControl; /* Offset: 0x008 (R/W) Clock frequency division low section register */
  172. __IOM uint32_t TxEOI; /* Offset: 0x00c (R) Clock frequency division high section register */
  173. __IOM uint32_t TxIntStatus; /* Offset: 0x010 (R) Interrupt enable register */
  174. } CSKY_TIMER_TypeDef;
  175. /* ================================================================================ */
  176. /* ============== TIMER Control ============= */
  177. /* ================================================================================ */
  178. typedef struct
  179. {
  180. __IOM uint32_t TimersIntStatus; /* Offset: 0x000 (R) Interrupt indicia register */
  181. __IOM uint32_t TimerEOI; /* Offset: 0x004 (R) Transmission control register */
  182. __IOM uint32_t TimerRawIntStatus; /* Offset: 0x008 (R) Modem control register */
  183. } CSKY_TIMER_Control_TypeDef;
  184. /* ================================================================================ */
  185. /* ============== GPIO ============= */
  186. /* ================================================================================ */
  187. typedef struct
  188. {
  189. __IOM uint32_t SWPORT_DR; /* Offset: 0x000 (R/W) Interrupt indicia register */
  190. __IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (R/W) Interrupt indicia register */
  191. __IOM uint32_t PORT_CTL; /* Offset: 0x008 (R/W) Interrupt indicia register */
  192. } CKStruct_GPIO, *PCKStruct_GPIO;
  193. typedef struct
  194. {
  195. __IOM uint32_t SHA_CON; /* Offset: 0x000 (R/W) Control register */
  196. __IOM uint32_t SHA_INTSTATE; /* Offset: 0x004 (R/W) Instatus register */
  197. __IOM uint32_t SHA_H0L; /* Offset: 0x008 (R/W) H0L register */
  198. __IOM uint32_t SHA_H1L; /* Offset: 0x00c (R/W) H1L register */
  199. __IOM uint32_t SHA_H2L; /* Offset: 0x010 (R/W) H2L register */
  200. __IOM uint32_t SHA_H3L; /* Offset: 0x014 (R/W) H3L register */
  201. __IOM uint32_t SHA_H4L; /* Offset: 0x018 (R/W) H4L register */
  202. __IOM uint32_t SHA_H5L; /* Offset: 0x01c (R/W) H5L register */
  203. __IOM uint32_t SHA_H6L; /* Offset: 0x020 (R/W) H6L register */
  204. __IOM uint32_t SHA_H7L; /* Offset: 0x024 (R/W) H7L register */
  205. __IOM uint32_t SHA_H0H; /* Offset: 0x028 (R/W) H0H register */
  206. __IOM uint32_t SHA_H1H; /* Offset: 0x02c (R/W) H1H register */
  207. __IOM uint32_t SHA_H2H; /* Offset: 0x030 (R/W) H2H register */
  208. __IOM uint32_t SHA_H3H; /* Offset: 0x034 (R/W) H3H register */
  209. __IOM uint32_t SHA_H4H; /* Offset: 0x038 (R/W) H4H register */
  210. __IOM uint32_t SHA_H5H; /* Offset: 0x03c (R/W) H5H register */
  211. __IOM uint32_t SHA_H6H; /* Offset: 0x040 (R/W) H6H register */
  212. __IOM uint32_t SHA_H7H; /* Offset: 0x044 (R/W) H7H register */
  213. __IOM uint32_t SHA_DATA1; /* Offset: 0x048 (R/W) DATA1 register */
  214. uint32_t REV[15];
  215. __IOM uint32_t SHA_DATA2; /* Offset: 0x088 (R/W) DATA2 register */
  216. } CSKY_SHA_TypeDef;
  217. #endif
  218. #define CONFIG_CRC_NUM 1
  219. #define CONFIG_IIC_NUM 2
  220. #define CONFIG_TRNG_NUM 1
  221. #define CONFIG_EFLASH_NUM 1
  222. #define CONFIG_AES_NUM 1
  223. #define CONFIG_RSA_NUM 1
  224. #define CONFIG_SHA_NUM 1
  225. #define CONFIG_SPI_NUM 2
  226. #define CONFIG_PWM_NUM 1
  227. #define CONFIG_TIMER_NUM 4
  228. #define CONFIG_RTC_NUM 1
  229. #define CONFIG_WDT_NUM 1
  230. #define CONFIG_DMAC_NUM 1
  231. #define CONFIG_ETH_NUM 2
  232. #define CSKY_I2C0_BASE (0x50014000UL)
  233. #define CSKY_I2C1_BASE (0x60014000UL)
  234. #define CONFIG_USART_NUM 4
  235. #define CSKY_UART0_BASE (0x50010000UL)
  236. #define CSKY_UART1_BASE (0x50010400UL)
  237. #define CSKY_UART2_BASE (0x60010000UL)
  238. #define CSKY_UART3_BASE (0x60010400UL)
  239. /* ================================================================================ */
  240. /* ================ Peripheral memory map ================ */
  241. /* ================================================================================ */
  242. /* -------------------------- CPU FPGA memory map ------------------------------- */
  243. #define CSKY_EFLASH_BASE (0x10000000UL)
  244. #define CSKY_SRAM_BASE (0x20000000UL)
  245. #define CSKY_PMU_BASE (0x40000000UL)
  246. #define CSKY_DMA_BASE (0x40001000UL)
  247. #define CSKY_EFLASH_CONTROL_BASE (0x40005000UL)
  248. #define CSKY_OTP_BASE (0x40006000UL)
  249. #define CSKY_SRAM_CONTROL_BASE (0x40009000UL)
  250. #define CSKY_AES_BASE (0x4000d000UL)
  251. #define CSKY_SHA_BASE (0x4000e000UL)
  252. #define CSKY_RSA_BASE (0x4000f000UL)
  253. #define CSKY_CRC_BASE (0x40010000UL)
  254. #define CSKY_TRNG_BASE (0x40015000UL)
  255. #define CSKY_TIMERA0_BASE (0x50000000UL)
  256. #define CSKY_TIMERA1_BASE (0x50000014UL)
  257. #define CSKY_TIMERA_CONTROL_BASE (0x500000a0UL)
  258. #define CSKY_RTC_BASE (0x50004000UL)
  259. #define CSKY_WDT_BASE (0x50008000UL)
  260. #define CSKY_SPI0_BASE (0x5000c000UL)
  261. #define CONFIG_GPIO_NUM 2
  262. #define CONFIG_GPIO_PIN_NUM 43
  263. #define CSKY_GPIOA_BASE (0x50018000UL)
  264. #define CSKY_GPIOA_CONTROL_BASE (0x50018030UL)
  265. #define CSKY_PWM_BASE (0x5001c000UL)
  266. #define CSKY_ADC_BASE (0x50020000UL)
  267. #define CSKY_I2S0_BASE (0x50030000UL)
  268. #define CSKY_TIMERB0_BASE (0x60000000UL)
  269. #define CSKY_TIMERB1_BASE (0x60000014UL)
  270. #define CSKY_SPI1_BASE (0x6000c000UL)
  271. #define CSKY_GPIOB_BASE (0x60018000UL)
  272. #define CSKY_GPIOB_CONTROL_BASE (0x60018030UL)
  273. #define CSKY_TIMERB_CONTROL_BASE (0x600000a0UL)
  274. #define CSKY_SIPC_BASE (0x6001c000UL)
  275. #define CSKY_I2S1_BASE (0x60020000UL)
  276. #define CSKY_ETB_BASE (0x60024000UL)
  277. #define CSKY_USI_BASE (0x60028000UL)
  278. /* ================================================================================ */
  279. /* ================ Peripheral declaration ================ */
  280. /* ================================================================================ */
  281. #define CSKY_UART1 (( CSKY_UART_TypeDef *) CSKY_UART1_BASE)
  282. #define CSKY_SHA (( CSKY_SHA_TypeDef *) CSKY_SHA_BASE)
  283. #ifdef __cplusplus
  284. }
  285. #endif
  286. #endif /* SOC_H */