drv_uart.c 27 KB

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  1. /*
  2. * Copyright (c) 2019-2020, Xim
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. */
  7. #include <rthw.h>
  8. #include <rtdevice.h>
  9. #include "board.h"
  10. #include "drv_uart.h"
  11. #include <stdio.h>
  12. #define DBG_TAG "DRV.UART"
  13. #define DBG_LVL DBG_WARNING
  14. #include <rtdbg.h>
  15. #include <hal_clk.h>
  16. #include <hal_reset.h>
  17. #include <hal_gpio.h>
  18. #define UART_DEFAULT_BAUDRATE 500000
  19. #ifdef UART0_TX_USING_GPIOB8
  20. #define UART0_TX GPIOB(8)
  21. #define UART0_TX_FUNCTION 6
  22. #elif defined(UART0_TX_USING_GPIOE2)
  23. #define UART0_TX GPIOE(2)
  24. #define UART0_TX_FUNCTION 6
  25. #elif defined(UART0_TX_USING_GPIOF2)
  26. #define UART0_TX GPIOF(2)
  27. #define UART0_TX_FUNCTION 3
  28. #endif
  29. #ifdef UART0_RX_USING_GPIOB9
  30. #define UART0_RX GPIOB(9)
  31. #define UART0_RX_FUNCTION 6
  32. #elif defined(UART0_RX_USING_GPIOE3)
  33. #define UART0_RX GPIOE(3)
  34. #define UART0_RX_FUNCTION 6
  35. #elif defined(UART0_RX_USING_GPIOF4)
  36. #define UART0_RX GPIOF(4)
  37. #define UART0_RX_FUNCTION 3
  38. #endif
  39. #ifdef UART1_TX_USING_GPIOD21
  40. #define UART1_TX GPIOD(21)
  41. #define UART1_TX_FUNCTION 4
  42. #elif defined(UART1_TX_USING_GPIOE10)
  43. #define UART1_TX GPIOE(10)
  44. #define UART1_TX_FUNCTION 3
  45. #elif defined(UART1_TX_USING_GPIOG6)
  46. #define UART1_TX GPIOG(6)
  47. #define UART1_TX_FUNCTION 3
  48. #elif defined(UART1_TX_USING_GPIOG12)
  49. #define UART1_TX GPIOG(12)
  50. #define UART1_TX_FUNCTION 7
  51. #endif
  52. #ifdef UART1_RX_USING_GPIOD22
  53. #define UART1_RX GPIOD(22)
  54. #define UART1_RX_FUNCTION 4
  55. #elif defined(UART1_RX_USING_GPIOE11)
  56. #define UART1_RX GPIOE(11)
  57. #define UART1_RX_FUNCTION 3
  58. #elif defined(UART1_RX_USING_GPIOG7)
  59. #define UART1_RX GPIOG(7)
  60. #define UART1_RX_FUNCTION 3
  61. #elif defined(UART1_RX_USING_GPIOG13)
  62. #define UART1_RX GPIOG(13)
  63. #define UART1_RX_FUNCTION 7
  64. #endif
  65. #ifdef UART2_TX_USING_GPIOD1
  66. #define UART2_TX GPIOD(1)
  67. #define UART2_TX_FUNCTION 5
  68. #elif defined(UART2_TX_USING_GPIOE2)
  69. #define UART2_TX GPIOE(2)
  70. #define UART2_TX_FUNCTION 3
  71. #endif
  72. #ifdef UART2_RX_USING_GPIOD2
  73. #define UART2_RX GPIOD(2)
  74. #define UART2_RX_FUNCTION 5
  75. #elif defined(UART2_RX_USING_GPIOE3)
  76. #define UART2_RX GPIOE(3)
  77. #define UART2_RX_FUNCTION 3
  78. #endif
  79. #ifdef UART3_TX_USING_GPIOB6
  80. #define UART3_TX GPIOB(6)
  81. #define UART3_TX_FUNCTION 7
  82. #elif defined(UART3_TX_USING_GPIOC6)
  83. #define UART3_TX GPIOC(6)
  84. #define UART3_TX_FUNCTION 4
  85. #elif defined(UART3_TX_USING_GPIOD10)
  86. #define UART3_TX GPIOD(10)
  87. #define UART3_TX_FUNCTION 5
  88. #elif defined(UART3_TX_USING_GPIOE8)
  89. #define UART3_TX GPIOE(8)
  90. #define UART3_TX_FUNCTION 5
  91. #elif defined(UART3_TX_USING_GPIOG0)
  92. #define UART3_TX GPIOG(0)
  93. #define UART3_TX_FUNCTION 3
  94. #elif defined(UART3_TX_USING_GPIOG8)
  95. #define UART3_TX GPIOG(8)
  96. #define UART3_TX_FUNCTION 5
  97. #endif
  98. #ifdef UART3_RX_USING_GPIOB7
  99. #define UART3_RX GPIOB(7)
  100. #define UART3_RX_FUNCTION 7
  101. #elif defined(UART3_RX_USING_GPIOC7)
  102. #define UART3_RX GPIOC(7)
  103. #define UART3_RX_FUNCTION 4
  104. #elif defined(UART3_RX_USING_GPIOD11)
  105. #define UART3_RX GPIOD(11)
  106. #define UART3_RX_FUNCTION 5
  107. #elif defined(UART3_RX_USING_GPIOE9)
  108. #define UART3_RX GPIOE(9)
  109. #define UART3_RX_FUNCTION 5
  110. #elif defined(UART3_RX_USING_GPIOG1)
  111. #define UART3_RX GPIOG(1)
  112. #define UART3_RX_FUNCTION 3
  113. #elif defined(UART3_RX_USING_GPIOG9)
  114. #define UART3_RX GPIOG(9)
  115. #define UART3_RX_FUNCTION 5
  116. #endif
  117. #ifdef UART4_TX_USING_GPIOB2
  118. #define UART4_TX GPIOB(2)
  119. #define UART4_TX_FUNCTION 7
  120. #elif defined(UART4_TX_USING_GPIOD7)
  121. #define UART4_TX GPIOD(7)
  122. #define UART4_TX_FUNCTION 5
  123. #elif defined(UART4_TX_USING_GPIOE4)
  124. #define UART4_TX GPIOE(4)
  125. #define UART4_TX_FUNCTION 3
  126. #elif defined(UART4_TX_USING_GPIOG2)
  127. #define UART4_TX GPIOG(2)
  128. #define UART4_TX_FUNCTION 5
  129. #endif
  130. #ifdef UART4_RX_USING_GPIOB3
  131. #define UART4_RX GPIOB(3)
  132. #define UART4_RX_FUNCTION 7
  133. #elif defined(UART4_RX_USING_GPIOD8)
  134. #define UART4_RX GPIOD(8)
  135. #define UART4_RX_FUNCTION 5
  136. #elif defined(UART4_RX_USING_GPIOE5)
  137. #define UART4_RX GPIOE(5)
  138. #define UART4_RX_FUNCTION 3
  139. #elif defined(UART4_TX_USING_GPIOG3)
  140. #define UART4_RX GPIOG(3)
  141. #define UART4_RX_FUNCTION 5
  142. #endif
  143. #ifdef UART5_TX_USING_GPIOB4
  144. #define UART5_TX GPIOB(4)
  145. #define UART5_TX_FUNCTION 7
  146. #elif defined(UART5_TX_USING_GPIOD5)
  147. #define UART5_TX GPIOD(5)
  148. #define UART5_TX_FUNCTION 5
  149. #elif defined(UART5_TX_USING_GPIOE6)
  150. #define UART5_TX GPIOE(6)
  151. #define UART5_TX_FUNCTION 3
  152. #elif defined(UART5_TX_USING_GPIOG4)
  153. #define UART5_TX GPIOG(4)
  154. #define UART5_TX_FUNCTION 3
  155. #endif
  156. #ifdef UART5_RX_USING_GPIOB5
  157. #define UART5_RX GPIOB(5)
  158. #define UART5_RX_FUNCTION 7
  159. #elif defined(UART5_RX_USING_GPIOD6)
  160. #define UART5_RX GPIOD(6)
  161. #define UART5_RX_FUNCTION 5
  162. #elif defined(UART5_RX_USING_GPIOE7)
  163. #define UART5_RX GPIOE(7)
  164. #define UART5_RX_FUNCTION 3
  165. #elif defined(UART5_RX_USING_GPIOG5)
  166. #define UART5_RX GPIOG(5)
  167. #define UART5_RX_FUNCTION 3
  168. #endif
  169. #define SUNXI_CLK_UART0 CLK_BUS_UART0;
  170. #define SUNXI_RST_UART0 RST_BUS_UART0;
  171. #define SUNXI_CLK_UART1 CLK_BUS_UART1;
  172. #define SUNXI_RST_UART1 RST_BUS_UART1;
  173. #define SUNXI_CLK_UART2 CLK_BUS_UART2;
  174. #define SUNXI_RST_UART2 RST_BUS_UART2;
  175. #define SUNXI_CLK_UART3 CLK_BUS_UART3;
  176. #define SUNXI_RST_UART3 RST_BUS_UART3;
  177. #define SUNXI_CLK_UART4 CLK_BUS_UART4;
  178. #define SUNXI_RST_UART4 RST_BUS_UART4;
  179. #define SUNXI_CLK_UART5 CLK_BUS_UART5;
  180. #define SUNXI_RST_UART5 RST_BUS_UART5;
  181. #define SUNXI_IRQ_UART0 (18)
  182. #define SUNXI_IRQ_UART1 (19)
  183. #define SUNXI_IRQ_UART2 (20)
  184. #define SUNXI_IRQ_UART3 (21)
  185. #define SUNXI_IRQ_UART4 (22)
  186. #define SUNXI_IRQ_UART5 (23)
  187. #define SUNXI_UART0_BASE (0x02500000)
  188. #define SUNXI_UART1_BASE (0x02500400)
  189. #define SUNXI_UART2_BASE (0x02500800)
  190. #define SUNXI_UART3_BASE (0x02500c00)
  191. #define SUNXI_UART4_BASE (0x02501000)
  192. #define SUNXI_UART5_BASE (0x02501400)
  193. /*
  194. * Register definitions for UART
  195. */
  196. #define UART_RHB (0x00)
  197. #define UART_RBR (0x00) /* receive buffer register */
  198. #define UART_THR (0x00) /* transmit holding register */
  199. #define UART_DLL (0x00) /* divisor latch low register */
  200. #define UART_DLH (0x04) /* diviso latch high register */
  201. #define UART_IER (0x04) /* interrupt enable register */
  202. #define UART_IIR (0x08) /* interrupt identity register */
  203. #define UART_FCR (0x08) /* FIFO control register */
  204. #define UART_LCR (0x0c) /* line control register */
  205. #define UART_MCR (0x10) /* modem control register */
  206. #define UART_LSR (0x14) /* line status register */
  207. #define UART_MSR (0x18) /* modem status register */
  208. #define UART_SCH (0x1c) /* scratch register */
  209. #define UART_USR (0x7c) /* status register */
  210. #define UART_TFL (0x80) /* transmit FIFO level */
  211. #define UART_RFL (0x84) /* RFL */
  212. #define UART_HALT (0xa4) /* halt tx register */
  213. #define UART_RS485 (0xc0) /* RS485 control and status register */
  214. /*
  215. * register bit field define
  216. */
  217. /* Interrupt Enable Register */
  218. #define UART_IER_MASK (0xff)
  219. #define UART_IER_PTIME (BIT(7))
  220. #define UART_IER_RS485 (BIT(4))
  221. #define UART_IER_MSI (BIT(3))
  222. #define UART_IER_RLSI (BIT(2))
  223. #define UART_IER_THRI (BIT(1))
  224. #define UART_IER_RDI (BIT(0))
  225. /* Interrupt ID Register */
  226. #define UART_IIR_FEFLAG_MASK (BIT(6) | BIT(7))
  227. #define UART_IIR_IID_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  228. #define UART_IIR_IID_MSTA (0)
  229. #define UART_IIR_IID_NOIRQ (1)
  230. #define UART_IIR_IID_THREMP (2)
  231. #define UART_IIR_IID_RXDVAL (4)
  232. #define UART_IIR_IID_LINESTA (6)
  233. #define UART_IIR_IID_BUSBSY (7)
  234. #define UART_IIR_IID_CHARTO (12)
  235. /* FIFO Control Register */
  236. #define UART_FCR_RXTRG_MASK (BIT(6) | BIT(7))
  237. #define UART_FCR_RXTRG_1CH (0 << 6)
  238. #define UART_FCR_RXTRG_1_4 (1 << 6)
  239. #define UART_FCR_RXTRG_1_2 (2 << 6)
  240. #define UART_FCR_RXTRG_FULL (3 << 6)
  241. #define UART_FCR_TXTRG_MASK (BIT(4) | BIT(5))
  242. #define UART_FCR_TXTRG_EMP (0 << 4)
  243. #define UART_FCR_TXTRG_2CH (1 << 4)
  244. #define UART_FCR_TXTRG_1_4 (2 << 4)
  245. #define UART_FCR_TXTRG_1_2 (3 << 4)
  246. #define UART_FCR_TXFIFO_RST (BIT(2))
  247. #define UART_FCR_RXFIFO_RST (BIT(1))
  248. #define UART_FCR_FIFO_EN (BIT(0))
  249. /* Line Control Register */
  250. #define UART_LCR_DLAB (BIT(7))
  251. #define UART_LCR_SBC (BIT(6))
  252. #define UART_LCR_PARITY_MASK (BIT(5) | BIT(4))
  253. #define UART_LCR_EPAR (1 << 4)
  254. #define UART_LCR_OPAR (0 << 4)
  255. #define UART_LCR_PARITY (BIT(3))
  256. #define UART_LCR_STOP (BIT(2))
  257. #define UART_LCR_DLEN_MASK (BIT(1) | BIT(0))
  258. #define UART_LCR_WLEN5 (0)
  259. #define UART_LCR_WLEN6 (1)
  260. #define UART_LCR_WLEN7 (2)
  261. #define UART_LCR_WLEN8 (3)
  262. /* Modem Control Register */
  263. #define UART_MCR_MODE_MASK (BIT(7) | BIT(6))
  264. #define UART_MCR_MODE_RS485 (2 << 6)
  265. #define UART_MCR_MODE_SIRE (1 << 6)
  266. #define UART_MCR_MODE_UART (0 << 6)
  267. #define UART_MCR_AFE (BIT(5))
  268. #define UART_MCR_LOOP (BIT(4))
  269. #define UART_MCR_RTS (BIT(1))
  270. #define UART_MCR_DTR (BIT(0))
  271. /* Line Status Rigster */
  272. #define UART_LSR_RXFIFOE (BIT(7))
  273. #define UART_LSR_TEMT (BIT(6))
  274. #define UART_LSR_THRE (BIT(5))
  275. #define UART_LSR_BI (BIT(4))
  276. #define UART_LSR_FE (BIT(3))
  277. #define UART_LSR_PE (BIT(2))
  278. #define UART_LSR_OE (BIT(1))
  279. #define UART_LSR_DR (BIT(0))
  280. #define UART_LSR_BRK_ERROR_BITS (0x1E) /* BI, FE, PE, OE bits */
  281. /* Modem Status Register */
  282. #define UART_MSR_DCD (BIT(7))
  283. #define UART_MSR_RI (BIT(6))
  284. #define UART_MSR_DSR (BIT(5))
  285. #define UART_MSR_CTS (BIT(4))
  286. #define UART_MSR_DDCD (BIT(3))
  287. #define UART_MSR_TERI (BIT(2))
  288. #define UART_MSR_DDSR (BIT(1))
  289. #define UART_MSR_DCTS (BIT(0))
  290. #define UART_MSR_ANY_DELTA (0x0F)
  291. #define MSR_SAVE_FLAGS (UART_MSR_ANY_DELTA)
  292. /* Status Register */
  293. #define UART_USR_RFF (BIT(4))
  294. #define UART_USR_RFNE (BIT(3))
  295. #define UART_USR_TFE (BIT(2))
  296. #define UART_USR_TFNF (BIT(1))
  297. #define UART_USR_BUSY (BIT(0))
  298. /* Halt Register */
  299. #define UART_HALT_LCRUP (BIT(2))
  300. #define UART_HALT_FORCECFG (BIT(1))
  301. #define UART_HALT_HTX (BIT(0))
  302. /* RS485 Control and Status Register */
  303. #define UART_RS485_RXBFA (BIT(3))
  304. #define UART_RS485_RXAFA (BIT(2))
  305. typedef enum
  306. {
  307. UART_0 = 0,
  308. UART_1,
  309. UART_2,
  310. UART_3,
  311. UART_4,
  312. UART_5,
  313. UART_MAX,
  314. } uart_port_t;
  315. /* This enum defines word length of the UART frame. */
  316. typedef enum
  317. {
  318. UART_WORD_LENGTH_5 = 0,
  319. UART_WORD_LENGTH_6,
  320. UART_WORD_LENGTH_7,
  321. UART_WORD_LENGTH_8,
  322. } uart_word_length_t;
  323. /* This enum defines stop bit of the UART frame. */
  324. typedef enum
  325. {
  326. UART_STOP_BIT_1 = 0,
  327. UART_STOP_BIT_2,
  328. } uart_stop_bit_t;
  329. /* This enum defines parity of the UART frame. */
  330. typedef enum
  331. {
  332. UART_PARITY_NONE = 0,
  333. UART_PARITY_ODD,
  334. UART_PARITY_EVEN
  335. } uart_parity_t;
  336. struct sunxi_uart
  337. {
  338. uart_port_t uart_port;
  339. uint32_t irqno;
  340. rt_uint16_t uart_dma_flag;
  341. struct rt_completion tx_fifo_empty;
  342. };
  343. static const size_t _uart_base[] =
  344. {
  345. SUNXI_UART0_BASE, SUNXI_UART1_BASE, SUNXI_UART2_BASE, SUNXI_UART3_BASE, SUNXI_UART4_BASE, SUNXI_UART5_BASE};
  346. static const uint32_t _uart_irqn[] =
  347. {
  348. SUNXI_IRQ_UART0, SUNXI_IRQ_UART1, SUNXI_IRQ_UART2, SUNXI_IRQ_UART3, SUNXI_IRQ_UART4, SUNXI_IRQ_UART5};
  349. static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
  350. static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg);
  351. static int _uart_putc(struct rt_serial_device *serial, char c);
  352. static int _uart_getc(struct rt_serial_device *serial);
  353. static rt_ssize_t _uart_transmit(struct rt_serial_device *serial,
  354. rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag);
  355. const struct rt_uart_ops _uart_ops =
  356. {
  357. _uart_configure,
  358. _uart_control,
  359. _uart_putc,
  360. _uart_getc,
  361. _uart_transmit};
  362. #ifdef BSP_USING_UART0
  363. struct rt_serial_device serial0;
  364. struct sunxi_uart uart0 = {
  365. .uart_port = UART_0,
  366. .irqno = SUNXI_IRQ_UART0};
  367. #endif
  368. #ifdef BSP_USING_UART1
  369. struct rt_serial_device serial1;
  370. struct sunxi_uart uart1 = {
  371. .uart_port = UART_1,
  372. .irqno = SUNXI_IRQ_UART1};
  373. #endif
  374. #ifdef BSP_USING_UART2
  375. struct rt_serial_device serial2;
  376. struct sunxi_uart uart2 = {
  377. .uart_port = UART_2,
  378. .irqno = SUNXI_IRQ_UART2};
  379. #endif
  380. #ifdef BSP_USING_UART3
  381. struct rt_serial_device serial3;
  382. struct sunxi_uart uart3 = {
  383. .uart_port = UART_3,
  384. .irqno = SUNXI_IRQ_UART3};
  385. #endif
  386. #ifdef BSP_USING_UART4
  387. struct rt_serial_device serial4;
  388. struct sunxi_uart uart4 = {
  389. .uart_port = UART_4,
  390. .irqno = SUNXI_IRQ_UART4};
  391. #endif
  392. #ifdef BSP_USING_UART5
  393. struct rt_serial_device serial5;
  394. struct sunxi_uart uart5 = {
  395. .uart_port = UART_5,
  396. .irqno = SUNXI_IRQ_UART5};
  397. #endif
  398. static void uart_set_baudrate(uart_port_t uart_port, uint32_t baudrate)
  399. {
  400. size_t uart_base;
  401. uint32_t quot, uart_clk;
  402. uint8_t lcr;
  403. uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
  404. uart_clk = 24000000; /* FIXME: fixed to 24MHz */
  405. quot = (uart_clk + 8 * baudrate) / (16 * baudrate);
  406. lcr = hal_readb(uart_base + UART_LCR);
  407. /* hold tx so that uart will update lcr and baud in the gap of tx */
  408. hal_writeb(UART_HALT_HTX | UART_HALT_FORCECFG, uart_base + UART_HALT);
  409. hal_writeb(lcr | UART_LCR_DLAB, uart_base + UART_LCR);
  410. hal_writeb(quot >> 8, uart_base + UART_DLH);
  411. hal_writeb(quot & 0xFFu, uart_base + UART_DLL);
  412. hal_writeb(UART_HALT_HTX | UART_HALT_FORCECFG | UART_HALT_LCRUP, uart_base + UART_HALT);
  413. /* FIXME: implement timeout */
  414. while (hal_readb(uart_base + UART_HALT) & UART_HALT_LCRUP)
  415. ;
  416. /* In fact there are two DLABs(DLAB and DLAB_BAK) in the hardware implementation.
  417. * The DLAB_BAK is sellected only when SW_UART_HALT_FORCECFG is set to 1,
  418. * and this bit can be access no matter uart is busy or not.
  419. * So we select the DLAB_BAK always by leaving SW_UART_HALT_FORCECFG to be 1. */
  420. hal_writeb(lcr, uart_base + UART_LCR);
  421. hal_writeb(UART_HALT_FORCECFG, uart_base + UART_HALT);
  422. }
  423. static void uart_set_format(uart_port_t uart_port, uint8_t data_bits, uint8_t stop_bits, uint8_t parity)
  424. {
  425. size_t uart_base;
  426. uint8_t lcr;
  427. uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
  428. lcr = hal_readb(uart_base + UART_LCR);
  429. /* set word length */
  430. lcr &= ~(UART_LCR_DLEN_MASK);
  431. switch (data_bits)
  432. {
  433. case 5:
  434. lcr |= UART_LCR_WLEN5;
  435. break;
  436. case 6:
  437. lcr |= UART_LCR_WLEN6;
  438. break;
  439. case 7:
  440. lcr |= UART_LCR_WLEN7;
  441. break;
  442. case 8:
  443. default:
  444. lcr |= UART_LCR_WLEN8;
  445. break;
  446. }
  447. /* set stop bit */
  448. switch (stop_bits)
  449. {
  450. case 1:
  451. default:
  452. lcr &= ~(UART_LCR_STOP);
  453. break;
  454. case 2:
  455. lcr |= UART_LCR_STOP;
  456. break;
  457. }
  458. /* set parity bit */
  459. lcr &= ~(UART_LCR_PARITY_MASK);
  460. switch (parity)
  461. {
  462. case PARITY_NONE:
  463. lcr &= ~(UART_LCR_PARITY);
  464. break;
  465. case PARITY_ODD:
  466. lcr |= UART_LCR_PARITY;
  467. break;
  468. case PARITY_EVEN:
  469. lcr |= UART_LCR_PARITY;
  470. lcr |= UART_LCR_EPAR;
  471. break;
  472. }
  473. hal_writeb(lcr, uart_base + UART_LCR);
  474. }
  475. static void uart_set_fifo(uart_port_t uart_port)
  476. {
  477. size_t uart_base;
  478. uint8_t fcr;
  479. uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
  480. fcr = UART_FCR_RXTRG_1_2 | UART_FCR_TXTRG_EMP | UART_FCR_FIFO_EN;
  481. hal_writeb(fcr, uart_base + UART_FCR);
  482. }
  483. static void uart_forcechange(uart_port_t uart_port)
  484. {
  485. size_t uart_base;
  486. uint32_t value;
  487. uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
  488. value = hal_readb(uart_base + UART_HALT);
  489. value |= UART_HALT_FORCECFG;
  490. hal_writeb(value, uart_base + UART_HALT);
  491. }
  492. static void uart_set_isr(uart_port_t uart_port, uint8_t enable, uint32_t irq_type)
  493. {
  494. size_t uart_base;
  495. uint32_t value;
  496. uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
  497. value = hal_readb(uart_base + UART_IER);
  498. if (enable)
  499. {
  500. value |= irq_type;
  501. }
  502. else
  503. {
  504. value &= ~irq_type;
  505. }
  506. hal_writeb(value, uart_base + UART_IER);
  507. }
  508. /*
  509. * UART interface
  510. */
  511. static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  512. {
  513. struct sunxi_uart *uart;
  514. RT_ASSERT(serial != RT_NULL);
  515. serial->config = *cfg;
  516. uart = serial->parent.user_data;
  517. uart_set_format(uart->uart_port, cfg->data_bits, cfg->stop_bits, cfg->parity);
  518. uart_set_baudrate(uart->uart_port, cfg->baud_rate);
  519. uart_set_fifo(uart->uart_port);
  520. uart_forcechange(uart->uart_port);
  521. return RT_EOK;
  522. }
  523. static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  524. {
  525. struct sunxi_uart *uart;
  526. rt_uint32_t channel = 1;
  527. #ifdef RT_USING_SERIAL_V2
  528. rt_ubase_t ctrl_flag = 0;
  529. rt_ubase_t ctrl_arg;
  530. #endif
  531. uart = serial->parent.user_data;
  532. RT_ASSERT(uart != RT_NULL);
  533. RT_ASSERT(channel != 3);
  534. #ifdef RT_USING_SERIAL_V2
  535. ctrl_arg = (rt_ubase_t)arg;
  536. if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
  537. {
  538. ctrl_flag |= RT_DEVICE_FLAG_INT_RX;
  539. }
  540. else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
  541. {
  542. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  543. {
  544. ctrl_flag = RT_DEVICE_FLAG_DMA_TX;
  545. }
  546. else
  547. {
  548. ctrl_flag = RT_DEVICE_FLAG_INT_TX;
  549. }
  550. }
  551. #endif
  552. LOG_D("uart%d control cmd:%x, arg:%x\n", uart->uart_port, cmd, ctrl_arg);
  553. switch (cmd)
  554. {
  555. case RT_DEVICE_CTRL_CLR_INT:
  556. #ifdef RT_USING_SERIAL_V2
  557. if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
  558. #else
  559. if ((size_t)arg == RT_DEVICE_FLAG_INT_RX)
  560. #endif
  561. {
  562. uart_set_isr(uart->uart_port, 0, UART_IER_RDI | UART_IER_RLSI);
  563. }
  564. break;
  565. case RT_DEVICE_CTRL_SET_INT:
  566. #ifdef RT_USING_SERIAL_V2
  567. if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
  568. #else
  569. if ((size_t)arg == RT_DEVICE_FLAG_INT_RX)
  570. #endif
  571. {
  572. uart_set_isr(uart->uart_port, 1, UART_IER_RDI | UART_IER_RLSI);
  573. }
  574. break;
  575. #ifdef RT_USING_SERIAL_V2
  576. case RT_DEVICE_CTRL_CONFIG:
  577. if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
  578. {
  579. uart_set_isr(uart->uart_port, 1, UART_IER_RDI | UART_IER_RLSI);
  580. }
  581. break;
  582. case RT_DEVICE_CHECK_OPTMODE:
  583. if (ctrl_flag & RT_DEVICE_FLAG_DMA_TX)
  584. {
  585. return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
  586. }
  587. else
  588. {
  589. return RT_SERIAL_TX_BLOCKING_BUFFER;
  590. }
  591. #endif /* RT_USING_SERIAL_V2 */
  592. }
  593. return (RT_EOK);
  594. }
  595. static int _uart_putc(struct rt_serial_device *serial, char c)
  596. {
  597. struct sunxi_uart *uart;
  598. size_t uart_base;
  599. uart = serial->parent.user_data;
  600. uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400;
  601. /* FIFO status, contain valid data */
  602. while (!(hal_readl(uart_base + UART_USR) & UART_USR_TFNF))
  603. ;
  604. hal_writeb(c, uart_base + UART_THR);
  605. // wait TX FIFO and the TX shift Register are empty.
  606. while (!(hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT))
  607. ;
  608. return 1;
  609. }
  610. static int _uart_getc(struct rt_serial_device *serial)
  611. {
  612. struct sunxi_uart *uart;
  613. size_t uart_base;
  614. int data = -1;
  615. uart = serial->parent.user_data;
  616. uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400;
  617. while (!(hal_readl(uart_base + UART_RFL) & 0x1FFu))
  618. ;
  619. /* Receive Data Available */
  620. if (hal_readl(uart_base + UART_USR) & UART_USR_RFNE)
  621. {
  622. data = hal_readb(uart_base + UART_RBR);
  623. }
  624. return data;
  625. }
  626. static rt_ssize_t _uart_transmit(struct rt_serial_device *serial,
  627. rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag)
  628. {
  629. struct sunxi_uart *uart;
  630. size_t uart_base;
  631. uart = serial->parent.user_data;
  632. uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400;
  633. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  634. {
  635. uint32_t remain = size;
  636. while (remain)
  637. {
  638. uint32_t write_count = 0;
  639. while (remain && (hal_readl(uart_base + UART_USR) & UART_USR_TFNF))
  640. {
  641. rt_uint8_t c = *buf++;
  642. hal_writeb(c, uart_base + UART_THR);
  643. remain--;
  644. write_count++;
  645. }
  646. while (write_count)
  647. {
  648. if (hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT)
  649. {
  650. break;
  651. }
  652. rt_completion_init(&(uart->tx_fifo_empty));
  653. uart_set_isr(uart->uart_port, 1, UART_IER_THRI);
  654. rt_err_t result = rt_completion_wait(&(uart->tx_fifo_empty), 100); // TODO: timeout calc by baud-rate.
  655. if (result == RT_EOK)
  656. {
  657. break;
  658. }
  659. }
  660. }
  661. /* last byte, must wait TEMT(transmitter Empty). TODO: need delay? */
  662. while (1)
  663. {
  664. if (hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT)
  665. {
  666. break;
  667. }
  668. }
  669. {
  670. struct rt_serial_tx_fifo *tx_fifo = RT_NULL;
  671. tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx;
  672. tx_fifo->activated = RT_FALSE;
  673. rt_completion_done(&(tx_fifo->tx_cpt));
  674. }
  675. return size;
  676. }
  677. return 0;
  678. }
  679. /**
  680. * this function will called when uart interrupt occur!
  681. */
  682. static void uart_irq_handler(int vector, void *param)
  683. {
  684. size_t uart_base;
  685. uint32_t iir, lsr;
  686. struct rt_serial_device *serial;
  687. struct sunxi_uart *uart;
  688. LOG_D("serial3:%p, uart3:%p\n", &serial3, &uart3);
  689. serial = (struct rt_serial_device *)param;
  690. uart = (struct sunxi_uart *)serial->parent.user_data;
  691. LOG_D("isr serial:%p, uart:%p, name:%s\n", serial, uart, serial->parent.parent.name);
  692. uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400;
  693. iir = hal_readb(uart_base + UART_IIR) & UART_IIR_IID_MASK;
  694. lsr = hal_readb(uart_base + UART_LSR);
  695. LOG_D("IRQ uart%d lsr is %08x \n", uart->uart_port, lsr);
  696. if (iir == UART_IIR_IID_BUSBSY)
  697. {
  698. (void)hal_readb(uart_base + UART_USR);
  699. /*
  700. * Before reseting lcr, we should ensure than uart is not in busy
  701. * state. Otherwise, a new busy interrupt will be introduced.
  702. * It is wise to set uart into loopback mode, since it can cut down the
  703. * serial in, then we should reset fifo(in my test, busy state
  704. * (UART_USR_BUSY) can't be cleard until the fifo is empty).
  705. */
  706. hal_writeb(hal_readb(uart_base + UART_MCR) | UART_MCR_LOOP, uart_base + UART_MCR);
  707. hal_writeb(UART_FCR_FIFO_EN, uart_base + UART_FCR);
  708. hal_writeb(UART_FCR_TXFIFO_RST | UART_FCR_RXFIFO_RST | UART_FCR_FIFO_EN, uart_base + UART_FCR);
  709. hal_writeb(0, uart_base + UART_FCR);
  710. uart_set_fifo(uart->uart_port);
  711. (void)hal_readb(uart_base + UART_FCR);
  712. hal_writeb(hal_readb(uart_base + UART_MCR) & ~UART_MCR_LOOP, uart_base + UART_MCR); /* exit loopback mode. */
  713. }
  714. else
  715. {
  716. if (lsr & (UART_LSR_DR | UART_LSR_BI))
  717. {
  718. #ifdef RT_USING_SERIAL_V2
  719. struct rt_serial_rx_fifo *rx_fifo;
  720. uint8_t data;
  721. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  722. RT_ASSERT(rx_fifo != RT_NULL);
  723. do
  724. {
  725. data = hal_readb(uart_base + UART_RBR);
  726. rt_ringbuffer_putchar(&(rx_fifo->rb), data);
  727. lsr = hal_readb(uart_base + UART_LSR);
  728. } while (lsr & UART_LSR_DR);
  729. #endif
  730. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  731. }
  732. else if (iir & UART_IIR_IID_CHARTO)
  733. /* has charto irq but no dr lsr? just read and ignore */
  734. {
  735. hal_readb(uart_base + UART_RBR);
  736. }
  737. /* if (lsr & UART_LSR_THRE)
  738. {
  739. uart_handle_tx(uart_port);
  740. }*/
  741. }
  742. if (iir == UART_IIR_IID_THREMP)
  743. {
  744. uart_set_isr(uart->uart_port, 0, UART_IER_THRI);
  745. rt_completion_done(&(uart->tx_fifo_empty));
  746. }
  747. }
  748. static int uart_clk_init(int bus, uint8_t enable)
  749. {
  750. hal_clk_status_t ret;
  751. hal_reset_type_t reset_type = HAL_SUNXI_RESET;
  752. u32 reset_id;
  753. hal_clk_type_t clk_type = HAL_SUNXI_CCU;
  754. hal_clk_id_t clk_id;
  755. hal_clk_t clk;
  756. struct reset_control *reset;
  757. switch (bus)
  758. {
  759. case 0:
  760. clk_id = SUNXI_CLK_UART0;
  761. reset_id = SUNXI_RST_UART0;
  762. break;
  763. case 1:
  764. clk_id = SUNXI_CLK_UART1;
  765. reset_id = SUNXI_RST_UART1;
  766. break;
  767. case 2:
  768. clk_id = SUNXI_CLK_UART2;
  769. reset_id = SUNXI_RST_UART2;
  770. break;
  771. case 3:
  772. clk_id = SUNXI_CLK_UART3;
  773. reset_id = SUNXI_RST_UART3;
  774. break;
  775. case 4:
  776. clk_id = SUNXI_CLK_UART4;
  777. reset_id = SUNXI_RST_UART4;
  778. break;
  779. case 5:
  780. clk_id = SUNXI_CLK_UART5;
  781. reset_id = SUNXI_RST_UART5;
  782. break;
  783. default:
  784. LOG_E("uart%d is invalid\n", bus);
  785. return -1;
  786. }
  787. if (enable)
  788. {
  789. reset = hal_reset_control_get(reset_type, reset_id);
  790. hal_reset_control_deassert(reset);
  791. hal_reset_control_put(reset);
  792. clk = hal_clock_get(clk_type, clk_id);
  793. ret = hal_clock_enable(clk);
  794. if (ret)
  795. {
  796. LOG_E("[uart%d] couldn't enable clk!\n", bus);
  797. return -1;
  798. }
  799. }
  800. else
  801. {
  802. clk = hal_clock_get(clk_type, clk_id);
  803. ret = hal_clock_disable(clk);
  804. if (ret)
  805. {
  806. LOG_E("[uart%d] couldn't disable clk!\n", bus);
  807. return -1;
  808. }
  809. }
  810. return 0;
  811. }
  812. static void uart_pinctrl_init(uart_port_t uart_port)
  813. {
  814. switch (uart_port)
  815. {
  816. #ifdef BSP_USING_UART0
  817. case UART_0:
  818. hal_gpio_set_pull(UART0_RX, GPIO_PULL_UP);
  819. hal_gpio_pinmux_set_function(UART0_TX, UART0_TX_FUNCTION); // TX
  820. hal_gpio_pinmux_set_function(UART0_RX, UART0_RX_FUNCTION); // RX
  821. break;
  822. #endif
  823. #ifdef BSP_USING_UART1
  824. case UART_1:
  825. hal_gpio_set_pull(UART1_RX, GPIO_PULL_UP);
  826. hal_gpio_pinmux_set_function(UART1_TX, UART1_TX_FUNCTION); // TX
  827. hal_gpio_pinmux_set_function(UART1_RX, UART1_RX_FUNCTION); // RX
  828. break;
  829. #endif
  830. #ifdef BSP_USING_UART2
  831. case UART_2:
  832. hal_gpio_set_pull(UART2_RX, GPIO_PULL_UP);
  833. hal_gpio_pinmux_set_function(UART2_TX, UART2_TX_FUNCTION); // TX
  834. hal_gpio_pinmux_set_function(UART2_RX, UART2_RX_FUNCTION); // RX
  835. break;
  836. #endif
  837. #ifdef BSP_USING_UART3
  838. case UART_3:
  839. hal_gpio_set_pull(UART3_RX, GPIO_PULL_UP);
  840. hal_gpio_pinmux_set_function(UART3_TX, UART3_TX_FUNCTION); // TX
  841. hal_gpio_pinmux_set_function(UART3_RX, UART3_RX_FUNCTION); // RX
  842. break;
  843. #endif
  844. #ifdef BSP_USING_UART4
  845. case UART_4:
  846. hal_gpio_set_pull(UART4_RX, GPIO_PULL_UP);
  847. hal_gpio_pinmux_set_function(UART4_TX, UART4_TX_FUNCTION); // TX
  848. hal_gpio_pinmux_set_function(UART4_RX, UART4_RX_FUNCTION); // RX
  849. break;
  850. #endif
  851. #ifdef BSP_USING_UART5
  852. case UART_5:
  853. hal_gpio_set_pull(UART5_RX, GPIO_PULL_UP);
  854. hal_gpio_pinmux_set_function(UART5_TX, UART5_TX_FUNCTION); // TX
  855. hal_gpio_pinmux_set_function(UART5_RX, UART5_RX_FUNCTION); // RX
  856. break;
  857. #endif
  858. default:
  859. LOG_E("[uart%d] not support \n", uart_port);
  860. break;
  861. }
  862. }
  863. static int uart_init(const char *name, struct sunxi_uart *uart, struct rt_serial_device *serial)
  864. {
  865. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  866. uart_clk_init(uart->uart_port, 1);
  867. uart_pinctrl_init(uart->uart_port);
  868. serial->ops = &_uart_ops;
  869. serial->config = config;
  870. serial->config.rx_bufsz = 256;
  871. serial->config.tx_bufsz = 0;
  872. serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
  873. if (strcmp(name, RT_CONSOLE_DEVICE_NAME) == 0)
  874. {
  875. uart->uart_dma_flag = 0;
  876. rt_hw_serial_register(serial, name, RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
  877. }
  878. else
  879. {
  880. uart->uart_dma_flag = RT_DEVICE_FLAG_DMA_TX;
  881. rt_hw_serial_register(serial, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
  882. }
  883. rt_hw_interrupt_install(uart->irqno, uart_irq_handler, serial, name);
  884. rt_hw_interrupt_umask(uart->irqno);
  885. return 0;
  886. }
  887. /*
  888. * UART Initiation
  889. */
  890. int rt_hw_uart_init(void)
  891. {
  892. #ifdef BSP_USING_UART0
  893. uart_init("uart0", &uart0, &serial0);
  894. #endif
  895. #ifdef BSP_USING_UART1
  896. uart_init("uart1", &uart1, &serial1);
  897. #endif
  898. #ifdef BSP_USING_UART2
  899. uart_init("uart2", &uart2, &serial2);
  900. #endif
  901. #ifdef BSP_USING_UART3
  902. uart_init("uart3", &uart3, &serial3);
  903. #endif
  904. #ifdef BSP_USING_UART4
  905. uart_init("uart4", &uart4, &serial4);
  906. #endif
  907. #ifdef BSP_USING_UART5
  908. uart_init("uart5", &uart5, &serial5);
  909. #endif
  910. return 0;
  911. }