sunxi_hal_geth.h 12 KB

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  1. /*
  2. * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
  3. *
  4. * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
  5. * the the People's Republic of China and other countries.
  6. * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
  7. *
  8. * DISCLAIMER
  9. * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
  10. * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
  11. * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
  12. * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
  13. * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
  14. * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
  15. * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
  16. *
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
  19. * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
  20. * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
  21. * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
  22. * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  23. * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  24. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  26. * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
  27. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  28. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  30. * OF THE POSSIBILITY OF SUCH DAMAGE.
  31. */
  32. #ifndef __SUNXI_HAL_GETH_H__
  33. #define __SUNXI_HAL_GETH_H__
  34. #ifdef __cplusplus
  35. extern "C"
  36. {
  37. #endif
  38. #include <rtthread.h>
  39. #include <netif/ethernetif.h>
  40. #include <sunxi_hal_common.h>
  41. #include <sunxi_hal_phy.h>
  42. #include <interrupt.h>
  43. #include <hal_gpio.h>
  44. #define CONFIG_DRIVERS_GETH_DEBUG
  45. #ifdef CONFIG_DRIVERS_GETH_DEBUG
  46. #define GETH_INFO(fmt, arg...) printf("GPIO : %s()%d "fmt, __func__, __LINE__, ##arg)
  47. #define GETH_ERR(fmt, arg...) printf("GPIO : %s()%d "fmt, __func__, __LINE__, ##arg)
  48. #else
  49. #define GETH_INFO(fmt, arg...) do {}while(0)
  50. #define GETH_ERR(fmt, arg...) do {}while(0)
  51. #endif
  52. /* Base config for geth */
  53. #define IOBASE 0x04500000
  54. #define PHY_CLK_REG (0x03000000 + 0x30)
  55. #define CCMU_BASE 0x02001000
  56. #define CCMU_GETH_CLK_REG 0x097c
  57. #define CCMU_GETH_RST_BIT 16
  58. #define CCMU_GETH_GATING_BIT 0
  59. #define CCMU_EPHY_CLK_REG 0x0970
  60. #define CCMU_EPHY_SCLK_GATING_BIT 31
  61. #define CCMU_EPHY_PLL_PERI0_GATING_BIT 30
  62. //#define DISABLE_AUTONEG
  63. #define CONFIG_HARD_CHECKSUM
  64. #define USE_EPHY25M
  65. #define GETH_IRQ_NUM 62
  66. /* Geth register list */
  67. #define GETH_BASIC_CTL0 0x00
  68. #define GETH_BASIC_CTL1 0x04
  69. #define GETH_INT_STA 0x08
  70. #define GETH_INT_EN 0x0C
  71. #define GETH_TX_CTL0 0x10
  72. #define GETH_TX_CTL1 0x14
  73. #define GETH_TX_FLOW_CTL 0x1C
  74. #define GETH_TX_DESC_LIST 0x20
  75. #define GETH_RX_CTL0 0x24
  76. #define GETH_RX_CTL1 0x28
  77. #define GETH_RX_DESC_LIST 0x34
  78. #define GETH_RX_FRM_FLT 0x38
  79. #define GETH_RX_HASH0 0x40
  80. #define GETH_RX_HASH1 0x44
  81. #define GETH_MDIO_ADDR 0x48
  82. #define GETH_MDIO_DATA 0x4C
  83. #define GETH_ADDR_HI(reg) (0x50 + ((reg) << 3))
  84. #define GETH_ADDR_LO(reg) (0x54 + ((reg) << 3))
  85. #define GETH_TX_DMA_STA 0xB0
  86. #define GETH_TX_CUR_DESC 0xB4
  87. #define GETH_TX_CUR_BUF 0xB8
  88. #define GETH_RX_DMA_STA 0xC0
  89. #define GETH_RX_CUR_DESC 0xC4
  90. #define GETH_RX_CUR_BUF 0xC8
  91. #define GETH_RGMII_STA 0xD0
  92. #define MII_BUSY 0x00000001
  93. #define MII_WRITE 0x00000002
  94. #define CTL0_DM 0x01
  95. #define CTL0_LM 0x02
  96. #define CTL0_SPEED 0x04
  97. #define BURST_LEN 0x3F000000
  98. #define RX_TX_PRI 0x02
  99. #define SOFT_RST 0x01
  100. #define TX_FLUSH 0x01
  101. #define TX_MD 0x02
  102. #define TX_NEXT_FRM 0x04
  103. #define TX_TH 0x0700
  104. #define RX_FLUSH 0x01
  105. #define RX_MD 0x02
  106. #define RX_RUNT_FRM 0x04
  107. #define RX_ERR_FRM 0x08
  108. #define RX_TH 0x0030
  109. #define STRIP_FCS 0x10000000
  110. #define TX_INT 0x00000001
  111. #define TX_STOP_INT 0x00000002
  112. #define TX_UA_INT 0x00000004
  113. #define TX_TOUT_INT 0x00000008
  114. #define TX_UNF_INT 0x00000010
  115. #define TX_EARLY_INT 0x00000020
  116. #define RX_INT 0x00000100
  117. #define RX_UA_INT 0x00000200
  118. #define RX_STOP_INT 0x00000400
  119. #define RX_TOUT_INT 0x00000800
  120. #define RX_OVF_INT 0x00001000
  121. #define RX_EARLY_INT 0x00002000
  122. #define LINK_STA_INT 0x00010000
  123. /* PHY address */
  124. #define PHY_DM 0x0010
  125. #define PHY_AUTO_NEG 0x0020
  126. #define PHY_POWERDOWN 0x0080
  127. #define PHY_NEG_EN 0x1000
  128. #define EXT_PHY 0
  129. #define INT_PHY 1
  130. #define MAX_ADDR_LEN 6
  131. #define ENET_FRAME_MAX_FRAMELEN 1518
  132. #define DMA_DESC_RX_NUM 64
  133. #define DMA_DESC_TX_NUM 64
  134. #define DMA_MEM_ALIGN_SIZE 2048
  135. #define SYS_PAGE_SIZE (4096U)
  136. #define TX_BUFFER_INDEX_NUM (6)
  137. #define RX_BUFFER_INDEX_NUM (6)
  138. #define TX_BD_INDEX_NUM (1)
  139. #define RX_BD_INDEX_NUM (1)
  140. #define PBUF_MAX_BUFF_SIZE 1514
  141. #define SZ_2K 0x00000800
  142. #define MAX_BUF_SZ (SZ_2K - 1)
  143. #define circ_inc(n, s) (((n) + 1) % (s))
  144. #define u8 uint8_t
  145. #define u16 uint16_t
  146. #define u32 uint32_t
  147. typedef enum rx_frame_status {
  148. good_frame = 0,
  149. discard_frame = 1,
  150. csum_none = 2,
  151. llc_snap = 4,
  152. } hal_geth_rx_frame_status_t;
  153. typedef union {
  154. struct {
  155. /* TDES0 */
  156. u32 deferred:1; /* Deferred bit (only half-duplex) */
  157. u32 under_err:1; /* Underflow error */
  158. u32 ex_deferral:1; /* Excessive deferral */
  159. u32 coll_cnt:4; /* Collision count */
  160. u32 vlan_tag:1; /* VLAN Frame */
  161. u32 ex_coll:1; /* Excessive collision */
  162. u32 late_coll:1; /* Late collision */
  163. u32 no_carr:1; /* No carrier */
  164. u32 loss_carr:1; /* Loss of collision */
  165. u32 ipdat_err:1; /* IP payload error */
  166. u32 frm_flu:1; /* Frame flushed */
  167. u32 jab_timeout:1; /* Jabber timeout */
  168. u32 err_sum:1; /* Error summary */
  169. u32 iphead_err:1; /* IP header error */
  170. u32 ttss:1; /* Transmit time stamp status */
  171. u32 reserved0:13;
  172. u32 own:1; /* Own bit. CPU:0, DMA:1 */
  173. } tx;
  174. struct {
  175. /* RDES0 */
  176. u32 chsum_err:1; /* Payload checksum error */
  177. u32 crc_err:1; /* CRC error */
  178. u32 dribbling:1; /* Dribble bit error */
  179. u32 mii_err:1; /* Received error (bit3) */
  180. u32 recv_wt:1; /* Received watchdog timeout */
  181. u32 frm_type:1; /* Frame type */
  182. u32 late_coll:1; /* Late Collision */
  183. u32 ipch_err:1; /* IPv header checksum error (bit7) */
  184. u32 last_desc:1; /* Laset descriptor */
  185. u32 first_desc:1; /* First descriptor */
  186. u32 vlan_tag:1; /* VLAN Tag */
  187. u32 over_err:1; /* Overflow error (bit11) */
  188. u32 len_err:1; /* Length error */
  189. u32 sou_filter:1; /* Source address filter fail */
  190. u32 desc_err:1; /* Descriptor error */
  191. u32 err_sum:1; /* Error summary (bit15) */
  192. u32 frm_len:14; /* Frame length */
  193. u32 des_filter:1; /* Destination address filter fail */
  194. u32 own:1; /* Own bit. CPU:0, DMA:1 */
  195. #define RX_PKT_OK 0x7FFFB77C
  196. #define RX_LEN 0x3FFF0000
  197. } rx;
  198. u32 all;
  199. } desc0_u;
  200. typedef union {
  201. struct {
  202. /* TDES1 */
  203. u32 buf1_size:11; /* Transmit buffer1 size */
  204. u32 buf2_size:11; /* Transmit buffer2 size */
  205. u32 ttse:1; /* Transmit time stamp enable */
  206. u32 dis_pad:1; /* Disable pad (bit23) */
  207. u32 adr_chain:1; /* Second address chained */
  208. u32 end_ring:1; /* Transmit end of ring */
  209. u32 crc_dis:1; /* Disable CRC */
  210. u32 cic:2; /* Checksum insertion control (bit27:28) */
  211. u32 first_sg:1; /* First Segment */
  212. u32 last_seg:1; /* Last Segment */
  213. u32 interrupt:1; /* Interrupt on completion */
  214. } tx;
  215. struct {
  216. /* RDES1 */
  217. u32 buf1_size:11; /* Received buffer1 size */
  218. u32 buf2_size:11; /* Received buffer2 size */
  219. u32 reserved1:2;
  220. u32 adr_chain:1; /* Second address chained */
  221. u32 end_ring:1; /* Received end of ring */
  222. u32 reserved2:5;
  223. u32 dis_ic:1; /* Disable interrupt on completion */
  224. } rx;
  225. u32 all;
  226. } desc1_u;
  227. typedef struct dma_desc {
  228. desc0_u desc0;
  229. desc1_u desc1;
  230. u32 desc2;
  231. u32 desc3;
  232. u32 resever0;
  233. u32 resever1;
  234. u32 resever2;
  235. u32 resever3;
  236. u32 resever4;
  237. u32 resever5;
  238. u32 resever6;
  239. u32 resever7;
  240. u32 resever8;
  241. u32 resever9;
  242. u32 resever10;
  243. u32 resever11;
  244. } hal_geth_dma_desc_t;
  245. typedef struct geth_buffer_config
  246. {
  247. hal_geth_dma_desc_t *dma_desc_tx;
  248. hal_geth_dma_desc_t *dma_desc_rx;
  249. hal_geth_dma_desc_t *phy_dma_desc_tx;
  250. hal_geth_dma_desc_t *phy_dma_desc_rx;
  251. void *tx_buff_addr;
  252. void *rx_buff_addr;
  253. void *phy_tx_buff_addr;
  254. void *phy_rx_buff_addr;
  255. } geth_buffer_config_t;
  256. struct geth_device {
  257. /* inherit from ethernet device */
  258. struct eth_device parent;
  259. /* interface address info, hw address */
  260. uint8_t dev_addr[MAX_ADDR_LEN];
  261. /* ethernet device base address */
  262. unsigned long iobase;
  263. /* phy mode */
  264. phy_interface_t phy_interface;
  265. rt_bool_t phy_link_status;
  266. geth_buffer_config_t get_buffer_config;
  267. uint32_t used_type;
  268. uint32_t tx_delay;
  269. uint32_t rx_delay;
  270. };
  271. typedef struct geth_priv {
  272. struct hal_gmac_dma_desc_t *dma_desc_tx;
  273. struct hal_gmac_dma_desc_t *dma_desc_rx;
  274. char *rx_handle_buf;
  275. int32_t base;
  276. int32_t phy_tpye;
  277. int32_t phy_interface;
  278. } hal_geth_priv_data_t;
  279. typedef struct sunxi_hal_driver_geth {
  280. rt_err_t (*initialize)(rt_device_t dev);
  281. void (*uninitialize)(rt_device_t dev);
  282. int32_t (*get_mac_address)(const unsigned char *addr);
  283. int32_t (*set_mac_address)(unsigned char *addr);
  284. int32_t (*set_address_filter)(void);
  285. rt_err_t (*send)(rt_device_t dev, struct pbuf *p);
  286. struct pbuf* (*recv)(rt_device_t dev);
  287. //int32_t (*phy_read)(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
  288. //int32_t (*phy_write)(uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
  289. } const sunxi_hal_driver_geth_t;
  290. void random_ether_addr(u8 *addr);
  291. void geth_set_link_mode(unsigned long iobase, int duplex, int speed);
  292. void geth_mac_loopback(unsigned long iobase, int enable);
  293. void geth_start_tx(unsigned long iobase);
  294. void geth_stop_tx(unsigned long iobase);
  295. void geth_start_rx(unsigned long iobase);
  296. void geth_stop_rx(unsigned long iobase);
  297. uint32_t geth_mac_reset(unsigned long iobase);
  298. void geth_mac_init(unsigned long iobase);
  299. void geth_set_filter(unsigned long iobase);
  300. void geth_set_mac_addr(unsigned long iobase, unsigned char *addr, int index);
  301. void geth_mac_enable(unsigned long iobase);
  302. void geth_mac_disable(unsigned long iobase);
  303. void geth_tx_poll(unsigned long iobase);
  304. void geth_rx_poll(unsigned long iobase);
  305. void geth_flush_tx(unsigned long iobase);
  306. void geth_rx_int_enable(unsigned long iobase);
  307. void geth_rx_int_disable(unsigned long iobase);
  308. void geth_tx_int_enable(unsigned long iobase);
  309. void geth_tx_int_disable(unsigned long iobase);
  310. void geth_all_int_disable(unsigned long iobase);
  311. void geth_clk_enable(uint32_t used_type,uint32_t phy_interface,uint32_t tx_delay,uint32_t rx_delay);
  312. void geth_clk_disable(void);
  313. uint32_t geth_mdio_read(unsigned long iobase, int phy_addr, u8 reg);
  314. uint32_t geth_mdio_write(unsigned long iobase, int phy_addr, u8 reg, u16 data);
  315. void rt_geth_driver_init(void);
  316. void geth_loopback_enable(unsigned long iobase);
  317. void geth_loopback_disable(unsigned long iobase);
  318. #ifdef __cplusplus
  319. }
  320. #endif
  321. #endif /* __SUNXI_HAL_GETH_H__ */