sunxi_hal_ir.h 3.4 KB

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  1. /*
  2. * ===========================================================================================
  3. *
  4. * Filename: sunxi_hal_spi.h
  5. *
  6. * Description: SPI HAL definition.
  7. *
  8. * Version: Melis3.0
  9. * Create: 2020-04-08 11:11:56
  10. * Revision: none
  11. * Compiler: GCC:version 9.2.1
  12. *
  13. * Author: bantao@allwinnertech.com
  14. * Organization: SWC-BPD
  15. * Last Modified: 2020-04-08 16:02:11
  16. *
  17. * ===========================================================================================
  18. */
  19. #ifndef SUNXI_IR_RX_H
  20. #define SUNXI_IR_RX_H
  21. #ifdef __cplusplus
  22. extern "C"
  23. {
  24. #endif
  25. #include "sunxi_hal_common.h"
  26. #include <hal_gpio.h>
  27. #include <hal_sem.h>
  28. #include <hal_clk.h>
  29. #define SUNXI_IRADC_PBASE 0X07040000 /* 0x34 */
  30. #define SUNXI_IRQ_IRADC 155
  31. #define IRADC_PIN GPIO_PH0
  32. #define IR_MUXSEL 4
  33. #define IR_DRVSEL 2
  34. /* Registers */
  35. #define IR_CTRL_REG (0x00) /* IR Control */
  36. #define IR_RXCFG_REG (0x10) /* Rx Config */
  37. #define IR_RXDAT_REG (0x20) /* Rx Data */
  38. #define IR_RXINTE_REG (0x2C) /* Rx Interrupt Enable */
  39. #define IR_RXINTS_REG (0x30) /* Rx Interrupt Status */
  40. #define IR_SPLCFG_REG (0x34) /* IR Sample Config */
  41. #define IR_FIFO_SIZE (64) /* 64Bytes */
  42. #define IR_SIMPLE_UNIT (21000) /* simple in ns */
  43. #define IR_CLK (24000000) /* 24Mhz */
  44. #define IR_SAMPLE_DEV (0x3<<0) /* 24MHz/512 =46875Hz (~21us) */
  45. /* Active Threshold (0+1)*128clock*21us = 2.6ms */
  46. #define IR_ACTIVE_T ((0&0xff)<<16)
  47. /* Filter Threshold = 16*21us = 336us < 500us */
  48. #define IR_RXFILT_VAL (((16)&0x3f)<<2)
  49. /* Filter Threshold = 22*21us = 336us < 500us */
  50. #define IR_RXFILT_VAL_RC5 (((22)&0x3f)<<2)
  51. /* Idle Threshold = (5+1)*128clock*21us = 16ms > 9ms */
  52. #define IR_RXIDLE_VAL (((5)&0xff)<<8)
  53. /* Active Threshold (0+1)*128clock*21us = 2.6ms */
  54. #define IR_ACTIVE_T_SAMPLE ((16&0xff)<<16)
  55. #define IR_ACTIVE_T_C (1<<23) /* Active Threshold */
  56. #define IR_CIR_MODE (0x3<<4) /* CIR mode enable */
  57. #define IR_ENTIRE_ENABLE (0x3<<0) /* IR entire enable */
  58. #define IR_FIFO_20 (((20)-1)<<8)
  59. #define IR_IRQ_STATUS ((0x1<<4)|0x3)
  60. #define IR_BOTH_PULSE (0x1 << 6)
  61. #define IR_LOW_PULSE (0x2 << 6)
  62. #define IR_HIGH_PULSE (0x3 << 6)
  63. /*Bit Definition of IR_RXINTS_REG Register*/
  64. #define IR_RXINTS_RXOF (0x1<<0) /* Rx FIFO Overflow */
  65. #define IR_RXINTS_RXPE (0x1<<1) /* Rx Packet End */
  66. #define IR_RXINTS_RXDA (0x1<<4) /* Rx FIFO Data Available */
  67. enum ir_mode {
  68. CIR_MODE_ENABLE,
  69. IR_MODULE_ENABLE,
  70. IR_BOTH_PULSE_MODE, /* new feature to avoid noisy */
  71. IR_LOW_PULSE_MODE,
  72. IR_HIGH_PULSE_MODE,
  73. };
  74. enum ir_sample_config {
  75. IR_SAMPLE_REG_CLEAR,
  76. IR_CLK_SAMPLE,
  77. IR_FILTER_TH_NEC,
  78. IR_FILTER_TH_RC5,
  79. IR_IDLE_TH,
  80. IR_ACTIVE_TH,
  81. IR_ACTIVE_TH_SAMPLE,
  82. };
  83. enum ir_irq_config {
  84. IR_IRQ_STATUS_CLEAR,
  85. IR_IRQ_ENABLE,
  86. IR_IRQ_FIFO_SIZE,
  87. };
  88. typedef enum
  89. {
  90. IR_PIN_ERR = -3,
  91. IR_CLK_ERR = -2,
  92. IR_IRQ_ERR = -1,
  93. IR_OK = 0,
  94. } hal_ir_status_t;
  95. typedef int (*ir_callback_t)(uint32_t data_type, uint32_t data);
  96. typedef struct sunxi_ir
  97. {
  98. uint16_t irq_num;
  99. uint32_t reg_base;
  100. gpio_pin_t pin;
  101. uint8_t pin_mux;
  102. uint8_t pin_drv;
  103. ir_callback_t callback;
  104. } hal_ir_t;
  105. int hal_ir_register_callback(ir_callback_t callback);
  106. int hal_ir_init(void);
  107. #ifdef __cplusplus
  108. }
  109. #endif
  110. #endif