sunxi_hal_spi.h 7.4 KB

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  1. /*
  2. * ===========================================================================================
  3. *
  4. * Filename: sunxi_hal_spi.h
  5. *
  6. * Description: SPI HAL definition.
  7. *
  8. * Version: Melis3.0
  9. * Create: 2019-11-18 11:11:56
  10. * Revision: none
  11. * Compiler: GCC:version 9.2.1
  12. *
  13. * Author: bantao@allwinnertech.com
  14. * Organization: SWC-BPD
  15. * Last Modified: 2019-12-03 16:02:11
  16. *
  17. * ===========================================================================================
  18. */
  19. #ifndef SUNXI_HAL_SPI_H
  20. #define SUNXI_HAL_SPI_H
  21. #ifdef __cplusplus
  22. extern "C"
  23. {
  24. #endif
  25. #include "sunxi_hal_common.h"
  26. #include <hal_gpio.h>
  27. #include <hal_dma.h>
  28. /* #include <sunxi_drv_spi.h> */
  29. #include <hal_sem.h>
  30. #include <hal_clk.h>
  31. #include <spi/platform_spi.h>
  32. #include <spi/common_spi.h>
  33. /*****************************************************************************
  34. * spi master
  35. *****************************************************************************/
  36. /** @brief This enum defines the SPI master port.
  37. * This chip total has 2 SPI master port
  38. */
  39. typedef enum
  40. {
  41. HAL_SPI_MASTER_0 = 0, /**< spi master port 0 */
  42. HAL_SPI_MASTER_1 = 1, /**< spi master port 1 */
  43. HAL_SPI_MASTER_2 = 2, /**< spi master port 1 */
  44. HAL_SPI_MASTER_MAX = SPI_MAX_NUM, /**< spi master max port number\<invalid\> */
  45. } hal_spi_master_port_t;
  46. typedef struct
  47. {
  48. const uint8_t *tx_buf; /**< Data buffer to send, */
  49. uint32_t tx_len; /**< The total number of bytes to send. */
  50. uint32_t
  51. tx_single_len; /**< The number of bytes to send in single mode. */
  52. uint8_t *rx_buf; /**< Received data buffer, */
  53. uint32_t rx_len; /**< The valid number of bytes received. */
  54. uint8_t tx_nbits : 3; /**< Data buffer to send in nbits mode */
  55. uint8_t rx_nbits : 3; /**< Data buffer to received in nbits mode */
  56. uint8_t dummy_byte; /**< Flash send dummy byte, default 0*/
  57. #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
  58. #define SPI_NBITS_DUAL 0x02 /* 2bit transfer */
  59. #define SPI_NBITS_QUAD 0x04 /* 4bit transfer */
  60. uint8_t bits_per_word; /**< transfer bit_per_word */
  61. } hal_spi_master_transfer_t;
  62. typedef enum spi_mode_type
  63. {
  64. SGLE_HALF_DUPLEX_RX, /* single mode, half duplex read */
  65. SGLE_HALF_DUPLEX_TX, /* single mode, half duplex write */
  66. DUAL_HALF_DUPLEX_RX, /* dual mode, half duplex read */
  67. DUAL_HALF_DUPLEX_TX, /* dual mode, half duplex write */
  68. QUAD_HALF_DUPLEX_RX, /* quad mode, half duplex read */
  69. QUAD_HALF_DUPLEX_TX, /* quad mode, half duplex write */
  70. FULL_DUPLEX_TX_RX, /* full duplex read and write */
  71. MODE_TYPE_NULL,
  72. } spi_mode_type_t;
  73. typedef struct spi_dma
  74. {
  75. struct dma_slave_config config;
  76. struct sunxi_dma_chan *chan;
  77. } spi_dma_t;
  78. typedef struct sunxi_spi
  79. {
  80. int8_t result : 2;
  81. #define SPI_XFER_READY 0
  82. #define SPI_XFER_OK 1
  83. #define SPI_XFER_FAILED -1
  84. bool sem;
  85. uint16_t irqnum;
  86. unsigned long base;
  87. spi_mode_type_t mode_type;
  88. hal_clk_t pclk; /* PLL clock */
  89. hal_clk_t bus_clk; /* BUS clock */
  90. hal_clk_t mclk; /* spi module clock */
  91. struct reset_control *reset;
  92. spi_dma_t dma_rx;
  93. spi_dma_t dma_tx;
  94. char *align_dma_buf;
  95. #define ALIGN_DMA_BUF_SIZE (4096 + 64)
  96. hal_sem_t xSemaphore_tx;
  97. hal_sem_t xSemaphore_rx;
  98. hal_spi_master_port_t port;
  99. hal_spi_master_transfer_t *transfer;
  100. } sunxi_spi_t;
  101. typedef enum
  102. {
  103. SPI_MASTER_ERROR = -6, /**< SPI master function error occurred. */
  104. SPI_MASTER_ERROR_NOMEM = -5, /**< SPI master request mem failed. */
  105. SPI_MASTER_ERROR_TIMEOUT = -4, /**< SPI master xfer timeout. */
  106. SPI_MASTER_ERROR_BUSY = -3, /**< SPI master is busy. */
  107. SPI_MASTER_ERROR_PORT = -2, /**< SPI master invalid port. */
  108. SPI_MASTER_INVALID_PARAMETER =
  109. -1, /**< SPI master invalid input parameter. */
  110. SPI_MASTER_OK = 0 /**< SPI master operation completed successfully. */
  111. } spi_master_status_t;
  112. /** @brief selection of spi slave device connected to which cs pin of spi master
  113. */
  114. typedef enum
  115. {
  116. HAL_SPI_MASTER_SLAVE_0 =
  117. 0, /**< spi slave device connect to spi master cs0 pin */
  118. HAL_SPI_MASTER_SLAVE_1 =
  119. 1, /**< spi slave device connect to spi master cs1 pin */
  120. HAL_SPI_MASTER_SLAVE_MAX /**< spi master max cs pin number\<invalid\> */
  121. } hal_spi_master_slave_port_t;
  122. /** @brief SPI master clock polarity definition */
  123. typedef enum
  124. {
  125. HAL_SPI_MASTER_CLOCK_POLARITY0 = 0, /**< Clock polarity is 0 */
  126. HAL_SPI_MASTER_CLOCK_POLARITY1 = 2 /**< Clock polarity is 1 */
  127. } hal_spi_master_clock_polarity_t;
  128. /** @brief SPI master clock format definition */
  129. typedef enum
  130. {
  131. HAL_SPI_MASTER_CLOCK_PHASE0 = 0, /**< Clock format is 0 */
  132. HAL_SPI_MASTER_CLOCK_PHASE1 = 1 /**< Clock format is 1 */
  133. } hal_spi_master_clock_phase_t;
  134. /** @brief SPI master transaction bit order definition */
  135. typedef enum
  136. {
  137. HAL_SPI_MASTER_MSB_FIRST =
  138. 0, /**< Both send and receive data transfer MSB first */
  139. HAL_SPI_MASTER_LSB_FIRST =
  140. 1 /**< Both send and receive data transfer LSB first */
  141. } hal_spi_master_bit_order_t;
  142. /** @brief SPI master status. */
  143. typedef enum
  144. {
  145. HAL_SPI_MASTER_STATUS_ERROR =
  146. -6, /**< SPI master function error occurred. */
  147. HAL_SPI_MASTER_STATUS_ERROR_NOMEM =
  148. -5, /**< SPI master request mem failed. */
  149. HAL_SPI_MASTER_STATUS_ERROR_TIMEOUT =
  150. -4, /**< SPI master xfer timeout. */
  151. HAL_SPI_MASTER_STATUS_ERROR_BUSY = -3, /**< SPI master is busy. */
  152. HAL_SPI_MASTER_STATUS_ERROR_PORT = -2, /**< SPI master invalid port. */
  153. HAL_SPI_MASTER_STATUS_INVALID_PARAMETER =
  154. -1, /**< SPI master invalid input parameter. */
  155. HAL_SPI_MASTER_STATUS_OK =
  156. 0 /**< SPI master operation completed successfully. */
  157. } hal_spi_master_status_t;
  158. /** @brief SPI master running status. */
  159. typedef enum
  160. {
  161. HAL_SPI_MASTER_BUSY = 0, /**< SPI master is busy. */
  162. HAL_SPI_MASTER_IDLE = 1 /**< SPI master is idle. */
  163. } hal_spi_master_running_status_t;
  164. typedef enum
  165. {
  166. HAL_SPI_MASTER_CS_AUTO = 0,
  167. HAL_SPI_MASTER_CS_SOFT = 1,
  168. } hal_spi_master_cs_mode_t;
  169. typedef struct
  170. {
  171. uint32_t clock_frequency; /**< SPI master clock frequency setting. */
  172. hal_spi_master_slave_port_t
  173. slave_port; /**< SPI slave device selection. */
  174. hal_spi_master_bit_order_t
  175. bit_order; /**< SPI master bit order setting. 0:MSB first 1:LSB
  176. first*/
  177. hal_spi_master_clock_polarity_t
  178. cpol; /**< SPI master clock polarity setting. 0:Active high
  179. polarity(0 = Idle) 1:Active low polarity(1 = Idle) */
  180. hal_spi_master_clock_phase_t
  181. cpha; /**< SPI master clock phase setting. 0: Phase 0(Leading edge
  182. for sample data) 1: Phase 1(Leading edge for setup data)
  183. */
  184. hal_spi_master_cs_mode_t csmode;
  185. } hal_spi_master_config_t;
  186. typedef enum
  187. {
  188. SPI_WRITE_READ = 0, /**< SPI master is busy. */
  189. SPI_CONFIG = 1 /**< SPI master is idle. */
  190. } hal_spi_transfer_cmd_t;
  191. spi_master_status_t hal_spi_init(hal_spi_master_port_t port, hal_spi_master_config_t *cfg);
  192. spi_master_status_t hal_spi_write(hal_spi_master_port_t port, const void *buf, uint32_t size);
  193. spi_master_status_t hal_spi_deinit(hal_spi_master_port_t port);
  194. spi_master_status_t hal_spi_read(hal_spi_master_port_t port, void *buf, uint32_t size);
  195. spi_master_status_t hal_spi_xfer(hal_spi_master_port_t port, hal_spi_master_transfer_t *transfer);
  196. spi_master_status_t hal_spi_hw_config(hal_spi_master_port_t port, hal_spi_master_config_t *spi_config);
  197. void hal_spi_cs(hal_spi_master_port_t port, uint8_t on_off);
  198. #endif