drv_gpio.c 2.2 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2023-10-25 Raman Gopalan Initial version
  9. * 2023-11-06 Raman Gopalan Abstraction for GPIO driver boilerplate
  10. */
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include "gpio.h"
  14. #include <rtdbg.h>
  15. #include "drv_gpio.h"
  16. #ifdef RT_USING_PIN
  17. static void at32uc3_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
  18. {
  19. RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
  20. /* Pointer to the register set for this GPIO port */
  21. volatile avr32_gpio_port_t *gpio_regs = &AVR32_GPIO.port[pin >> 5];
  22. /* Decide based on required mode */
  23. switch (mode)
  24. {
  25. case PIN_MODE_OUTPUT:
  26. gpio_regs->oders = 1 << (pin & 0x1F); /* Enable output driver */
  27. gpio_regs->gpers = 1 << (pin & 0x1F); /* Make GPIO control this pin */
  28. break;
  29. case PIN_MODE_INPUT:
  30. gpio_regs->oderc = 1 << (pin & 0x1F);
  31. gpio_regs->gpers = 1 << (pin & 0x1F);
  32. break;
  33. case PIN_MODE_INPUT_PULLUP:
  34. gpio_regs->puers = 1 << (pin & 0x1F);
  35. break;
  36. case PIN_MODE_INPUT_PULLDOWN:
  37. LOG_W("Pull-down enable register not defined for this SOC.");
  38. break;
  39. case PIN_MODE_OUTPUT_OD:
  40. LOG_W("The open-drain mode is not synthesized on the current AVR32 products.");
  41. break;
  42. }
  43. }
  44. static void at32uc3_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
  45. {
  46. RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
  47. if (value == PIN_HIGH)
  48. {
  49. gpio_set_gpio_pin(pin);
  50. }
  51. else
  52. {
  53. gpio_clr_gpio_pin(pin);
  54. }
  55. }
  56. static rt_int8_t at32uc3_pin_read(struct rt_device *device, rt_base_t pin)
  57. {
  58. RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
  59. return (gpio_get_pin_value(pin) ? PIN_HIGH : PIN_LOW);
  60. }
  61. static const struct rt_pin_ops ops =
  62. {
  63. at32uc3_pin_mode,
  64. at32uc3_pin_write,
  65. at32uc3_pin_read,
  66. RT_NULL,
  67. RT_NULL,
  68. RT_NULL,
  69. RT_NULL,
  70. };
  71. int rt_hw_gpio_init(void)
  72. {
  73. rt_device_pin_register("gpio", &ops, RT_NULL);
  74. return 0;
  75. }
  76. #endif /* RT_USING_PIN */