drv_uart_v2.c 42 KB

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  1. /*
  2. * Copyright (c) 2022-2023 HPMicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-03-08 HPMicro First version
  9. * 2022-07-28 HPMicro Fix compiling warning if RT_SERIAL_USING_DMA was not defined
  10. * 2022-08-08 HPMicro Integrate DMA Manager and support dynamic DMA resource assignment'
  11. * 2023-03-07 HPMicro Fix the issue that the data_width was not initialized before setup dma handshake
  12. *
  13. */
  14. #include <rtthread.h>
  15. #include <rtdevice.h>
  16. #include "board.h"
  17. #include "drv_uart_v2.h"
  18. #include "hpm_uart_drv.h"
  19. #include "hpm_sysctl_drv.h"
  20. #include "hpm_l1c_drv.h"
  21. #include "hpm_dma_drv.h"
  22. #include "hpm_dmamux_drv.h"
  23. #include "hpm_dma_manager.h"
  24. #include "hpm_soc.h"
  25. #ifdef RT_USING_SERIAL_V2
  26. #ifdef RT_SERIAL_USING_DMA
  27. #define BOARD_UART_DMAMUX HPM_DMAMUX
  28. #define UART_DMA_TRIGGER_LEVEL (1U)
  29. typedef struct dma_channel {
  30. struct rt_serial_device *serial;
  31. hpm_dma_resource_t resource;
  32. void (*tranfer_done)(struct rt_serial_device *serial);
  33. void (*tranfer_abort)(struct rt_serial_device *serial);
  34. void (*tranfer_error)(struct rt_serial_device *serial);
  35. } hpm_dma_channel_handle_t;
  36. //static struct dma_channel dma_channels[DMA_SOC_CHANNEL_NUM];
  37. static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg);
  38. #endif
  39. #define UART_ROOT_CLK_FREQ BOARD_APP_UART_SRC_FREQ
  40. struct hpm_uart {
  41. UART_Type *uart_base;
  42. uint32_t irq_num;
  43. struct rt_serial_device *serial;
  44. char *device_name;
  45. #ifdef RT_SERIAL_USING_DMA
  46. uint32_t tx_dma_mux;
  47. uint32_t rx_dma_mux;
  48. uint32_t dma_flags;
  49. hpm_dma_channel_handle_t tx_chn_ctx;
  50. hpm_dma_channel_handle_t rx_chn_ctx;
  51. bool tx_resource_allocated;
  52. bool rx_resource_allocated;
  53. #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA)
  54. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t rx_idle_tmp_buffer[1024];
  55. #endif
  56. #endif
  57. };
  58. extern void init_uart_pins(UART_Type *ptr);
  59. static void hpm_uart_isr(struct rt_serial_device *serial);
  60. static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
  61. static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg);
  62. static int hpm_uart_putc(struct rt_serial_device *serial, char ch);
  63. static int hpm_uart_getc(struct rt_serial_device *serial);
  64. #ifdef RT_SERIAL_USING_DMA
  65. int hpm_uart_dma_register_channel(struct rt_serial_device *serial,
  66. bool is_tx,
  67. void (*done)(struct rt_serial_device *serial),
  68. void (*abort)(struct rt_serial_device *serial),
  69. void (*error)(struct rt_serial_device *serial))
  70. {
  71. struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data;
  72. if (is_tx) {
  73. uart->tx_chn_ctx.serial = serial;
  74. uart->tx_chn_ctx.tranfer_done = done;
  75. uart->tx_chn_ctx.tranfer_abort = abort;
  76. uart->tx_chn_ctx.tranfer_error = error;
  77. } else {
  78. uart->rx_chn_ctx.serial = serial;
  79. uart->rx_chn_ctx.tranfer_done = done;
  80. uart->rx_chn_ctx.tranfer_abort = abort;
  81. uart->rx_chn_ctx.tranfer_error = error;
  82. }
  83. return RT_EOK;
  84. }
  85. #endif /* RT_SERIAL_USING_DMA */
  86. #if defined(BSP_USING_UART0)
  87. struct rt_serial_device serial0;
  88. void uart0_isr(void)
  89. {
  90. hpm_uart_isr(&serial0);
  91. }
  92. SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr)
  93. #endif
  94. #if defined(BSP_USING_UART1)
  95. struct rt_serial_device serial1;
  96. void uart1_isr(void)
  97. {
  98. hpm_uart_isr(&serial1);
  99. }
  100. SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr)
  101. #endif
  102. #if defined(BSP_USING_UART2)
  103. struct rt_serial_device serial2;
  104. void uart2_isr(void)
  105. {
  106. hpm_uart_isr(&serial2);
  107. }
  108. SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr)
  109. #endif
  110. #if defined(BSP_USING_UART3)
  111. struct rt_serial_device serial3;
  112. void uart3_isr(void)
  113. {
  114. hpm_uart_isr(&serial3);
  115. }
  116. SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr)
  117. #endif
  118. #if defined(BSP_USING_UART4)
  119. struct rt_serial_device serial4;
  120. void uart4_isr(void)
  121. {
  122. hpm_uart_isr(&serial4);
  123. }
  124. SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr)
  125. #endif
  126. #if defined(BSP_USING_UART5)
  127. struct rt_serial_device serial5;
  128. void uart5_isr(void)
  129. {
  130. hpm_uart_isr(&serial5);
  131. }
  132. SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr)
  133. #endif
  134. #if defined(BSP_USING_UART6)
  135. struct rt_serial_device serial6;
  136. void uart6_isr(void)
  137. {
  138. hpm_uart_isr(&serial6);
  139. }
  140. SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr)
  141. #endif
  142. #if defined(BSP_USING_UART7)
  143. struct rt_serial_device serial7;
  144. void uart7_isr(void)
  145. {
  146. hpm_uart_isr(&serial7);
  147. }
  148. SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr)
  149. #endif
  150. #if defined(BSP_USING_UART8)
  151. struct rt_serial_device serial8;
  152. void uart8_isr(void)
  153. {
  154. hpm_uart_isr(&serial8);
  155. }
  156. SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr)
  157. #endif
  158. #if defined(BSP_USING_UART9)
  159. struct rt_serial_device serial9;
  160. void uart9_isr(void)
  161. {
  162. hpm_uart_isr(&serial9);
  163. }
  164. SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr)
  165. #endif
  166. #if defined(BSP_USING_UART10)
  167. struct rt_serial_device serial10;
  168. void uart10_isr(void)
  169. {
  170. hpm_uart_isr(&serial10);
  171. }
  172. SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr)
  173. #endif
  174. #if defined(BSP_USING_UART11)
  175. struct rt_serial_device serial11;
  176. void uart11_isr(void)
  177. {
  178. hpm_uart_isr(&serial11);
  179. }
  180. SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr)
  181. #endif
  182. #if defined(BSP_USING_UART12)
  183. struct rt_serial_device serial12;
  184. void uart12_isr(void)
  185. {
  186. hpm_uart_isr(&serial12);
  187. }
  188. SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr)
  189. #endif
  190. #if defined(BSP_USING_UART13)
  191. struct rt_serial_device serial13;
  192. void uart13_isr(void)
  193. {
  194. hpm_uart_isr(&serial13);
  195. }
  196. SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr)
  197. #endif
  198. #if defined(BSP_USING_UART14)
  199. struct rt_serial_device serial14;
  200. void uart14_isr(void)
  201. {
  202. hpm_uart_isr(&serial14);
  203. }
  204. SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr)
  205. #endif
  206. #if defined(BSP_USING_UART15)
  207. struct rt_serial_device serial15;
  208. void uart15_isr(void)
  209. {
  210. hpm_uart_isr(&serial15);
  211. }
  212. SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr)
  213. #endif
  214. static struct hpm_uart uarts[] =
  215. {
  216. #if defined(BSP_USING_UART0)
  217. {
  218. HPM_UART0,
  219. IRQn_UART0,
  220. &serial0,
  221. "uart0",
  222. #ifdef RT_SERIAL_USING_DMA
  223. HPM_DMA_SRC_UART0_TX,
  224. HPM_DMA_SRC_UART0_RX,
  225. 0,
  226. #endif
  227. },
  228. #endif
  229. #if defined(BSP_USING_UART1)
  230. {
  231. HPM_UART1,
  232. IRQn_UART1,
  233. &serial1,
  234. "uart1",
  235. #ifdef RT_SERIAL_USING_DMA
  236. HPM_DMA_SRC_UART1_TX,
  237. HPM_DMA_SRC_UART1_RX,
  238. 0,
  239. #endif
  240. },
  241. #endif
  242. #if defined(BSP_USING_UART2)
  243. {
  244. HPM_UART2,
  245. IRQn_UART2,
  246. &serial2,
  247. "uart2",
  248. #ifdef RT_SERIAL_USING_DMA
  249. HPM_DMA_SRC_UART2_TX,
  250. HPM_DMA_SRC_UART2_RX,
  251. 0,
  252. #endif
  253. },
  254. #endif
  255. #if defined(BSP_USING_UART3)
  256. {
  257. HPM_UART3,
  258. IRQn_UART3,
  259. &serial3,
  260. "uart3",
  261. #ifdef RT_SERIAL_USING_DMA
  262. HPM_DMA_SRC_UART3_TX,
  263. HPM_DMA_SRC_UART3_RX,
  264. 0,
  265. #endif
  266. },
  267. #endif
  268. #if defined(BSP_USING_UART4)
  269. {
  270. HPM_UART4,
  271. IRQn_UART4,
  272. &serial4,
  273. "uart4",
  274. #ifdef RT_SERIAL_USING_DMA
  275. HPM_DMA_SRC_UART4_TX,
  276. HPM_DMA_SRC_UART4_RX,
  277. 0,
  278. #endif
  279. },
  280. #endif
  281. #if defined(BSP_USING_UART5)
  282. {
  283. HPM_UART5,
  284. IRQn_UART5,
  285. &serial5,
  286. "uart5",
  287. #ifdef RT_SERIAL_USING_DMA
  288. HPM_DMA_SRC_UART5_TX,
  289. HPM_DMA_SRC_UART5_RX,
  290. 0,
  291. #endif
  292. },
  293. #endif
  294. #if defined(BSP_USING_UART6)
  295. {
  296. HPM_UART6,
  297. IRQn_UART6,
  298. &serial6,
  299. "uart6",
  300. #ifdef RT_SERIAL_USING_DMA
  301. HPM_DMA_SRC_UART6_TX,
  302. HPM_DMA_SRC_UART6_RX,
  303. 0,
  304. #endif
  305. },
  306. #endif
  307. #if defined(BSP_USING_UART7)
  308. {
  309. HPM_UART7,
  310. IRQn_UART7,
  311. &serial7,
  312. "uart7",
  313. #ifdef RT_SERIAL_USING_DMA
  314. HPM_DMA_SRC_UART7_TX,
  315. HPM_DMA_SRC_UART7_RX,
  316. 0,
  317. #endif
  318. },
  319. #endif
  320. #if defined(BSP_USING_UART8)
  321. {
  322. HPM_UART8,
  323. IRQn_UART8,
  324. &serial8,
  325. "uart8",
  326. #ifdef RT_SERIAL_USING_DMA
  327. HPM_DMA_SRC_UART8_TX,
  328. HPM_DMA_SRC_UART8_RX,
  329. 0,
  330. #endif
  331. },
  332. #endif
  333. #if defined(BSP_USING_UART9)
  334. {
  335. HPM_UART9,
  336. IRQn_UART9,
  337. &serial9,
  338. "uart9",
  339. #ifdef RT_SERIAL_USING_DMA
  340. HPM_DMA_SRC_UART9_TX,
  341. HPM_DMA_SRC_UART9_RX,
  342. 0,
  343. #endif
  344. },
  345. #endif
  346. #if defined(BSP_USING_UART10)
  347. {
  348. HPM_UART10,
  349. IRQn_UART10,
  350. &serial10,
  351. "uart10",
  352. #ifdef RT_SERIAL_USING_DMA
  353. HPM_DMA_SRC_UART10_TX,
  354. HPM_DMA_SRC_UART10_RX,
  355. 0,
  356. #endif
  357. },
  358. #endif
  359. #if defined(BSP_USING_UART11)
  360. {
  361. HPM_UART11,
  362. IRQn_UART11,
  363. &serial11,
  364. "uart11",
  365. #ifdef RT_SERIAL_USING_DMA
  366. HPM_DMA_SRC_UART11_TX,
  367. HPM_DMA_SRC_UART11_RX,
  368. 0,
  369. #endif
  370. },
  371. #endif
  372. #if defined(BSP_USING_UART12)
  373. {
  374. HPM_UART12,
  375. IRQn_UART12,
  376. &serial12,
  377. "uart12",
  378. #ifdef RT_SERIAL_USING_DMA
  379. HPM_DMA_SRC_UART12_TX,
  380. HPM_DMA_SRC_UART12_RX,
  381. 0,
  382. #endif
  383. },
  384. #endif
  385. #if defined(BSP_USING_UART13)
  386. {
  387. HPM_UART13,
  388. IRQn_UART13,
  389. &serial13,
  390. "uart13",
  391. #ifdef RT_SERIAL_USING_DMA
  392. HPM_DMA_SRC_UART13_TX,
  393. HPM_DMA_SRC_UART13_RX,
  394. 0,
  395. #endif
  396. },
  397. #endif
  398. #if defined(BSP_USING_UART14)
  399. {
  400. HPM_UART14,
  401. IRQn_UART14,
  402. &serial14,
  403. "uart14",
  404. #ifdef RT_SERIAL_USING_DMA
  405. HPM_DMA_SRC_UART14_TX,
  406. HPM_DMA_SRC_UART14_RX,
  407. 0,
  408. #endif
  409. },
  410. #endif
  411. #if defined(BSP_USING_UART15)
  412. {
  413. HPM_UART15,
  414. IRQn_UART15,
  415. &serial15,
  416. "uart15",
  417. #ifdef RT_SERIAL_USING_DMA
  418. HPM_DMA_SRC_UART15_TX,
  419. HPM_DMA_SRC_UART15_RX,
  420. 0,
  421. #endif
  422. },
  423. #endif
  424. };
  425. enum
  426. {
  427. #if defined(BSP_USING_UART0)
  428. HPM_UART0_INDEX,
  429. #endif
  430. #if defined(BSP_USING_UART1)
  431. HPM_UART1_INDEX,
  432. #endif
  433. #if defined(BSP_USING_UART2)
  434. HPM_UART2_INDEX,
  435. #endif
  436. #if defined(BSP_USING_UART3)
  437. HPM_UART3_INDEX,
  438. #endif
  439. #if defined(BSP_USING_UART4)
  440. HPM_UART4_INDEX,
  441. #endif
  442. #if defined(BSP_USING_UART5)
  443. HPM_UART15_INDEX,
  444. #endif
  445. #if defined(BSP_USING_UART6)
  446. HPM_UART6_INDEX,
  447. #endif
  448. #if defined(BSP_USING_UART7)
  449. HPM_UART7_INDEX,
  450. #endif
  451. #if defined(BSP_USING_UART8)
  452. HPM_UART8_INDEX,
  453. #endif
  454. #if defined(BSP_USING_UART9)
  455. HPM_UART10_INDEX,
  456. #endif
  457. #if defined(BSP_USING_UART10)
  458. HPM_UART10_INDEX,
  459. #endif
  460. #if defined(BSP_USING_UART11)
  461. HPM_UART11_INDEX,
  462. #endif
  463. #if defined(BSP_USING_UART12)
  464. HPM_UART12_INDEX,
  465. #endif
  466. #if defined(BSP_USING_UART13)
  467. HPM_UART13_INDEX,
  468. #endif
  469. #if defined(BSP_USING_UART14)
  470. HPM_UART14_INDEX,
  471. #endif
  472. #if defined(BSP_USING_UART15)
  473. HPM_UART15_INDEX,
  474. #endif
  475. };
  476. #if defined(RT_SERIAL_USING_DMA)
  477. static void uart_dma_callback(DMA_Type *base, uint32_t channel, void *user_data, uint32_t int_stat)
  478. {
  479. hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data;
  480. if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel))
  481. {
  482. return;
  483. }
  484. if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_TC) && (dma_handle->tranfer_done != NULL))
  485. {
  486. dma_handle->tranfer_done(dma_handle->serial);
  487. }
  488. if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_ABORT) && (dma_handle->tranfer_abort != NULL))
  489. {
  490. dma_handle->tranfer_abort(dma_handle->serial);
  491. }
  492. if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_ERROR) && (dma_handle->tranfer_error != NULL))
  493. {
  494. dma_handle->tranfer_error(dma_handle->serial);
  495. }
  496. }
  497. static void uart_tx_done(struct rt_serial_device *serial)
  498. {
  499. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  500. }
  501. static void uart_rx_done(struct rt_serial_device *serial)
  502. {
  503. struct rt_serial_rx_fifo *rx_fifo;
  504. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  505. #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA)
  506. uint32_t uart_recv_data_count = 0;
  507. struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data;
  508. uint32_t rx_idle_tmp_buffer_size = sizeof(uart->rx_idle_tmp_buffer);
  509. uart_recv_data_count = rx_idle_tmp_buffer_size - dma_get_residue_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel);
  510. if (l1c_dc_is_enabled()) {
  511. uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)uart->rx_idle_tmp_buffer);
  512. uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)uart->rx_idle_tmp_buffer + rx_idle_tmp_buffer_size);
  513. uint32_t aligned_size = aligned_end - aligned_start;
  514. l1c_dc_invalidate(aligned_start, aligned_size);
  515. }
  516. rt_ringbuffer_put(&(rx_fifo->rb), uart->rx_idle_tmp_buffer, uart_recv_data_count);
  517. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE);
  518. #else
  519. if (l1c_dc_is_enabled()) {
  520. uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)rx_fifo->rb.buffer_ptr);
  521. uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)rx_fifo->rb.buffer_ptr + serial->config.rx_bufsz);
  522. uint32_t aligned_size = aligned_end - aligned_start;
  523. l1c_dc_invalidate(aligned_start, aligned_size);
  524. }
  525. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (serial->config.rx_bufsz << 8));
  526. #endif
  527. /* prepare for next read */
  528. hpm_uart_dma_config(serial, (void *)RT_DEVICE_FLAG_DMA_RX);
  529. }
  530. #endif /* RT_SERIAL_USING_DMA */
  531. /**
  532. * @brief UART common interrupt process. This
  533. *
  534. * @param serial Serial device
  535. */
  536. static void hpm_uart_isr(struct rt_serial_device *serial)
  537. {
  538. struct hpm_uart *uart;
  539. rt_uint32_t stat, enabled_irq;
  540. rt_uint8_t irq_id;
  541. rt_uint8_t count = 0;
  542. rt_uint8_t put_char = 0;
  543. RT_ASSERT(serial != RT_NULL);
  544. uart = (struct hpm_uart *)serial->parent.user_data;
  545. RT_ASSERT(uart != RT_NULL);
  546. struct rt_serial_rx_fifo *rx_fifo;
  547. rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
  548. /* enter interrupt */
  549. rt_interrupt_enter();
  550. stat = uart_get_status(uart->uart_base);
  551. enabled_irq = uart_get_enabled_irq(uart->uart_base);
  552. irq_id = uart_get_irq_id(uart->uart_base);
  553. if (irq_id == uart_intr_id_rx_data_avail) {
  554. while (uart_check_status(uart->uart_base, uart_stat_data_ready)) {
  555. count++;
  556. put_char = uart_read_byte(uart->uart_base);
  557. rt_ringbuffer_putchar(&(rx_fifo->rb), put_char);
  558. /*in order to ensure rx fifo there are remaining bytes*/
  559. if (count > 12) {
  560. break;
  561. }
  562. }
  563. }
  564. if (irq_id == uart_intr_id_rx_timeout) {
  565. while ((uart_check_status(uart->uart_base, uart_stat_data_ready)) || (uart_check_status(uart->uart_base, uart_stat_overrun_error))) {
  566. put_char= uart_read_byte(uart->uart_base);
  567. rt_ringbuffer_putchar(&(rx_fifo->rb), put_char);
  568. }
  569. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  570. }
  571. if ((enabled_irq & uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) {
  572. /* UART in mode Transmitter */
  573. struct rt_serial_tx_fifo *tx_fifo;
  574. tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx;
  575. RT_ASSERT(tx_fifo != RT_NULL);
  576. rt_uint8_t put_char = 0;
  577. uint32_t fifo_size = 0, ringbuffer_data_len = 0, tx_size = 0;
  578. uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail);
  579. fifo_size = uart_get_fifo_size(uart->uart_base);
  580. ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb);
  581. tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len;
  582. for (uint32_t i = 0; i < tx_size; i++) {
  583. rt_ringbuffer_getchar(&tx_fifo->rb, &put_char);
  584. uart_write_byte(uart->uart_base, put_char);
  585. }
  586. ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb);;
  587. if (ringbuffer_data_len) {
  588. uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail);
  589. } else {
  590. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  591. }
  592. }
  593. #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA)
  594. if (uart_is_rxline_idle(uart->uart_base)) {
  595. uart_rx_done(serial);
  596. uart_clear_rxline_idle_flag(uart->uart_base);
  597. uart_flush(uart->uart_base);
  598. }
  599. #endif
  600. /* leave interrupt */
  601. rt_interrupt_leave();
  602. }
  603. static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  604. {
  605. RT_ASSERT(serial != RT_NULL);
  606. RT_ASSERT(cfg != RT_NULL);
  607. uart_config_t uart_config;
  608. struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data;
  609. init_uart_pins(uart->uart_base);
  610. uart_default_config(uart->uart_base, &uart_config);
  611. uart_config.src_freq_in_hz = board_init_uart_clock(uart->uart_base);
  612. uart_config.baudrate = cfg->baud_rate;
  613. uart_config.num_of_stop_bits = cfg->stop_bits;
  614. uart_config.parity = cfg->parity;
  615. uart_config.rx_fifo_level = uart_rx_fifo_trg_gt_three_quarters;
  616. #ifdef RT_SERIAL_USING_DMA
  617. if (uart->dma_flags & (RT_DEVICE_FLAG_DMA_TX | RT_DEVICE_FLAG_DMA_RX)) {
  618. uart_config.fifo_enable = true;
  619. uart_config.dma_enable = true;
  620. if (uart->dma_flags & RT_DEVICE_FLAG_DMA_TX) {
  621. uart_config.tx_fifo_level = uart_tx_fifo_trg_not_full;
  622. }
  623. if (uart->dma_flags & RT_DEVICE_FLAG_DMA_RX) {
  624. uart_config.rx_fifo_level = uart_rx_fifo_trg_not_empty;
  625. }
  626. #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1)
  627. uart_config.rxidle_config.detect_enable = true;
  628. uart_config.rxidle_config.detect_irq_enable = true;
  629. uart_config.rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one;
  630. uart_config.rxidle_config.threshold = 10U; /* 10bit */
  631. #endif
  632. }
  633. #endif
  634. uart_config.word_length = cfg->data_bits - DATA_BITS_5;
  635. hpm_stat_t status = uart_init(uart->uart_base, &uart_config);
  636. return (status != status_success) ? -RT_ERROR : RT_EOK;
  637. }
  638. #ifdef RT_SERIAL_USING_DMA
  639. hpm_stat_t hpm_uart_dma_rx_init(struct hpm_uart *uart_ctx)
  640. {
  641. hpm_stat_t status = status_fail;
  642. if (!uart_ctx->rx_resource_allocated)
  643. {
  644. status = dma_manager_request_resource(&uart_ctx->rx_chn_ctx.resource);
  645. if (status == status_success)
  646. {
  647. uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_RX;
  648. uart_ctx->rx_resource_allocated = true;
  649. dma_manager_install_interrupt_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_callback, &uart_ctx->rx_chn_ctx);
  650. }
  651. }
  652. return status;
  653. }
  654. hpm_stat_t hpm_uart_dma_tx_init(struct hpm_uart *uart_ctx)
  655. {
  656. hpm_stat_t status = status_fail;
  657. if (!uart_ctx->tx_resource_allocated)
  658. {
  659. status = dma_manager_request_resource(&uart_ctx->tx_chn_ctx.resource);
  660. if (status == status_success)
  661. {
  662. uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_TX;
  663. uart_ctx->tx_resource_allocated = true;
  664. dma_manager_install_interrupt_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_callback, &uart_ctx->tx_chn_ctx);
  665. }
  666. }
  667. return status;
  668. }
  669. static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg)
  670. {
  671. rt_ubase_t ctrl_arg = (rt_ubase_t) arg;
  672. struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data;
  673. dma_handshake_config_t config;
  674. struct rt_serial_rx_fifo *rx_fifo;
  675. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) {
  676. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  677. config.ch_index = uart->rx_chn_ctx.resource.channel;
  678. #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1)
  679. config.dst = (uint32_t)uart->rx_idle_tmp_buffer;
  680. #else
  681. config.dst = (uint32_t) rx_fifo->rb.buffer_ptr;
  682. #endif
  683. config.dst_fixed = false;
  684. config.src = (uint32_t)&(uart->uart_base->RBR);
  685. config.src_fixed = true;
  686. config.data_width = DMA_TRANSFER_WIDTH_BYTE;
  687. #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1)
  688. config.size_in_byte = sizeof(uart->rx_idle_tmp_buffer);
  689. #else
  690. config.size_in_byte = serial->config.rx_bufsz;
  691. #endif
  692. if (status_success != dma_setup_handshake(uart->rx_chn_ctx.resource.base, &config, true)) {
  693. return RT_ERROR;
  694. }
  695. uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->rx_chn_ctx.resource.base, uart->rx_dma_mux);
  696. dmamux_config(BOARD_UART_DMAMUX, uart->rx_chn_ctx.resource.channel, mux, true);
  697. #if !defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) || (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 0)
  698. hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL);
  699. intc_m_enable_irq(uart->rx_chn_ctx.resource.irq_num);
  700. #else
  701. intc_m_enable_irq_with_priority(uart->irq_num, 1);
  702. #endif
  703. } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) {
  704. uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->tx_chn_ctx.resource.base, uart->tx_dma_mux);
  705. dmamux_config(BOARD_UART_DMAMUX, uart->tx_chn_ctx.resource.channel, mux, true);
  706. intc_m_enable_irq(uart->tx_chn_ctx.resource.irq_num);
  707. }
  708. return RT_EOK;
  709. }
  710. static void hpm_uart_transmit_dma(DMA_Type *dma, uint32_t ch_num, UART_Type *uart, uint8_t *src, uint32_t size)
  711. {
  712. rt_base_t align = 0;
  713. dma_handshake_config_t config;
  714. config.ch_index = ch_num;
  715. config.dst = (uint32_t)&uart->THR;
  716. config.dst_fixed = true;
  717. config.src = (uint32_t) src;
  718. config.src_fixed = false;
  719. config.size_in_byte = size;
  720. config.data_width = DMA_TRANSFER_WIDTH_BYTE;
  721. dma_setup_handshake(dma, &config, true);
  722. }
  723. #endif /* RT_SERIAL_USING_DMA */
  724. static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  725. {
  726. RT_ASSERT(serial != RT_NULL);
  727. rt_ubase_t ctrl_arg = (rt_ubase_t) arg;
  728. uint8_t *tmp_buffer = NULL;
  729. struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo*)serial->serial_rx;
  730. struct rt_serial_tx_fifo *tx_fifo = (struct rt_serial_tx_fifo*)serial->serial_tx;
  731. struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data;
  732. if(ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
  733. {
  734. #ifdef RT_SERIAL_USING_DMA
  735. if (uart->dma_flags & RT_DEVICE_FLAG_DMA_RX)
  736. {
  737. ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
  738. }
  739. else
  740. #endif
  741. {
  742. ctrl_arg = RT_DEVICE_FLAG_INT_RX;
  743. }
  744. }
  745. else if(ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
  746. {
  747. #ifdef RT_SERIAL_USING_DMA
  748. if (uart->dma_flags & RT_DEVICE_FLAG_DMA_TX)
  749. {
  750. ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
  751. }
  752. else
  753. #endif
  754. {
  755. ctrl_arg = RT_DEVICE_FLAG_INT_TX;
  756. }
  757. }
  758. switch (cmd) {
  759. case RT_DEVICE_CTRL_CLR_INT:
  760. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) {
  761. /* disable rx irq */
  762. uart_disable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout);
  763. intc_m_disable_irq(uart->irq_num);
  764. }
  765. else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) {
  766. /* disable tx irq */
  767. uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail);
  768. intc_m_disable_irq(uart->irq_num);
  769. }
  770. #ifdef RT_SERIAL_USING_DMA
  771. else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) {
  772. dma_manager_disable_channel_interrupt(&uart->tx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL);
  773. dma_abort_channel(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel);
  774. } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) {
  775. dma_manager_disable_channel_interrupt(&uart->rx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL);
  776. dma_abort_channel(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel);
  777. }
  778. #endif
  779. break;
  780. case RT_DEVICE_CTRL_SET_INT:
  781. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) {
  782. /* enable rx irq */
  783. uart_enable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout);
  784. intc_m_enable_irq_with_priority(uart->irq_num, 1);
  785. } else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) {
  786. /* enable tx irq */
  787. uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail);
  788. intc_m_enable_irq_with_priority(uart->irq_num, 1);
  789. }
  790. break;
  791. case RT_DEVICE_CTRL_CONFIG:
  792. #ifdef RT_SERIAL_USING_DMA
  793. if ((ctrl_arg == RT_DEVICE_FLAG_DMA_RX) || (ctrl_arg == RT_DEVICE_FLAG_INT_RX)) {
  794. if ((rx_fifo) && (((rt_uint32_t)rx_fifo->rb.buffer_ptr % HPM_L1C_CACHELINE_SIZE) || (rx_fifo->rb.buffer_size % HPM_L1C_CACHELINE_SIZE))) {
  795. rt_free(rx_fifo);
  796. rx_fifo = RT_NULL;
  797. rx_fifo = (struct rt_serial_rx_fifo *) rt_malloc(sizeof(struct rt_serial_rx_fifo));
  798. RT_ASSERT(rx_fifo != RT_NULL);
  799. tmp_buffer = rt_malloc(serial->config.rx_bufsz + HPM_L1C_CACHELINE_SIZE);
  800. RT_ASSERT(tmp_buffer != RT_NULL);
  801. tmp_buffer += (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE));
  802. rt_ringbuffer_init(&rx_fifo->rb, tmp_buffer, serial->config.rx_bufsz);
  803. rt_ringbuffer_reset(&rx_fifo->rb);
  804. serial->serial_rx = rx_fifo;
  805. }
  806. }
  807. if ((ctrl_arg == RT_DEVICE_FLAG_DMA_TX) || (ctrl_arg == RT_DEVICE_FLAG_INT_TX)) {
  808. if ((tx_fifo) && (((rt_uint32_t)tx_fifo->rb.buffer_ptr % HPM_L1C_CACHELINE_SIZE) || (tx_fifo->rb.buffer_size % HPM_L1C_CACHELINE_SIZE))) {
  809. rt_free(tx_fifo);
  810. tx_fifo = RT_NULL;
  811. tx_fifo = (struct rt_serial_tx_fifo *) rt_malloc(sizeof(struct rt_serial_tx_fifo));
  812. RT_ASSERT(tx_fifo != RT_NULL);
  813. tmp_buffer = rt_malloc(serial->config.tx_bufsz + HPM_L1C_CACHELINE_SIZE);
  814. RT_ASSERT(tmp_buffer != RT_NULL);
  815. tmp_buffer+= (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE));
  816. rt_ringbuffer_init(&tx_fifo->rb, tmp_buffer, serial->config.tx_bufsz);
  817. rt_ringbuffer_reset(&tx_fifo->rb);
  818. tx_fifo->activated = RT_FALSE;
  819. tx_fifo->put_size = 0;
  820. serial->serial_tx = tx_fifo;
  821. }
  822. }
  823. if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) {
  824. hpm_uart_dma_config(serial, (void *)ctrl_arg);
  825. } else
  826. #endif
  827. {
  828. hpm_uart_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg);
  829. }
  830. break;
  831. case RT_DEVICE_CHECK_OPTMODE:
  832. #ifdef RT_SERIAL_USING_DMA
  833. if ((ctrl_arg & RT_DEVICE_FLAG_DMA_TX)) {
  834. return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
  835. } else
  836. #endif
  837. {
  838. return RT_SERIAL_TX_BLOCKING_BUFFER;
  839. }
  840. }
  841. return RT_EOK;
  842. }
  843. static int hpm_uart_putc(struct rt_serial_device *serial, char ch)
  844. {
  845. struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data;
  846. uart_send_byte(uart->uart_base, ch);
  847. uart_flush(uart->uart_base);
  848. return ch;
  849. }
  850. static int hpm_uart_getc(struct rt_serial_device *serial)
  851. {
  852. int result = -1;
  853. struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data;
  854. if (uart_check_status(uart->uart_base, uart_stat_data_ready)) {
  855. uart_receive_byte(uart->uart_base, (uint8_t*)&result);
  856. }
  857. return result;
  858. }
  859. static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial,
  860. rt_uint8_t *buf,
  861. rt_size_t size,
  862. rt_uint32_t tx_flag)
  863. {
  864. RT_ASSERT(serial != RT_NULL);
  865. RT_ASSERT(buf != RT_NULL);
  866. RT_ASSERT(size);
  867. uint32_t fifo_size = 0, tx_size = 0;
  868. uint32_t ringbuffer_data_len = 0;
  869. struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data;
  870. struct rt_serial_tx_fifo *tx_fifo;
  871. tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx;
  872. uint8_t ch = 0;
  873. RT_ASSERT(tx_fifo != RT_NULL);
  874. #ifdef RT_SERIAL_USING_DMA
  875. if (uart->dma_flags & RT_DEVICE_FLAG_DMA_TX) {
  876. hpm_uart_dma_register_channel(serial, true, uart_tx_done, RT_NULL, RT_NULL);
  877. intc_m_enable_irq(uart->tx_chn_ctx.resource.irq_num);
  878. if (l1c_dc_is_enabled()) {
  879. uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)buf);
  880. uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)buf + size);
  881. uint32_t aligned_size = aligned_end - aligned_start;
  882. l1c_dc_flush(aligned_start, aligned_size);
  883. }
  884. hpm_uart_transmit_dma(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel, uart->uart_base, buf, size);
  885. return size;
  886. } else {
  887. #else
  888. {
  889. #endif
  890. if (size > 0) {
  891. if (uart_check_status(uart->uart_base, uart_stat_transmitter_empty)) {
  892. uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail);
  893. fifo_size = uart_get_fifo_size(uart->uart_base);
  894. ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb);
  895. tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len;
  896. for (uint32_t i = 0; i < tx_size; i++) {
  897. rt_ringbuffer_getchar(&tx_fifo->rb, &ch);
  898. uart_write_byte(uart->uart_base, ch);
  899. }
  900. if (rt_ringbuffer_data_len(&tx_fifo->rb)) {
  901. uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail);
  902. } else {
  903. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  904. }
  905. }
  906. }
  907. }
  908. return size;
  909. }
  910. static const struct rt_uart_ops hpm_uart_ops = {
  911. hpm_uart_configure,
  912. hpm_uart_control,
  913. hpm_uart_putc,
  914. hpm_uart_getc,
  915. hpm_uart_transmit,
  916. };
  917. static int hpm_uart_config(void)
  918. {
  919. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  920. hpm_stat_t status = status_success;
  921. #ifdef BSP_USING_UART0
  922. uarts[HPM_UART0_INDEX].serial->config = config;
  923. uarts[HPM_UART0_INDEX].serial->config.rx_bufsz = BSP_UART0_RX_BUFSIZE;
  924. uarts[HPM_UART0_INDEX].serial->config.tx_bufsz = BSP_UART0_TX_BUFSIZE;
  925. #ifdef RT_SERIAL_USING_DMA
  926. uarts[HPM_UART0_INDEX].dma_flags = 0;
  927. #ifdef BSP_UART0_RX_USING_DMA
  928. status = hpm_uart_dma_rx_init(&uarts[HPM_UART0_INDEX]);
  929. if (status != status_success)
  930. {
  931. return -RT_ERROR;
  932. }
  933. #endif //BSP_UART0_RX_USING_DMA
  934. #ifdef BSP_UART0_TX_USING_DMA
  935. status = hpm_uart_dma_tx_init(&uarts[HPM_UART0_INDEX]);
  936. if (status != status_success)
  937. {
  938. return -RT_ERROR;
  939. }
  940. #endif //BSP_UART0_TX_USING_DMA
  941. #endif // RT_SERIAL_USING_DMA
  942. #endif //BSP_USING_UART0
  943. #ifdef BSP_USING_UART1
  944. uarts[HPM_UART1_INDEX].serial->config = config;
  945. uarts[HPM_UART1_INDEX].serial->config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
  946. uarts[HPM_UART1_INDEX].serial->config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
  947. #ifdef RT_SERIAL_USING_DMA
  948. uarts[HPM_UART1_INDEX].dma_flags = 0;
  949. #ifdef BSP_UART1_RX_USING_DMA
  950. status = hpm_uart_dma_rx_init(&uarts[HPM_UART1_INDEX]);
  951. if (status != status_success)
  952. {
  953. return -RT_ERROR;
  954. }
  955. #endif //BSP_UART1_RX_USING_DMA
  956. #ifdef BSP_UART1_TX_USING_DMA
  957. status = hpm_uart_dma_tx_init(&uarts[HPM_UART1_INDEX]);
  958. if (status != status_success)
  959. {
  960. return -RT_ERROR;
  961. }
  962. #endif //BSP_UART1_TX_USING_DMA
  963. #endif // RT_SERIAL_USING_DMA
  964. #endif //BSP_USING_UART1
  965. #ifdef BSP_USING_UART2
  966. uarts[HPM_UART2_INDEX].serial->config = config;
  967. uarts[HPM_UART2_INDEX].serial->config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
  968. uarts[HPM_UART2_INDEX].serial->config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
  969. #ifdef RT_SERIAL_USING_DMA
  970. uarts[HPM_UART2_INDEX].dma_flags = 0;
  971. #ifdef BSP_UART2_RX_USING_DMA
  972. status = hpm_uart_dma_rx_init(&uarts[HPM_UART2_INDEX]);
  973. if (status != status_success)
  974. {
  975. return -RT_ERROR;
  976. }
  977. #endif //BSP_UART2_RX_USING_DMA
  978. #ifdef BSP_UART2_TX_USING_DMA
  979. status = hpm_uart_dma_tx_init(&uarts[HPM_UART2_INDEX]);
  980. if (status != status_success)
  981. {
  982. return -RT_ERROR;
  983. }
  984. #endif //BSP_UART2_TX_USING_DMA
  985. #endif // RT_SERIAL_USING_DMA
  986. #endif //BSP_USING_UART2
  987. #ifdef BSP_USING_UART3
  988. uarts[HPM_UART3_INDEX].serial->config = config;
  989. uarts[HPM_UART3_INDEX].serial->config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
  990. uarts[HPM_UART3_INDEX].serial->config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
  991. #ifdef RT_SERIAL_USING_DMA
  992. uarts[HPM_UART3_INDEX].dma_flags = 0;
  993. #ifdef BSP_UART3_RX_USING_DMA
  994. status = hpm_uart_dma_rx_init(&uarts[HPM_UART3_INDEX]);
  995. if (status != status_success)
  996. {
  997. return -RT_ERROR;
  998. }
  999. #endif //BSP_UART3_RX_USING_DMA
  1000. #ifdef BSP_UART3_TX_USING_DMA
  1001. status = hpm_uart_dma_tx_init(&uarts[HPM_UART3_INDEX]);
  1002. if (status != status_success)
  1003. {
  1004. return -RT_ERROR;
  1005. }
  1006. #endif //BSP_UART3_TX_USING_DMA
  1007. #endif // RT_SERIAL_USING_DMA
  1008. #endif //BSP_USING_UART3
  1009. #ifdef BSP_USING_UART4
  1010. uarts[HPM_UART4_INDEX].serial->config = config;
  1011. uarts[HPM_UART4_INDEX].serial->config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
  1012. uarts[HPM_UART4_INDEX].serial->config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
  1013. #ifdef RT_SERIAL_USING_DMA
  1014. uarts[HPM_UART4_INDEX].dma_flags = 0;
  1015. #ifdef BSP_UART4_RX_USING_DMA
  1016. status = hpm_uart_dma_rx_init(&uarts[HPM_UART4_INDEX]);
  1017. if (status != status_success)
  1018. {
  1019. return -RT_ERROR;
  1020. }
  1021. #endif //BSP_UART4_RX_USING_DMA
  1022. #ifdef BSP_UART4_TX_USING_DMA
  1023. status = hpm_uart_dma_tx_init(&uarts[HPM_UART4_INDEX]);
  1024. if (status != status_success)
  1025. {
  1026. return -RT_ERROR;
  1027. }
  1028. #endif //BSP_UART4_TX_USING_DMA
  1029. #endif // RT_SERIAL_USING_DMA
  1030. #endif //BSP_USING_UART4
  1031. #ifdef BSP_USING_UART5
  1032. uarts[HPM_UART5_INDEX].serial->config = config;
  1033. uarts[HPM_UART5_INDEX].serial->config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
  1034. uarts[HPM_UART5_INDEX].serial->config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
  1035. #ifdef RT_SERIAL_USING_DMA
  1036. uarts[HPM_UART5_INDEX].dma_flags = 0;
  1037. #ifdef BSP_UART5_RX_USING_DMA
  1038. status = hpm_uart_dma_rx_init(&uarts[HPM_UART5_INDEX]);
  1039. if (status != status_success)
  1040. {
  1041. return -RT_ERROR;
  1042. }
  1043. #endif //BSP_UART5_RX_USING_DMA
  1044. #ifdef BSP_UART5_TX_USING_DMA
  1045. status = hpm_uart_dma_tx_init(&uarts[HPM_UART5_INDEX]);
  1046. if (status != status_success)
  1047. {
  1048. return -RT_ERROR;
  1049. }
  1050. #endif //BSP_UART5_TX_USING_DMA
  1051. #endif // RT_SERIAL_USING_DMA
  1052. #endif //BSP_USING_UART5
  1053. #ifdef BSP_USING_UART6
  1054. uarts[HPM_UART6_INDEX].serial->config = config;
  1055. uarts[HPM_UART6_INDEX].serial->config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
  1056. uarts[HPM_UART6_INDEX].serial->config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
  1057. #ifdef RT_SERIAL_USING_DMA
  1058. uarts[HPM_UART6_INDEX].dma_flags = 0;
  1059. #ifdef BSP_UART6_RX_USING_DMA
  1060. status = hpm_uart_dma_rx_init(&uarts[HPM_UART6_INDEX]);
  1061. if (status != status_success)
  1062. {
  1063. return -RT_ERROR;
  1064. }
  1065. #endif //BSP_UART6_RX_USING_DMA
  1066. #ifdef BSP_UART6_TX_USING_DMA
  1067. status = hpm_uart_dma_tx_init(&uarts[HPM_UART6_INDEX]);
  1068. if (status != status_success)
  1069. {
  1070. return -RT_ERROR;
  1071. }
  1072. #endif //BSP_UART6_TX_USING_DMA
  1073. #endif // RT_SERIAL_USING_DMA
  1074. #endif //BSP_USING_UART6
  1075. #ifdef BSP_USING_UART7
  1076. uarts[HPM_UART7_INDEX].serial->config = config;
  1077. uarts[HPM_UART7_INDEX].serial->config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
  1078. uarts[HPM_UART7_INDEX].serial->config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
  1079. #ifdef RT_SERIAL_USING_DMA
  1080. uarts[HPM_UART7_INDEX].dma_flags = 0;
  1081. #ifdef BSP_UART7_RX_USING_DMA
  1082. status = hpm_uart_dma_rx_init(&uarts[HPM_UART7_INDEX]);
  1083. if (status != status_success)
  1084. {
  1085. return -RT_ERROR;
  1086. }
  1087. #endif //BSP_UART7_RX_USING_DMA
  1088. #ifdef BSP_UART0_TX_USING_DMA
  1089. status = hpm_uart_dma_tx_init(&uarts[HPM_UART7_INDEX]);
  1090. if (status != status_success)
  1091. {
  1092. return -RT_ERROR;
  1093. }
  1094. #endif //BSP_UART7_TX_USING_DMA
  1095. #endif // RT_SERIAL_USING_DMA
  1096. #endif //BSP_USING_UART7
  1097. #ifdef BSP_USING_UART8
  1098. uarts[HPM_UART8_INDEX].serial->config = config;
  1099. uarts[HPM_UART8_INDEX].serial->config.rx_bufsz = BSP_UART8_RX_BUFSIZE;
  1100. uarts[HPM_UART8_INDEX].serial->config.tx_bufsz = BSP_UART8_TX_BUFSIZE;
  1101. #ifdef RT_SERIAL_USING_DMA
  1102. uarts[HPM_UART8_INDEX].dma_flags = 0;
  1103. #ifdef BSP_UART8_RX_USING_DMA
  1104. status = hpm_uart_dma_rx_init(&uarts[HPM_UART8_INDEX]);
  1105. if (status != status_success)
  1106. {
  1107. return -RT_ERROR;
  1108. }
  1109. #endif //BSP_UART8_RX_USING_DMA
  1110. #ifdef BSP_UART0_TX_USING_DMA
  1111. status = hpm_uart_dma_tx_init(&uarts[HPM_UART8_INDEX]);
  1112. if (status != status_success)
  1113. {
  1114. return -RT_ERROR;
  1115. }
  1116. #endif //BSP_UART8_TX_USING_DMA
  1117. #endif // RT_SERIAL_USING_DMA
  1118. #endif //BSP_USING_UART8
  1119. #ifdef BSP_USING_UART9
  1120. uarts[HPM_UART9_INDEX].serial->config = config;
  1121. uarts[HPM_UART9_INDEX].serial->config.rx_bufsz = BSP_UART9_RX_BUFSIZE;
  1122. uarts[HPM_UART9_INDEX].serial->config.tx_bufsz = BSP_UART9_TX_BUFSIZE;
  1123. #ifdef RT_SERIAL_USING_DMA
  1124. uarts[HPM_UART9_INDEX].dma_flags = 0;
  1125. #ifdef BSP_UART9_RX_USING_DMA
  1126. status = hpm_uart_dma_rx_init(&uarts[HPM_UART9_INDEX]);
  1127. if (status != status_success)
  1128. {
  1129. return -RT_ERROR;
  1130. }
  1131. #endif //BSP_UART9_RX_USING_DMA
  1132. #ifdef BSP_UART9_TX_USING_DMA
  1133. status = hpm_uart_dma_tx_init(&uarts[HPM_UART9_INDEX]);
  1134. if (status != status_success)
  1135. {
  1136. return -RT_ERROR;
  1137. }
  1138. #endif //BSP_UART9_TX_USING_DMA
  1139. #endif // RT_SERIAL_USING_DMA
  1140. #endif //BSP_USING_UART9
  1141. #ifdef BSP_USING_UART10
  1142. uarts[HPM_UART10_INDEX].serial->config = config;
  1143. uarts[HPM_UART10_INDEX].serial->config.rx_bufsz = BSP_UART10_RX_BUFSIZE;
  1144. uarts[HPM_UART10_INDEX].serial->config.tx_bufsz = BSP_UART10_TX_BUFSIZE;
  1145. #ifdef RT_SERIAL_USING_DMA
  1146. uarts[HPM_UART10_INDEX].dma_flags = 0;
  1147. #ifdef BSP_UART10_RX_USING_DMA
  1148. status = hpm_uart_dma_rx_init(&uarts[HPM_UART10_INDEX]);
  1149. if (status != status_success)
  1150. {
  1151. return -RT_ERROR;
  1152. }
  1153. #endif //BSP_UART10_RX_USING_DMA
  1154. #ifdef BSP_UART10_TX_USING_DMA
  1155. status = hpm_uart_dma_tx_init(&uarts[HPM_UART10_INDEX]);
  1156. if (status != status_success)
  1157. {
  1158. return -RT_ERROR;
  1159. }
  1160. #endif //BSP_UART10_TX_USING_DMA
  1161. #endif // RT_SERIAL_USING_DMA
  1162. #endif //BSP_USING_UART10
  1163. #ifdef BSP_USING_UART11
  1164. uarts[HPM_UART11_INDEX].serial->config = config;
  1165. uarts[HPM_UART11_INDEX].serial->config.rx_bufsz = BSP_UART11_RX_BUFSIZE;
  1166. uarts[HPM_UART11_INDEX].serial->config.tx_bufsz = BSP_UART11_TX_BUFSIZE;
  1167. #ifdef RT_SERIAL_USING_DMA
  1168. uarts[HPM_UART11_INDEX].dma_flags = 0;
  1169. #ifdef BSP_UART11_RX_USING_DMA
  1170. status = hpm_uart_dma_rx_init(&uarts[HPM_UART11_INDEX]);
  1171. if (status != status_success)
  1172. {
  1173. return -RT_ERROR;
  1174. }
  1175. #endif //BSP_UART11_RX_USING_DMA
  1176. #ifdef BSP_UART11_TX_USING_DMA
  1177. status = hpm_uart_dma_tx_init(&uarts[HPM_UART11_INDEX]);
  1178. if (status != status_success)
  1179. {
  1180. return -RT_ERROR;
  1181. }
  1182. #endif //BSP_UART11_TX_USING_DMA
  1183. #endif // RT_SERIAL_USING_DMA
  1184. #endif //BSP_USING_UART11
  1185. #ifdef BSP_USING_UART12
  1186. uarts[HPM_UART12_INDEX].serial->config = config;
  1187. uarts[HPM_UART12_INDEX].serial->config.rx_bufsz = BSP_UART12_RX_BUFSIZE;
  1188. uarts[HPM_UART12_INDEX].serial->config.tx_bufsz = BSP_UART12_TX_BUFSIZE;
  1189. #ifdef RT_SERIAL_USING_DMA
  1190. uarts[HPM_UART12_INDEX].dma_flags = 0;
  1191. #ifdef BSP_UART12_RX_USING_DMA
  1192. status = hpm_uart_dma_rx_init(&uarts[HPM_UART12_INDEX]);
  1193. if (status != status_success)
  1194. {
  1195. return -RT_ERROR;
  1196. }
  1197. #endif //BSP_UART12_RX_USING_DMA
  1198. #ifdef BSP_UART12_TX_USING_DMA
  1199. status = hpm_uart_dma_tx_init(&uarts[HPM_UART12_INDEX]);
  1200. if (status != status_success)
  1201. {
  1202. return -RT_ERROR;
  1203. }
  1204. #endif //BSP_UART12_TX_USING_DMA
  1205. #endif // RT_SERIAL_USING_DMA
  1206. #endif //BSP_USING_UART12
  1207. #ifdef BSP_USING_UART13
  1208. uarts[HPM_UART13_INDEX].serial->config = config;
  1209. uarts[HPM_UART13_INDEX].serial->config.rx_bufsz = BSP_UART13_RX_BUFSIZE;
  1210. uarts[HPM_UART13_INDEX].serial->config.tx_bufsz = BSP_UART13_TX_BUFSIZE;
  1211. #ifdef RT_SERIAL_USING_DMA
  1212. uarts[HPM_UART13_INDEX].dma_flags = 0;
  1213. #ifdef BSP_UART13_RX_USING_DMA
  1214. status = hpm_uart_dma_rx_init(&uarts[HPM_UART13_INDEX]);
  1215. if (status != status_success)
  1216. {
  1217. return -RT_ERROR;
  1218. }
  1219. #endif //BSP_UART13_RX_USING_DMA
  1220. #ifdef BSP_UART13_TX_USING_DMA
  1221. status = hpm_uart_dma_tx_init(&uarts[HPM_UART13_INDEX]);
  1222. if (status != status_success)
  1223. {
  1224. return -RT_ERROR;
  1225. }
  1226. #endif //BSP_UART13_TX_USING_DMA
  1227. #endif // RT_SERIAL_USING_DMA
  1228. #endif //BSP_USING_UART13
  1229. #ifdef BSP_USING_UART14
  1230. uarts[HPM_UART14_INDEX].serial->config = config;
  1231. uarts[HPM_UART14_INDEX].serial->config.rx_bufsz = BSP_UART14_RX_BUFSIZE;
  1232. uarts[HPM_UART14_INDEX].serial->config.tx_bufsz = BSP_UART14_TX_BUFSIZE;
  1233. #ifdef RT_SERIAL_USING_DMA
  1234. uarts[HPM_UART14_INDEX].dma_flags = 0;
  1235. #ifdef BSP_UART14_RX_USING_DMA
  1236. status = hpm_uart_dma_rx_init(&uarts[HPM_UART14_INDEX]);
  1237. if (status != status_success)
  1238. {
  1239. return -RT_ERROR;
  1240. }
  1241. #endif //BSP_UART14_RX_USING_DMA
  1242. #ifdef BSP_UART14_TX_USING_DMA
  1243. status = hpm_uart_dma_tx_init(&uarts[HPM_UART14_INDEX]);
  1244. if (status != status_success)
  1245. {
  1246. return -RT_ERROR;
  1247. }
  1248. #endif //BSP_UART14_TX_USING_DMA
  1249. #endif // RT_SERIAL_USING_DMA
  1250. #endif //BSP_USING_UART14
  1251. #ifdef BSP_USING_UART15
  1252. uarts[HPM_UART15_INDEX].serial->config = config;
  1253. uarts[HPM_UART15_INDEX].serial->config.rx_bufsz = BSP_UART15_RX_BUFSIZE;
  1254. uarts[HPM_UART15_INDEX].serial->config.tx_bufsz = BSP_UART15_TX_BUFSIZE;
  1255. #ifdef RT_SERIAL_USING_DMA
  1256. uarts[HPM_UART15_INDEX].dma_flags = 0;
  1257. #ifdef BSP_UART15_RX_USING_DMA
  1258. status = hpm_uart_dma_rx_init(&uarts[HPM_UART15_INDEX]);
  1259. if (status != status_success)
  1260. {
  1261. return -RT_ERROR;
  1262. }
  1263. #endif //BSP_UART15_RX_USING_DMA
  1264. #ifdef BSP_UART15_TX_USING_DMA
  1265. status = hpm_uart_dma_tx_init(&uarts[HPM_UART15_INDEX]);
  1266. if (status != status_success)
  1267. {
  1268. return -RT_ERROR;
  1269. }
  1270. #endif //BSP_UART15_TX_USING_DMA
  1271. #endif // RT_SERIAL_USING_DMA
  1272. #endif //BSP_USING_UART15
  1273. return RT_EOK;
  1274. }
  1275. int rt_hw_uart_init(void)
  1276. {
  1277. /* Added bypass logic here since the rt_hw_uart_init function will be initialized twice, the 2nd initialization should be bypassed */
  1278. static bool initialized;
  1279. rt_err_t err = RT_EOK;
  1280. if (initialized)
  1281. {
  1282. return err;
  1283. }
  1284. else
  1285. {
  1286. initialized = true;
  1287. }
  1288. if (RT_EOK != hpm_uart_config()) {
  1289. return RT_ERROR;
  1290. }
  1291. for (uint32_t i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) {
  1292. uarts[i].serial->ops = &hpm_uart_ops;
  1293. /* register UART device */
  1294. err = rt_hw_serial_register(uarts[i].serial,
  1295. uarts[i].device_name,
  1296. RT_DEVICE_FLAG_RDWR,
  1297. (void*)&uarts[i]);
  1298. }
  1299. return err;
  1300. }
  1301. INIT_BOARD_EXPORT(rt_hw_uart_init);
  1302. #endif /* RT_USING_SERIAL */