serial.c 9.3 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2006-08-23 Bernard first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "LPC24xx.h"
  13. #include "board.h"
  14. /* serial hardware register */
  15. #define REG8(d) (*((volatile unsigned char *)(d)))
  16. #define REG32(d) (*((volatile unsigned long *)(d)))
  17. #define UART_RBR(base) REG8(base + 0x00)
  18. #define UART_THR(base) REG8(base + 0x00)
  19. #define UART_IER(base) REG32(base + 0x04)
  20. #define UART_IIR(base) REG32(base + 0x08)
  21. #define UART_FCR(base) REG8(base + 0x08)
  22. #define UART_LCR(base) REG8(base + 0x0C)
  23. #define UART_MCR(base) REG8(base + 0x10)
  24. #define UART_LSR(base) REG8(base + 0x14)
  25. #define UART_MSR(base) REG8(base + 0x18)
  26. #define UART_SCR(base) REG8(base + 0x1C)
  27. #define UART_DLL(base) REG8(base + 0x00)
  28. #define UART_DLM(base) REG8(base + 0x04)
  29. #define UART_ACR(base) REG32(base + 0x20)
  30. #define UART_FDR(base) REG32(base + 0x28)
  31. #define UART_TER(base) REG8(base + 0x30)
  32. /* LPC serial device */
  33. struct rt_lpcserial
  34. {
  35. /* inherit from device */
  36. struct rt_device parent;
  37. rt_uint32_t hw_base;
  38. rt_uint32_t irqno;
  39. rt_uint32_t baudrate;
  40. /* reception field */
  41. rt_uint16_t save_index, read_index;
  42. rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
  43. };
  44. #ifdef RT_USING_UART1
  45. struct rt_lpcserial serial1;
  46. #endif
  47. #ifdef RT_USING_UART2
  48. struct rt_lpcserial serial2;
  49. #endif
  50. void rt_hw_serial_init(void);
  51. #define U0PINS 0x00000005
  52. void rt_hw_uart_isr(int irqno, void *param)
  53. {
  54. rt_uint32_t iir;
  55. struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param;
  56. RT_ASSERT(lpc_serial != RT_NULL)
  57. RT_UNUSED(iir);
  58. if (UART_LSR(lpc_serial->hw_base) & 0x01)
  59. {
  60. rt_base_t level;
  61. while (UART_LSR(lpc_serial->hw_base) & 0x01)
  62. {
  63. /* disable interrupt */
  64. level = rt_hw_interrupt_disable();
  65. /* read character */
  66. lpc_serial->rx_buffer[lpc_serial->save_index] =
  67. UART_RBR(lpc_serial->hw_base);
  68. lpc_serial->save_index ++;
  69. if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
  70. lpc_serial->save_index = 0;
  71. /* if the next position is read index, discard this 'read char' */
  72. if (lpc_serial->save_index == lpc_serial->read_index)
  73. {
  74. lpc_serial->read_index ++;
  75. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  76. lpc_serial->read_index = 0;
  77. }
  78. /* enable interrupt */
  79. rt_hw_interrupt_enable(level);
  80. }
  81. /* invoke callback */
  82. if(lpc_serial->parent.rx_indicate != RT_NULL)
  83. {
  84. lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
  85. }
  86. }
  87. /* clear interrupt source */
  88. iir = UART_IIR(lpc_serial->hw_base);
  89. /* acknowledge Interrupt */
  90. VICVectAddr = 0;
  91. }
  92. /**
  93. * @addtogroup LPC214x
  94. */
  95. /*@{*/
  96. static rt_err_t rt_serial_init (rt_device_t dev)
  97. {
  98. return RT_EOK;
  99. }
  100. static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
  101. {
  102. struct rt_lpcserial* lpc_serial;
  103. lpc_serial = (struct rt_lpcserial*) dev;
  104. RT_ASSERT(lpc_serial != RT_NULL);
  105. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  106. {
  107. /* init UART rx interrupt */
  108. UART_IER(lpc_serial->hw_base) = 0x01;
  109. /* install ISR */
  110. rt_hw_interrupt_install(lpc_serial->irqno,
  111. rt_hw_uart_isr, lpc_serial, RT_NULL);
  112. rt_hw_interrupt_umask(lpc_serial->irqno);
  113. }
  114. return RT_EOK;
  115. }
  116. static rt_err_t rt_serial_close(rt_device_t dev)
  117. {
  118. struct rt_lpcserial* lpc_serial;
  119. lpc_serial = (struct rt_lpcserial*) dev;
  120. RT_ASSERT(lpc_serial != RT_NULL);
  121. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  122. {
  123. /* disable UART rx interrupt */
  124. UART_IER(lpc_serial->hw_base) = 0x00;
  125. }
  126. return RT_EOK;
  127. }
  128. static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
  129. {
  130. return RT_EOK;
  131. }
  132. static rt_ssize_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
  133. {
  134. rt_uint8_t* ptr;
  135. struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
  136. RT_ASSERT(lpc_serial != RT_NULL);
  137. /* point to buffer */
  138. ptr = (rt_uint8_t*) buffer;
  139. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  140. {
  141. while (size)
  142. {
  143. /* interrupt receive */
  144. rt_base_t level;
  145. /* disable interrupt */
  146. level = rt_hw_interrupt_disable();
  147. if (lpc_serial->read_index != lpc_serial->save_index)
  148. {
  149. *ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
  150. lpc_serial->read_index ++;
  151. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  152. lpc_serial->read_index = 0;
  153. }
  154. else
  155. {
  156. /* no data in rx buffer */
  157. /* enable interrupt */
  158. rt_hw_interrupt_enable(level);
  159. break;
  160. }
  161. /* enable interrupt */
  162. rt_hw_interrupt_enable(level);
  163. ptr ++; size --;
  164. }
  165. return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
  166. }
  167. else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
  168. {
  169. /* not support right now */
  170. RT_ASSERT(0);
  171. }
  172. /* polling mode */
  173. while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
  174. {
  175. /* Read Character */
  176. *ptr = UART_RBR(lpc_serial->hw_base);
  177. ptr ++;
  178. size --;
  179. }
  180. return (rt_size_t)ptr - (rt_size_t)buffer;
  181. }
  182. static rt_ssize_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
  183. {
  184. struct rt_lpcserial* lpc_serial;
  185. char *ptr;
  186. lpc_serial = (struct rt_lpcserial*) dev;
  187. if (dev->flag & RT_DEVICE_FLAG_INT_TX)
  188. {
  189. /* not support */
  190. RT_ASSERT(0);
  191. }
  192. else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
  193. {
  194. /* not support */
  195. RT_ASSERT(0);
  196. }
  197. /* polling write */
  198. ptr = (char *)buffer;
  199. if (dev->flag & RT_DEVICE_FLAG_STREAM)
  200. {
  201. /* stream mode */
  202. while (size)
  203. {
  204. if (*ptr == '\n')
  205. {
  206. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  207. UART_THR(lpc_serial->hw_base) = '\r';
  208. }
  209. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  210. UART_THR(lpc_serial->hw_base) = *ptr;
  211. ptr ++;
  212. size --;
  213. }
  214. }
  215. else
  216. {
  217. while (size)
  218. {
  219. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  220. UART_THR(lpc_serial->hw_base) = *ptr;
  221. ptr ++;
  222. size --;
  223. }
  224. }
  225. return (rt_size_t) ptr - (rt_size_t) buffer;
  226. }
  227. void rt_hw_serial_init(void)
  228. {
  229. struct rt_lpcserial* lpc_serial;
  230. #ifdef RT_USING_UART1
  231. lpc_serial = &serial1;
  232. lpc_serial->parent.type = RT_Device_Class_Char;
  233. lpc_serial->hw_base = 0xE000C000;
  234. lpc_serial->baudrate = 115200;
  235. lpc_serial->irqno = UART0_INT;
  236. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  237. lpc_serial->read_index = lpc_serial->save_index = 0;
  238. /* Enable UART0 RxD and TxD pins */
  239. PINSEL0 |= 0x50;
  240. /* 8 bits, no Parity, 1 Stop bit */
  241. UART_LCR(lpc_serial->hw_base) = 0x83;
  242. /* Setup Baudrate */
  243. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  244. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  245. /* DLAB = 0 */
  246. UART_LCR(lpc_serial->hw_base) = 0x03;
  247. lpc_serial->parent.type = RT_Device_Class_Char;
  248. lpc_serial->parent.init = rt_serial_init;
  249. lpc_serial->parent.open = rt_serial_open;
  250. lpc_serial->parent.close = rt_serial_close;
  251. lpc_serial->parent.read = rt_serial_read;
  252. lpc_serial->parent.write = rt_serial_write;
  253. lpc_serial->parent.control = rt_serial_control;
  254. lpc_serial->parent.user_data = RT_NULL;
  255. rt_device_register(&lpc_serial->parent,
  256. "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
  257. #endif
  258. #ifdef RT_USING_UART2
  259. lpc_serial = &serial2;
  260. lpc_serial->parent.type = RT_Device_Class_Char;
  261. lpc_serial->hw_base = 0xE0010000;
  262. lpc_serial->baudrate = 115200;
  263. lpc_serial->irqno = UART1_INT;
  264. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  265. lpc_serial->read_index = lpc_serial->save_index = 0;
  266. /* Enable UART1 RxD and TxD pins */
  267. PINSEL0 |= 0x05 << 16;
  268. /* 8 bits, no Parity, 1 Stop bit */
  269. UART_LCR(lpc_serial->hw_base) = 0x83;
  270. /* Setup Baudrate */
  271. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  272. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  273. /* DLAB = 0 */
  274. UART_LCR(lpc_serial->hw_base) = 0x03;
  275. lpc_serial->parent.type = RT_Device_Class_Char;
  276. lpc_serial->parent.init = rt_serial_init;
  277. lpc_serial->parent.open = rt_serial_open;
  278. lpc_serial->parent.close = rt_serial_close;
  279. lpc_serial->parent.read = rt_serial_read;
  280. lpc_serial->parent.write = rt_serial_write;
  281. lpc_serial->parent.control = rt_serial_control;
  282. lpc_serial->parent.user_data = RT_NULL;
  283. rt_device_register(&lpc_serial->parent,
  284. "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
  285. #endif
  286. }
  287. /*@}*/