drv_adc.c 6.3 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-10-19 Nations first version
  9. */
  10. #include "drv_adc.h"
  11. #ifdef RT_USING_ADC
  12. #if defined(BSP_USING_ADC) || defined(BSP_USING_ADC1) || \
  13. defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || \
  14. defined(BSP_USING_ADC4)
  15. static struct n32_adc_config adc_config[] =
  16. {
  17. #if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
  18. #ifdef BSP_USING_ADC
  19. {
  20. "adc",
  21. ADC,
  22. },
  23. #endif
  24. #endif
  25. #ifdef BSP_USING_ADC1
  26. {
  27. "adc1",
  28. ADC1,
  29. },
  30. #endif
  31. #ifdef BSP_USING_ADC2
  32. {
  33. "adc2",
  34. ADC2,
  35. },
  36. #endif
  37. #ifdef BSP_USING_ADC3
  38. {
  39. "adc3",
  40. ADC3,
  41. },
  42. #endif
  43. #ifdef BSP_USING_ADC4
  44. {
  45. "adc4",
  46. ADC4,
  47. },
  48. #endif
  49. };
  50. static struct n32_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])] = {0};
  51. static void n32_adc_init(struct n32_adc_config *config)
  52. {
  53. ADC_InitType ADC_InitStructure;
  54. ADC_DeInit((ADC_Module*)config->adc_periph);
  55. /* ADC configuration */
  56. #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
  57. ADC_InitStructure.WorkMode = ADC_WORKMODE_INDEPENDENT;
  58. #endif
  59. ADC_InitStructure.MultiChEn = DISABLE;
  60. ADC_InitStructure.ContinueConvEn = DISABLE;
  61. ADC_InitStructure.ExtTrigSelect = ADC_EXT_TRIGCONV_NONE;
  62. ADC_InitStructure.DatAlign = ADC_DAT_ALIGN_R;
  63. ADC_InitStructure.ChsNumber = 1;
  64. ADC_Init((ADC_Module*)config->adc_periph, &ADC_InitStructure);
  65. /* Enable ADC */
  66. ADC_Enable((ADC_Module*)config->adc_periph, ENABLE);
  67. /* Check ADC Ready */
  68. while (ADC_GetFlagStatusNew((ADC_Module*)config->adc_periph, ADC_FLAG_RDY) == RESET);
  69. /* Start ADC calibration */
  70. ADC_StartCalibration((ADC_Module*)config->adc_periph);
  71. /* Check the end of ADC calibration */
  72. while (ADC_GetCalibrationStatus((ADC_Module*)config->adc_periph));
  73. }
  74. static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
  75. {
  76. if (channel > ADC_CH_18)
  77. {
  78. return -RT_EINVAL;
  79. }
  80. return RT_EOK;
  81. }
  82. static rt_err_t n32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
  83. {
  84. struct n32_adc_config *config;
  85. RT_ASSERT(device != RT_NULL);
  86. if (channel > ADC_CH_18)
  87. {
  88. return -RT_EINVAL;
  89. }
  90. config = (struct n32_adc_config *)(device->parent.user_data);
  91. ADC_ConfigRegularChannel((ADC_Module*)config->adc_periph, channel, 1, ADC_SAMP_TIME_239CYCLES5);
  92. /* Start ADC Software Conversion */
  93. ADC_EnableSoftwareStartConv((ADC_Module*)config->adc_periph, ENABLE);
  94. while (ADC_GetFlagStatus((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC)==0)
  95. {
  96. }
  97. ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC);
  98. ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_STR);
  99. *value = ADC_GetDat((ADC_Module*)config->adc_periph);
  100. return RT_EOK;
  101. }
  102. static struct rt_adc_ops n32_adc_ops =
  103. {
  104. .enabled = n32_adc_enabled,
  105. .convert = n32_adc_convert,
  106. };
  107. int rt_hw_adc_init(void)
  108. {
  109. GPIO_InitType GPIO_InitStructure;
  110. int i = 0;
  111. int result = RT_EOK;
  112. #if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) || defined(SOC_N32G4FR)
  113. #ifdef BSP_USING_ADC
  114. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
  115. RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC, ENABLE);
  116. GPIO_InitStruct(&GPIO_InitStructure);
  117. /* Configure PA.01 PA.02 as analog input */
  118. GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2;
  119. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Analog;
  120. GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
  121. #endif
  122. #endif
  123. #ifdef BSP_USING_ADC1
  124. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
  125. RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE);
  126. GPIO_InitStruct(&GPIO_InitStructure);
  127. /* Configure PA.01 PA.03 as analog input */
  128. GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_3;
  129. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
  130. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  131. GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
  132. #endif /* BSP_USING_ADC1 */
  133. #ifdef BSP_USING_ADC2
  134. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
  135. RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE);
  136. GPIO_InitStruct(&GPIO_InitStructure);
  137. /* Configure PA.04 PA.05 as analog input */
  138. GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_5;
  139. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
  140. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  141. GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
  142. #endif /* BSP_USING_ADC2 */
  143. #ifdef BSP_USING_ADC3
  144. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
  145. RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC3, ENABLE);
  146. GPIO_InitStruct(&GPIO_InitStructure);
  147. /* Configure PB.11 PB.13 as analog input */
  148. GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
  149. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
  150. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  151. GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
  152. #endif /* BSP_USING_ADC3 */
  153. #ifdef BSP_USING_ADC4
  154. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
  155. RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC4, ENABLE);
  156. GPIO_InitStruct(&GPIO_InitStructure);
  157. /* Configure PB.14 PB.15 as analog input */
  158. GPIO_InitStructure.Pin = GPIO_PIN_14 | GPIO_PIN_15;
  159. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
  160. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  161. GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
  162. #endif /* BSP_USING_ADC4 */
  163. /* RCC_ADCHCLK_DIV16*/
  164. ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV16);
  165. /* Selsect HSE as RCC ADC1M CLK Source */
  166. RCC_ConfigAdc1mClk(RCC_ADC1MCLK_SRC_HSE, RCC_ADC1MCLK_DIV8);
  167. for (i = 0; i < sizeof(adc_obj) / sizeof(adc_obj[0]); i++)
  168. {
  169. adc_obj[i].config = &adc_config[i];
  170. n32_adc_init(&adc_config[i]);
  171. rt_hw_adc_register(&adc_obj[i].adc_device, \
  172. adc_obj[i].config->name, &n32_adc_ops, adc_obj[i].config);
  173. }
  174. return result;
  175. }
  176. INIT_DEVICE_EXPORT(rt_hw_adc_init);
  177. #endif /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || defined(BSP_USING_ADC4) */
  178. #endif /* RT_USING_ADC */