drv_usart.c 20 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-10-19 Nations first version
  9. */
  10. #include <drv_usart.h>
  11. #ifdef RT_USING_SERIAL
  12. #if defined(BSP_USING_USART1) || defined(BSP_USING_USART2) || \
  13. defined(BSP_USING_USART3) || defined(BSP_USING_UART4) || \
  14. defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \
  15. defined(BSP_USING_UART7)
  16. #include <rtdevice.h>
  17. /* n32 uart driver */
  18. // Todo: compress uart info
  19. #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
  20. struct n32_uart
  21. {
  22. USART_Module* uart_periph; //Todo: 3bits
  23. IRQn_Type irqn; //Todo: 7bits
  24. uint32_t per_clk; //Todo: 5bits
  25. uint32_t tx_gpio_clk; //Todo: 5bits
  26. uint32_t rx_gpio_clk; //Todo: 5bits
  27. GPIO_Module* tx_port; //Todo: 4bits
  28. GPIO_ModeType tx_af; //Todo: 4bits
  29. uint16_t tx_pin; //Todo: 4bits
  30. GPIO_Module* rx_port; //Todo: 4bits
  31. GPIO_ModeType rx_af; //Todo: 4bits
  32. uint16_t rx_pin; //Todo: 4bits
  33. struct rt_serial_device * serial;
  34. char *device_name;
  35. };
  36. #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
  37. struct n32_uart
  38. {
  39. USART_Module* uart_periph; // Todo: 3bits
  40. IRQn_Type irqn; // Todo: 7bits
  41. uint32_t per_clk; // Todo: 5bits
  42. uint32_t tx_gpio_clk; // Todo: 5bits
  43. uint32_t rx_gpio_clk; // Todo: 5bits
  44. GPIO_Module* tx_port; // Todo: 4bits
  45. uint32_t tx_af; // Todo: 4bits
  46. uint16_t tx_pin; // Todo: 4bits
  47. GPIO_Module* rx_port; // Todo: 4bits
  48. uint32_t rx_af; // Todo: 4bits
  49. uint16_t rx_pin; // Todo: 4bits
  50. struct rt_serial_device * serial;
  51. char *device_name;
  52. };
  53. #endif
  54. static void uart_isr(struct rt_serial_device *serial);
  55. #ifdef BSP_USING_USART1
  56. struct rt_serial_device serial1;
  57. void USART1_IRQHandler(void)
  58. {
  59. /* enter interrupt */
  60. rt_interrupt_enter();
  61. uart_isr(&serial1);
  62. /* leave interrupt */
  63. rt_interrupt_leave();
  64. }
  65. #endif /* BSP_USING_USART1 */
  66. #ifdef BSP_USING_USART2
  67. struct rt_serial_device serial2;
  68. void USART2_IRQHandler(void)
  69. {
  70. /* enter interrupt */
  71. rt_interrupt_enter();
  72. uart_isr(&serial2);
  73. /* leave interrupt */
  74. rt_interrupt_leave();
  75. }
  76. #endif /* BSP_USING_USART2 */
  77. #ifdef BSP_USING_USART3
  78. struct rt_serial_device serial3;
  79. void USART3_IRQHandler(void)
  80. {
  81. /* enter interrupt */
  82. rt_interrupt_enter();
  83. uart_isr(&serial3);
  84. /* leave interrupt */
  85. rt_interrupt_leave();
  86. }
  87. #endif /* BSP_USING_USART3 */
  88. #ifdef BSP_USING_UART4
  89. struct rt_serial_device serial4;
  90. void UART4_IRQHandler(void)
  91. {
  92. /* enter interrupt */
  93. rt_interrupt_enter();
  94. uart_isr(&serial4);
  95. /* leave interrupt */
  96. rt_interrupt_leave();
  97. }
  98. #endif /* BSP_USING_UART4 */
  99. #ifdef BSP_USING_UART5
  100. struct rt_serial_device serial5;
  101. void UART5_IRQHandler(void)
  102. {
  103. /* enter interrupt */
  104. rt_interrupt_enter();
  105. uart_isr(&serial5);
  106. /* leave interrupt */
  107. rt_interrupt_leave();
  108. }
  109. #endif /* BSP_USING_UART5 */
  110. #ifdef BSP_USING_UART6
  111. struct rt_serial_device serial6;
  112. void UART6_IRQHandler(void)
  113. {
  114. /* enter interrupt */
  115. rt_interrupt_enter();
  116. uart_isr(&serial6);
  117. /* leave interrupt */
  118. rt_interrupt_leave();
  119. }
  120. #endif /* BSP_USING_UART6 */
  121. #ifdef BSP_USING_UART7
  122. struct rt_serial_device serial7;
  123. void UART7_IRQHandler(void)
  124. {
  125. /* enter interrupt */
  126. rt_interrupt_enter();
  127. uart_isr(&serial7);
  128. /* leave interrupt */
  129. rt_interrupt_leave();
  130. }
  131. #endif /* BSP_USING_UART7 */
  132. static const struct n32_uart uarts[] = {
  133. #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
  134. #ifdef BSP_USING_USART1
  135. {
  136. USART1, // uart peripheral index
  137. USART1_IRQn, // uart iqrn
  138. RCC_APB2_PERIPH_USART1, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock
  139. GPIOA, GPIO_Mode_AF_PP, GPIO_PIN_9, // tx port, tx alternate, tx pin
  140. GPIOA, GPIO_Mode_IN_FLOATING, GPIO_PIN_10, // rx port, rx alternate, rx pin
  141. &serial1,
  142. "usart1",
  143. },
  144. #endif
  145. #ifdef BSP_USING_USART2
  146. {
  147. USART2, // uart peripheral index
  148. USART2_IRQn, // uart iqrn
  149. RCC_APB1_PERIPH_USART2, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock
  150. GPIOA, GPIO_Mode_AF_PP, GPIO_PIN_2, // tx port, tx alternate, tx pin
  151. GPIOA, GPIO_Mode_IN_FLOATING, GPIO_PIN_3, // rx port, rx alternate, rx pin
  152. &serial2,
  153. "usart2",
  154. },
  155. #endif
  156. #ifdef BSP_USING_USART3
  157. {
  158. USART3, // uart peripheral index
  159. USART3_IRQn, // uart iqrn
  160. RCC_APB1_PERIPH_USART3, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock
  161. GPIOB, GPIO_Mode_AF_PP, GPIO_PIN_10, // tx port, tx alternate, tx pin
  162. GPIOB, GPIO_Mode_IN_FLOATING, GPIO_PIN_11, // rx port, rx alternate, rx pin
  163. &serial3,
  164. "usart3",
  165. },
  166. #endif
  167. #ifdef BSP_USING_UART4
  168. {
  169. UART4, // uart peripheral index
  170. UART4_IRQn, // uart iqrn
  171. RCC_APB1_PERIPH_UART4, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock
  172. GPIOA, GPIO_Mode_AF_PP, GPIO_PIN_13, // tx port, tx alternate, tx pin
  173. GPIOA, GPIO_Mode_IN_FLOATING, GPIO_PIN_14, // rx port, rx alternate, rx pin
  174. &serial4,
  175. "uart4",
  176. },
  177. #endif
  178. #ifdef BSP_USING_UART5
  179. {
  180. UART5, // uart peripheral index
  181. UART5_IRQn, // uart iqrn
  182. RCC_APB1_PERIPH_UART5, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock
  183. GPIOB, GPIO_Mode_AF_PP, GPIO_PIN_13, // tx port, tx alternate, tx pin
  184. GPIOB, GPIO_Mode_IN_FLOATING, GPIO_PIN_14, // rx port, rx alternate, rx pin
  185. &serial5,
  186. "uart5",
  187. },
  188. #endif
  189. #ifdef BSP_USING_UART6
  190. {
  191. UART6, // uart peripheral index
  192. UART6_IRQn, // uart iqrn
  193. RCC_APB2_PERIPH_UART6, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock
  194. GPIOB, GPIO_Mode_AF_PP, GPIO_PIN_0, // tx port, tx alternate, tx pin
  195. GPIOB, GPIO_Mode_IN_FLOATING, GPIO_PIN_1, // rx port, rx alternate, rx pin
  196. &serial6,
  197. "uart6",
  198. },
  199. #endif
  200. #ifdef BSP_USING_UART7
  201. {
  202. UART7, // uart peripheral index
  203. UART7_IRQn, // uart iqrn
  204. RCC_APB2_PERIPH_UART7, RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock
  205. GPIOC, GPIO_Mode_AF_PP, GPIO_PIN_2, // tx port, tx alternate, tx pin
  206. GPIOC, GPIO_Mode_IN_FLOATING, GPIO_PIN_3, // rx port, rx alternate, rx pin
  207. &serial7,
  208. "uart7",
  209. },
  210. #endif
  211. #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
  212. #ifdef BSP_USING_USART1
  213. {
  214. USART1, // uart peripheral index
  215. USART1_IRQn, // uart iqrn
  216. RCC_APB2_PERIPH_USART1, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock
  217. GPIOA, GPIO_AF4_USART1, GPIO_PIN_9, // tx port, tx alternate, tx pin
  218. GPIOA, GPIO_AF4_USART1, GPIO_PIN_10, // rx port, rx alternate, rx pin
  219. &serial1,
  220. "usart1",
  221. },
  222. #endif
  223. #ifdef BSP_USING_USART2
  224. {
  225. USART2, // uart peripheral index
  226. USART2_IRQn, // uart iqrn
  227. RCC_APB1_PERIPH_USART2, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock
  228. GPIOA, GPIO_AF4_USART2, GPIO_PIN_2, // tx port, tx alternate, tx pin
  229. GPIOA, GPIO_AF4_USART2, GPIO_PIN_3, // rx port, rx alternate, rx pin
  230. &serial2,
  231. "usart2",
  232. },
  233. #endif
  234. #ifdef BSP_USING_USART3
  235. {
  236. USART3, // uart peripheral index
  237. USART3_IRQn, // uart iqrn
  238. RCC_APB1_PERIPH_USART3, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock
  239. GPIOB, GPIO_AF0_USART3, GPIO_PIN_10, // tx port, tx alternate, tx pin
  240. GPIOB, GPIO_AF5_USART3, GPIO_PIN_11, // rx port, rx alternate, rx pin
  241. &serial3,
  242. "usart3",
  243. },
  244. #endif
  245. #ifdef BSP_USING_UART4
  246. {
  247. UART4, // uart peripheral index
  248. UART4_IRQn, // uart iqrn
  249. RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock
  250. GPIOB, GPIO_AF6_UART4, GPIO_PIN_0, // tx port, tx alternate, tx pin
  251. GPIOB, GPIO_AF6_UART4, GPIO_PIN_1, // rx port, rx alternate, rx pin
  252. &serial4,
  253. "uart4",
  254. },
  255. #endif
  256. #ifdef BSP_USING_UART5
  257. {
  258. UART5, // uart peripheral index
  259. UART5_IRQn, // uart iqrn
  260. RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock
  261. GPIOB, GPIO_AF6_UART5, GPIO_PIN_8, // tx port, tx alternate, tx pin
  262. GPIOB, GPIO_AF6_UART5, GPIO_PIN_9, // rx port, rx alternate, rx pin
  263. &serial5,
  264. "uart5",
  265. },
  266. #endif
  267. #endif
  268. };
  269. /**
  270. * @brief UART MSP Initialization
  271. * This function configures the hardware resources used in this example:
  272. * - Peripheral's clock enable
  273. * - Peripheral's GPIO Configuration
  274. * - NVIC configuration for UART interrupt request enable
  275. * @param huart: UART handle pointer
  276. * @retval None
  277. */
  278. void n32_uart_gpio_init(struct n32_uart *uart, struct serial_configure *cfg)
  279. {
  280. GPIO_InitType GPIO_InitStructure;
  281. #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
  282. /* enable USART clock */
  283. RCC_EnableAPB2PeriphClk(uart->tx_gpio_clk | uart->rx_gpio_clk | RCC_APB2_PERIPH_AFIO, ENABLE);
  284. if (uart->uart_periph == USART1 || uart->uart_periph == UART6 || uart->uart_periph == UART7)
  285. {
  286. RCC_EnableAPB2PeriphClk(uart->per_clk, ENABLE);
  287. }
  288. else
  289. {
  290. RCC_EnableAPB1PeriphClk(uart->per_clk, ENABLE);
  291. }
  292. #ifdef BSP_USING_UART4
  293. GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_DISABLE, ENABLE);
  294. GPIO_ConfigPinRemap(GPIO_RMP2_UART4, ENABLE);
  295. #endif /* BSP_USING_UART4 */
  296. #ifdef BSP_USING_UART5
  297. GPIO_ConfigPinRemap(GPIO_RMP1_UART5, ENABLE);
  298. #endif /* BSP_USING_UART5 */
  299. #ifdef BSP_USING_UART6
  300. GPIO_ConfigPinRemap(GPIO_RMP3_UART6, ENABLE);
  301. #endif /* BSP_USING_UART6 */
  302. #ifdef BSP_USING_UART7
  303. GPIO_ConfigPinRemap(GPIO_RMP1_UART7, ENABLE);
  304. #endif /* BSP_USING_UART7 */
  305. GPIO_InitStruct(&GPIO_InitStructure);
  306. /* Config USARTx_TX I/O */
  307. GPIO_InitStructure.Pin = uart->tx_pin;
  308. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  309. GPIO_InitStructure.GPIO_Mode = uart->tx_af;
  310. GPIO_InitPeripheral(uart->tx_port, &GPIO_InitStructure);
  311. /* Config USARTx_RX I/O */
  312. GPIO_InitStructure.Pin = uart->rx_pin;
  313. GPIO_InitStructure.GPIO_Mode = uart->rx_af;
  314. GPIO_InitPeripheral(uart->rx_port, &GPIO_InitStructure);
  315. #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
  316. /* enable USART clock */
  317. RCC_EnableAPB2PeriphClk(uart->tx_gpio_clk | uart->rx_gpio_clk | RCC_APB2_PERIPH_AFIO, ENABLE);
  318. if (uart->uart_periph == USART1 || uart->uart_periph == UART4 || uart->uart_periph == UART5)
  319. {
  320. RCC_EnableAPB2PeriphClk(uart->per_clk, ENABLE);
  321. }
  322. else
  323. {
  324. RCC_EnableAPB1PeriphClk(uart->per_clk, ENABLE);
  325. }
  326. GPIO_InitStruct(&GPIO_InitStructure);
  327. /* connect port to USARTx_Tx */
  328. GPIO_InitStructure.Pin = uart->tx_pin;
  329. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
  330. GPIO_InitStructure.GPIO_Alternate = uart->tx_af;
  331. GPIO_InitPeripheral(uart->tx_port, &GPIO_InitStructure);
  332. /* connect port to USARTx_Rx */
  333. GPIO_InitStructure.Pin = uart->rx_pin;
  334. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
  335. GPIO_InitStructure.GPIO_Alternate = uart->rx_af;
  336. GPIO_InitPeripheral(uart->rx_port, &GPIO_InitStructure);
  337. #endif
  338. NVIC_SetPriority(uart->irqn, 0);
  339. NVIC_EnableIRQ(uart->irqn);
  340. }
  341. static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  342. {
  343. struct n32_uart *uart;
  344. USART_InitType USART_InitStructure;
  345. RT_ASSERT(serial != RT_NULL);
  346. RT_ASSERT(cfg != RT_NULL);
  347. uart = (struct n32_uart *)serial->parent.user_data;
  348. n32_uart_gpio_init(uart, cfg);
  349. USART_InitStructure.BaudRate = cfg->baud_rate;
  350. switch (cfg->data_bits)
  351. {
  352. case DATA_BITS_9:
  353. USART_InitStructure.WordLength = USART_WL_9B;
  354. break;
  355. default:
  356. USART_InitStructure.WordLength = USART_WL_8B;;
  357. break;
  358. }
  359. switch (cfg->stop_bits)
  360. {
  361. case STOP_BITS_1:
  362. USART_InitStructure.StopBits = USART_STPB_1;
  363. break;
  364. case STOP_BITS_2:
  365. USART_InitStructure.StopBits = USART_STPB_0_5;
  366. break;
  367. case STOP_BITS_3:
  368. USART_InitStructure.StopBits = USART_STPB_2;
  369. break;
  370. case STOP_BITS_4:
  371. USART_InitStructure.StopBits = USART_STPB_1_5;
  372. break;
  373. default:
  374. break;
  375. }
  376. switch (cfg->parity)
  377. {
  378. case PARITY_ODD:
  379. USART_InitStructure.Parity = USART_PE_ODD;
  380. break;
  381. case PARITY_EVEN:
  382. USART_InitStructure.Parity = USART_PE_EVEN;
  383. break;
  384. case PARITY_NONE:
  385. USART_InitStructure.Parity = USART_PE_NO;
  386. break;
  387. default:
  388. break;
  389. }
  390. switch (cfg->flowcontrol)
  391. {
  392. case RT_SERIAL_FLOWCONTROL_NONE:
  393. USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE;
  394. break;
  395. case RT_SERIAL_FLOWCONTROL_CTSRTS:
  396. USART_InitStructure.HardwareFlowControl = USART_HFCTRL_RTS_CTS;
  397. break;
  398. default:
  399. USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE;
  400. break;
  401. }
  402. USART_InitStructure.Mode = USART_MODE_TX | USART_MODE_RX;
  403. USART_Init(uart->uart_periph, &USART_InitStructure);
  404. USART_Enable(uart->uart_periph, ENABLE);
  405. return RT_EOK;
  406. }
  407. static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg)
  408. {
  409. struct n32_uart *uart;
  410. NVIC_InitType NVIC_InitStructure;
  411. /* Configure the NVIC Preemption Priority Bits */
  412. NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
  413. RT_ASSERT(serial != RT_NULL);
  414. uart = (struct n32_uart *)serial->parent.user_data;
  415. switch (cmd)
  416. {
  417. case RT_DEVICE_CTRL_CLR_INT:
  418. /* disable rx irq */
  419. NVIC_InitStructure.NVIC_IRQChannel = uart->irqn;
  420. NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  421. NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
  422. NVIC_Init(&NVIC_InitStructure);
  423. /* disable interrupt */
  424. USART_ConfigInt(uart->uart_periph, USART_INT_RXDNE, DISABLE);
  425. break;
  426. case RT_DEVICE_CTRL_SET_INT:
  427. /* enable rx irq */
  428. NVIC_InitStructure.NVIC_IRQChannel = uart->irqn;
  429. NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  430. NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  431. NVIC_Init(&NVIC_InitStructure);
  432. /* enable interrupt */
  433. USART_ConfigInt(uart->uart_periph, USART_INT_RXDNE, ENABLE);
  434. break;
  435. default:
  436. break;
  437. }
  438. return RT_EOK;
  439. }
  440. static int n32_putc(struct rt_serial_device *serial, char ch)
  441. {
  442. struct n32_uart *uart;
  443. RT_ASSERT(serial != RT_NULL);
  444. uart = (struct n32_uart *)serial->parent.user_data;
  445. USART_SendData(uart->uart_periph, ch);
  446. while ((USART_GetFlagStatus(uart->uart_periph, USART_FLAG_TXDE) == RESET));
  447. return 1;
  448. }
  449. static int n32_getc(struct rt_serial_device *serial)
  450. {
  451. int ch;
  452. struct n32_uart *uart;
  453. RT_ASSERT(serial != RT_NULL);
  454. uart = (struct n32_uart *)serial->parent.user_data;
  455. ch = -1;
  456. if (USART_GetFlagStatus(uart->uart_periph, USART_FLAG_RXDNE) != RESET)
  457. {
  458. ch = USART_ReceiveData(uart->uart_periph);
  459. }
  460. return ch;
  461. }
  462. /**
  463. * Uart common interrupt process. This need add to uart ISR.
  464. *
  465. * @param serial serial device
  466. */
  467. static void uart_isr(struct rt_serial_device *serial)
  468. {
  469. struct n32_uart *uart = (struct n32_uart *) serial->parent.user_data;
  470. RT_ASSERT(uart != RT_NULL);
  471. /* UART in mode Receiver -------------------------------------------------*/
  472. if (USART_GetIntStatus(uart->uart_periph, USART_INT_RXDNE) != RESET &&
  473. USART_GetFlagStatus(uart->uart_periph, USART_FLAG_RXDNE) != RESET)
  474. {
  475. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  476. }
  477. if (USART_GetIntStatus(uart->uart_periph, USART_INT_TXDE) != RESET &&
  478. USART_GetFlagStatus(uart->uart_periph, USART_FLAG_TXDE) != RESET)
  479. {
  480. /* Write one byte to the transmit data register */
  481. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  482. }
  483. }
  484. static const struct rt_uart_ops n32_uart_ops =
  485. {
  486. n32_configure,
  487. n32_control,
  488. n32_putc,
  489. n32_getc,
  490. };
  491. int rt_hw_usart_init(void)
  492. {
  493. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  494. int i;
  495. for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
  496. {
  497. uarts[i].serial->ops = &n32_uart_ops;
  498. uarts[i].serial->config = config;
  499. /* register UART device */
  500. rt_hw_serial_register(uarts[i].serial,
  501. uarts[i].device_name,
  502. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  503. (void *)&uarts[i]);
  504. }
  505. return 0;
  506. }
  507. INIT_BOARD_EXPORT(rt_hw_usart_init);
  508. #endif /* defined(BSP_USING_USARTx) */
  509. #endif /* BSP_USING_SERIAL */