drv_sdif.c 16 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Email: opensource_embedded@phytium.com.cn
  7. *
  8. * Change Logs:
  9. * Date Author Notes
  10. * 2023/7/11 liqiaozhong init SD card and mount file system
  11. * 2023/11/8 zhugengyu add interrupt handling for dma waiting, unify function naming
  12. */
  13. /***************************** Include Files *********************************/
  14. #include"rtconfig.h"
  15. #ifdef BSP_USING_SDIF
  16. #include <rthw.h>
  17. #include <rtdef.h>
  18. #include <rtthread.h>
  19. #include <rtdevice.h>
  20. #include <rtdbg.h>
  21. #include <drivers/mmcsd_core.h>
  22. #ifdef RT_USING_SMART
  23. #include "ioremap.h"
  24. #endif
  25. #include "mm_aspace.h"
  26. #include "interrupt.h"
  27. #define LOG_TAG "sdif_drv"
  28. #include "drv_log.h"
  29. #include "ftypes.h"
  30. #include "fparameters.h"
  31. #include "fcpu_info.h"
  32. #include "fsdif_timing.h"
  33. #include "fsdif.h"
  34. #include "fsdif_hw.h"
  35. #include "drv_sdif.h"
  36. /************************** Constant Definitions *****************************/
  37. #ifdef USING_SDIF0
  38. #define SDIF_CONTROLLER_ID FSDIF0_ID
  39. #elif defined (USING_SDIF1)
  40. #define SDIF_CONTROLLER_ID FSDIF1_ID
  41. #endif
  42. #define SDIF_MALLOC_CAP_DESC 256U
  43. #define SDIF_DMA_ALIGN 512U
  44. #define SDIF_DMA_BLK_SZ 512U
  45. #define SDIF_VALID_OCR 0x00FFFF80 /* supported voltage range is 1.65v-3.6v (VDD_165_195-VDD_35_36) */
  46. #define SDIF_MAX_BLK_TRANS 20U
  47. #ifndef CONFIG_SDCARD_OFFSET
  48. #define CONFIG_SDCARD_OFFSET 0x0U
  49. #endif
  50. /* preserve pointer to host instance */
  51. static struct rt_mmcsd_host *mmc_host[FSDIF_NUM] = {RT_NULL};
  52. /**************************** Type Definitions *******************************/
  53. typedef struct
  54. {
  55. FSdif *mmcsd_instance;
  56. FSdifIDmaDesc *rw_desc;
  57. rt_err_t (*transfer)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req, FSdifCmdData *cmd_data_p);
  58. struct rt_event event;
  59. #define SDIF_EVENT_CARD_DETECTED (1 << 0)
  60. #define SDIF_EVENT_COMMAND_DONE (1 << 1)
  61. #define SDIF_EVENT_DATA_DONE (1 << 2)
  62. #define SDIF_EVENT_ERROR_OCCUR (1 << 3)
  63. #define SDIF_EVENT_SDIO_IRQ (1 << 4)
  64. } fsdif_info_t;
  65. /************************** Variable Definitions *****************************/
  66. /***************** Macros (Inline Functions) Definitions *********************/
  67. void fsdif_change(void);
  68. /*******************************Api Functions*********************************/
  69. static void fsdif_host_relax(void)
  70. {
  71. rt_thread_mdelay(1);
  72. }
  73. static void fsdif_card_detect_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status)
  74. {
  75. struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
  76. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  77. rt_event_send(&private_data->event, SDIF_EVENT_CARD_DETECTED);
  78. fsdif_change();
  79. }
  80. static void fsdif_command_done_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status)
  81. {
  82. struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
  83. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  84. rt_event_send(&private_data->event, SDIF_EVENT_COMMAND_DONE);
  85. }
  86. static void fsdif_data_done_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status)
  87. {
  88. struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
  89. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  90. rt_event_send(&private_data->event, SDIF_EVENT_DATA_DONE);
  91. }
  92. static void fsdif_sdio_irq_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status)
  93. {
  94. struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
  95. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  96. rt_event_send(&private_data->event, SDIF_EVENT_SDIO_IRQ);
  97. }
  98. static void fsdif_error_occur_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status)
  99. {
  100. struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
  101. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  102. rt_event_send(&private_data->event, SDIF_EVENT_ERROR_OCCUR);
  103. }
  104. static void fsdif_ctrl_setup_interrupt(struct rt_mmcsd_host *host)
  105. {
  106. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  107. FSdif *mmcsd_instance = private_data->mmcsd_instance;
  108. FSdifConfig *config_p = &mmcsd_instance->config;
  109. rt_uint32_t cpu_id = 0;
  110. GetCpuId((u32 *)&cpu_id);
  111. rt_hw_interrupt_set_target_cpus(config_p->irq_num, cpu_id);
  112. rt_hw_interrupt_set_priority(config_p->irq_num, 0xd0);
  113. /* register intr callback */
  114. rt_hw_interrupt_install(config_p->irq_num,
  115. FSdifInterruptHandler,
  116. mmcsd_instance,
  117. NULL);
  118. /* enable irq */
  119. rt_hw_interrupt_umask(config_p->irq_num);
  120. FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_CARD_DETECTED, fsdif_card_detect_callback, host);
  121. FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_ERR_OCCURE, fsdif_error_occur_callback, host);
  122. FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_CMD_DONE, fsdif_command_done_callback, host);
  123. FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_DATA_DONE, fsdif_data_done_callback, host);
  124. FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_SDIO_IRQ, fsdif_sdio_irq_callback, host);
  125. return;
  126. }
  127. static rt_err_t fsdif_ctrl_init(struct rt_mmcsd_host *host)
  128. {
  129. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  130. FSdif *mmcsd_instance = RT_NULL;
  131. const FSdifConfig *default_mmcsd_config = RT_NULL;
  132. FSdifConfig mmcsd_config;
  133. FSdifIDmaDesc *rw_desc = RT_NULL;
  134. mmcsd_instance = rt_malloc(sizeof(FSdif));
  135. if (!mmcsd_instance)
  136. {
  137. LOG_E("Malloc mmcsd_instance failed");
  138. return RT_ERROR;
  139. }
  140. rw_desc = rt_malloc_align(SDIF_MAX_BLK_TRANS * sizeof(FSdifIDmaDesc), SDIF_MALLOC_CAP_DESC);
  141. if (!rw_desc)
  142. {
  143. LOG_E("Malloc rw_desc failed");
  144. return RT_ERROR;
  145. }
  146. rt_memset(mmcsd_instance, 0, sizeof(FSdif));
  147. rt_memset(rw_desc, 0, SDIF_MAX_BLK_TRANS * sizeof(FSdifIDmaDesc));
  148. /* SDIF controller init */
  149. RT_ASSERT((default_mmcsd_config = FSdifLookupConfig(SDIF_CONTROLLER_ID)) != RT_NULL);
  150. mmcsd_config = *default_mmcsd_config; /* load default config */
  151. #ifdef RT_USING_SMART
  152. mmcsd_config.base_addr = (uintptr)rt_ioremap((void *)mmcsd_config.base_addr, 0x1000);
  153. #endif
  154. mmcsd_config.trans_mode = FSDIF_IDMA_TRANS_MODE;
  155. #ifdef USING_EMMC
  156. mmcsd_config.non_removable = TRUE; /* eMMC is unremovable on board */
  157. #else
  158. mmcsd_config.non_removable = FALSE; /* TF card is removable on board */
  159. #endif
  160. mmcsd_config.get_tuning = FSdifGetTimingSetting;
  161. if (FSDIF_SUCCESS != FSdifCfgInitialize(mmcsd_instance, &mmcsd_config))
  162. {
  163. LOG_E("SDIF controller init failed.");
  164. return RT_ERROR;
  165. }
  166. if (FSDIF_SUCCESS != FSdifSetIDMAList(mmcsd_instance, rw_desc, (uintptr)rw_desc + PV_OFFSET, SDIF_MAX_BLK_TRANS))
  167. {
  168. LOG_E("SDIF controller setup DMA failed.");
  169. return RT_ERROR;
  170. }
  171. mmcsd_instance->desc_list.first_desc_dma = (uintptr)rw_desc + PV_OFFSET;
  172. FSdifRegisterRelaxHandler(mmcsd_instance, fsdif_host_relax); /* SDIF delay for a while */
  173. private_data->mmcsd_instance = mmcsd_instance;
  174. private_data->rw_desc = rw_desc;
  175. fsdif_ctrl_setup_interrupt(host);
  176. return RT_EOK;
  177. }
  178. rt_inline rt_err_t fsdif_dma_transfer(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req, FSdifCmdData *req_cmd)
  179. {
  180. FError ret = FT_SUCCESS;
  181. rt_uint32_t event = 0U;
  182. rt_uint32_t wait_event = 0U;
  183. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  184. FSdif *mmcsd_instance = private_data->mmcsd_instance;
  185. if (req_cmd->data_p == RT_NULL)
  186. {
  187. wait_event = SDIF_EVENT_COMMAND_DONE;
  188. }
  189. else
  190. {
  191. wait_event = SDIF_EVENT_COMMAND_DONE | SDIF_EVENT_DATA_DONE;
  192. }
  193. ret = FSdifDMATransfer(mmcsd_instance, req_cmd);
  194. if (ret != FT_SUCCESS)
  195. {
  196. LOG_E("FSdifDMATransfer() fail.");
  197. return -RT_ERROR;
  198. }
  199. while (TRUE)
  200. {
  201. if (rt_event_recv(&private_data->event,
  202. (wait_event),
  203. (RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR | RT_WAITING_NO),
  204. rt_tick_from_millisecond(5000),
  205. &event) == RT_EOK)
  206. {
  207. (void)FSdifGetCmdResponse(mmcsd_instance, req_cmd);
  208. break;
  209. }
  210. else
  211. {
  212. if (rt_event_recv(&private_data->event,
  213. (SDIF_EVENT_ERROR_OCCUR),
  214. (RT_EVENT_FLAG_CLEAR | RT_WAITING_NO),
  215. rt_tick_from_millisecond(5000),
  216. &event) == RT_EOK)
  217. {
  218. LOG_E("Sdif DMA transfer endup with error !!!");
  219. return -RT_EIO;
  220. }
  221. }
  222. fsdif_host_relax();
  223. }
  224. if (resp_type(req->cmd) & RESP_MASK)
  225. {
  226. if (resp_type(req->cmd) == RESP_R2)
  227. {
  228. req->cmd->resp[3] = req_cmd->response[0];
  229. req->cmd->resp[2] = req_cmd->response[1];
  230. req->cmd->resp[1] = req_cmd->response[2];
  231. req->cmd->resp[0] = req_cmd->response[3];
  232. }
  233. else
  234. {
  235. req->cmd->resp[0] = req_cmd->response[0];
  236. }
  237. }
  238. return RT_EOK;
  239. }
  240. static void fsdif_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  241. {
  242. /* ignore some SDIF-ONIY cmd */
  243. if ((req->cmd->cmd_code == SD_IO_SEND_OP_COND) || (req->cmd->cmd_code == SD_IO_RW_DIRECT))
  244. {
  245. req->cmd->err = -1;
  246. goto skip_cmd;
  247. }
  248. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  249. FSdifCmdData req_cmd;
  250. FSdifCmdData req_stop;
  251. FSdifData req_data;
  252. rt_uint32_t *data_buf_aligned = RT_NULL;
  253. rt_uint32_t cmd_flag = resp_type(req->cmd);
  254. rt_memset(&req_cmd, 0, sizeof(FSdifCmdData));
  255. rt_memset(&req_stop, 0, sizeof(FSdifCmdData));
  256. rt_memset(&req_data, 0, sizeof(FSdifData));
  257. /* convert req into ft driver type */
  258. if (req->cmd->cmd_code == GO_IDLE_STATE)
  259. {
  260. req_cmd.flag |= FSDIF_CMD_FLAG_NEED_INIT;
  261. }
  262. if (req->cmd->cmd_code == GO_INACTIVE_STATE)
  263. {
  264. req_cmd.flag |= FSDIF_CMD_FLAG_NEED_AUTO_STOP;
  265. }
  266. if ((cmd_flag != RESP_R3) && (cmd_flag != RESP_R4) && (cmd_flag != RESP_NONE))
  267. {
  268. req_cmd.flag |= FSDIF_CMD_FLAG_NEED_RESP_CRC;
  269. }
  270. if (cmd_flag & RESP_MASK)
  271. {
  272. req_cmd.flag |= FSDIF_CMD_FLAG_EXP_RESP;
  273. if (cmd_flag == RESP_R2)
  274. {
  275. req_cmd.flag |= FSDIF_CMD_FLAG_EXP_LONG_RESP;
  276. }
  277. }
  278. if (req->data) /* transfer command with data */
  279. {
  280. data_buf_aligned = rt_malloc_align(SDIF_DMA_BLK_SZ * req->data->blks, SDIF_DMA_ALIGN);
  281. if (!data_buf_aligned)
  282. {
  283. LOG_E("Malloc data_buf_aligned failed");
  284. return;
  285. }
  286. rt_memset(data_buf_aligned, 0, SDIF_DMA_BLK_SZ * req->data->blks);
  287. req_cmd.flag |= FSDIF_CMD_FLAG_EXP_DATA;
  288. req_data.blksz = req->data->blksize;
  289. req_data.blkcnt = req->data->blks + CONFIG_SDCARD_OFFSET;
  290. req_data.datalen = req->data->blksize * req->data->blks;
  291. if ((uintptr)req->data->buf % SDIF_DMA_ALIGN) /* data buffer should be 512-aligned */
  292. {
  293. if (req->data->flags & DATA_DIR_WRITE)
  294. {
  295. rt_memcpy((void *)data_buf_aligned, (void *)req->data->buf, req_data.datalen);
  296. }
  297. req_data.buf = (rt_uint8_t *)data_buf_aligned;
  298. req_data.buf_dma = (uintptr)data_buf_aligned + PV_OFFSET;
  299. }
  300. else
  301. {
  302. req_data.buf = (rt_uint8_t *)req->data->buf;
  303. req_data.buf_dma = (uintptr)req->data->buf + PV_OFFSET;
  304. }
  305. req_cmd.data_p = &req_data;
  306. if (req->data->flags & DATA_DIR_READ)
  307. {
  308. req_cmd.flag |= FSDIF_CMD_FLAG_READ_DATA;
  309. }
  310. else if (req->data->flags & DATA_DIR_WRITE)
  311. {
  312. req_cmd.flag |= FSDIF_CMD_FLAG_WRITE_DATA;
  313. }
  314. }
  315. req_cmd.cmdidx = req->cmd->cmd_code;
  316. req_cmd.cmdarg = req->cmd->arg;
  317. /* do cmd and data transfer */
  318. req->cmd->err = (private_data->transfer)(host, req, &req_cmd);
  319. if (req->cmd->err != RT_EOK)
  320. {
  321. LOG_E("transfer failed in %s", __func__);
  322. }
  323. if (req->data && (req->data->flags & DATA_DIR_READ))
  324. {
  325. if ((uintptr)req->data->buf % SDIF_DMA_ALIGN) /* data buffer should be 512-aligned */
  326. {
  327. rt_memcpy((void *)req->data->buf, (void *)data_buf_aligned, req_data.datalen);
  328. }
  329. }
  330. /* stop cmd */
  331. if (req->stop)
  332. {
  333. req_stop.cmdidx = req->stop->cmd_code;
  334. req_stop.cmdarg = req->stop->arg;
  335. if (req->stop->flags & RESP_MASK)
  336. {
  337. req_stop.flag |= FSDIF_CMD_FLAG_READ_DATA;
  338. if (resp_type(req->stop) == RESP_R2)
  339. {
  340. req_stop.flag |= FSDIF_CMD_FLAG_EXP_LONG_RESP;
  341. }
  342. }
  343. req->stop->err = (private_data->transfer)(host, req, &req_stop);
  344. }
  345. if (data_buf_aligned)
  346. {
  347. rt_free_align(data_buf_aligned);
  348. }
  349. skip_cmd:
  350. mmcsd_req_complete(host);
  351. }
  352. static void fsdif_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
  353. {
  354. FError ret = FT_SUCCESS;
  355. fsdif_info_t *private_data = (fsdif_info_t *)host->private_data;
  356. FSdif *mmcsd_instance = private_data->mmcsd_instance;
  357. uintptr base_addr = mmcsd_instance->config.base_addr;
  358. if (0 != io_cfg->clock)
  359. {
  360. ret = FSdifSetClkFreq(mmcsd_instance, io_cfg->clock);
  361. if (ret != FT_SUCCESS)
  362. {
  363. LOG_E("FSdifSetClkFreq fail.");
  364. }
  365. }
  366. switch (io_cfg->bus_width)
  367. {
  368. case MMCSD_BUS_WIDTH_1:
  369. FSdifSetBusWidth(base_addr, 1U);
  370. break;
  371. case MMCSD_BUS_WIDTH_4:
  372. FSdifSetBusWidth(base_addr, 4U);
  373. break;
  374. case MMCSD_BUS_WIDTH_8:
  375. FSdifSetBusWidth(base_addr, 8U);
  376. break;
  377. default:
  378. LOG_E("Invalid bus width %d", io_cfg->bus_width);
  379. break;
  380. }
  381. }
  382. static const struct rt_mmcsd_host_ops ops =
  383. {
  384. fsdif_request_send,
  385. fsdif_set_iocfg,
  386. RT_NULL,
  387. RT_NULL,
  388. RT_NULL,
  389. };
  390. void fsdif_change(void)
  391. {
  392. mmcsd_change(mmc_host[SDIF_CONTROLLER_ID]);
  393. }
  394. int rt_hw_fsdif_init(void)
  395. {
  396. /* variables init */
  397. struct rt_mmcsd_host *host = RT_NULL;
  398. fsdif_info_t *private_data = RT_NULL;
  399. rt_err_t result = RT_EOK;
  400. host = mmcsd_alloc_host();
  401. if (!host)
  402. {
  403. LOG_E("Alloc host failed");
  404. goto err_free;
  405. }
  406. private_data = rt_malloc(sizeof(fsdif_info_t));
  407. if (!private_data)
  408. {
  409. LOG_E("Malloc private_data failed");
  410. goto err_free;
  411. }
  412. rt_memset(private_data, 0, sizeof(fsdif_info_t));
  413. private_data->transfer = fsdif_dma_transfer;
  414. result = rt_event_init(&private_data->event, "sdif_event", RT_IPC_FLAG_FIFO);
  415. RT_ASSERT(RT_EOK == result);
  416. /* host data init */
  417. host->ops = &ops;
  418. host->freq_min = 400000;
  419. host->freq_max = 50000000;
  420. host->valid_ocr = SDIF_VALID_OCR; /* the voltage range supported is 1.65v-3.6v */
  421. host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4;
  422. host->max_seg_size = SDIF_DMA_BLK_SZ; /* used in block_dev.c */
  423. host->max_dma_segs = SDIF_MAX_BLK_TRANS; /* physical segment number */
  424. host->max_blk_size = SDIF_DMA_BLK_SZ; /* all the 4 para limits size of one blk tran */
  425. host->max_blk_count = SDIF_MAX_BLK_TRANS;
  426. host->private_data = private_data;
  427. mmc_host[SDIF_CONTROLLER_ID] = host;
  428. if (RT_EOK != fsdif_ctrl_init(host))
  429. {
  430. LOG_E("fsdif_ctrl_init() failed");
  431. goto err_free;
  432. }
  433. return RT_EOK;
  434. err_free:
  435. if (host)
  436. {
  437. rt_free(host);
  438. }
  439. if (private_data->mmcsd_instance)
  440. {
  441. rt_free(private_data->mmcsd_instance);
  442. }
  443. if (private_data->rw_desc)
  444. {
  445. rt_free_align(private_data->rw_desc);
  446. }
  447. if (private_data)
  448. {
  449. rt_free(private_data);
  450. }
  451. return -RT_EOK;
  452. }
  453. INIT_DEVICE_EXPORT(rt_hw_fsdif_init);
  454. #endif // #ifdef RT_USING_SDIO