drv_sdmmc.c 19 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-05-23 liuduanfei first version
  9. * 2020-08-25 wanghaijing add sdmmmc2
  10. * 2023-03-26 wdfk-prog Distinguish between SDMMC and SDIO drivers
  11. */
  12. #include "board.h"
  13. #ifdef RT_USING_SDIO
  14. #if !defined(BSP_USING_SDIO1) && !defined(BSP_USING_SDIO2)
  15. #error "Please define at least one BSP_USING_SDIOx"
  16. #endif
  17. #include "drv_sdmmc.h"
  18. #define DBG_TAG "drv.sdmmc"
  19. #ifdef DRV_DEBUG
  20. #define DBG_LVL DBG_LOG
  21. #else
  22. #define DBG_LVL DBG_INFO
  23. #endif /* DRV_DEBUG */
  24. #include <rtdbg.h>
  25. static struct stm32_sdio_class sdio_obj;
  26. static struct rt_mmcsd_host *host1;
  27. static struct rt_mmcsd_host *host2;
  28. #define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (1000000)
  29. #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
  30. #define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
  31. struct sdio_pkg
  32. {
  33. struct rt_mmcsd_cmd *cmd;
  34. void *buff;
  35. rt_uint32_t flag;
  36. };
  37. struct rthw_sdio
  38. {
  39. struct rt_mmcsd_host *host;
  40. struct stm32_sdio_des sdio_des;
  41. struct rt_event event;
  42. struct rt_mutex mutex;
  43. struct sdio_pkg *pkg;
  44. };
  45. rt_align(SDIO_ALIGN_LEN)
  46. static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
  47. /**
  48. * @brief This function get order from sdio.
  49. * @param data
  50. * @retval sdio order
  51. */
  52. static int get_order(rt_uint32_t data)
  53. {
  54. int order = 0;
  55. switch (data)
  56. {
  57. case 1:
  58. order = 0;
  59. break;
  60. case 2:
  61. order = 1;
  62. break;
  63. case 4:
  64. order = 2;
  65. break;
  66. case 8:
  67. order = 3;
  68. break;
  69. case 16:
  70. order = 4;
  71. break;
  72. case 32:
  73. order = 5;
  74. break;
  75. case 64:
  76. order = 6;
  77. break;
  78. case 128:
  79. order = 7;
  80. break;
  81. case 256:
  82. order = 8;
  83. break;
  84. case 512:
  85. order = 9;
  86. break;
  87. case 1024:
  88. order = 10;
  89. break;
  90. case 2048:
  91. order = 11;
  92. break;
  93. case 4096:
  94. order = 12;
  95. break;
  96. case 8192:
  97. order = 13;
  98. break;
  99. case 16384:
  100. order = 14;
  101. break;
  102. default :
  103. order = 0;
  104. break;
  105. }
  106. return order;
  107. }
  108. /**
  109. * @brief This function wait sdio cmd completed.
  110. * @param sdio rthw_sdio
  111. * @retval None
  112. */
  113. static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
  114. {
  115. rt_uint32_t status;
  116. struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
  117. struct rt_mmcsd_data *data = cmd->data;
  118. SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance;
  119. if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
  120. rt_tick_from_millisecond(5000), &status) != RT_EOK)
  121. {
  122. LOG_E("wait cmd completed timeout");
  123. cmd->err = -RT_ETIMEOUT;
  124. return;
  125. }
  126. if (sdio->pkg == RT_NULL)
  127. {
  128. return;
  129. }
  130. /* Get Card Specific Data */
  131. cmd->resp[0] = hsd->RESP1;
  132. if (resp_type(cmd) == RESP_R2)
  133. {
  134. cmd->resp[1] = hsd->RESP2;
  135. cmd->resp[2] = hsd->RESP3;
  136. cmd->resp[3] = hsd->RESP4;
  137. }
  138. /* Check for error conditions */
  139. if (status & SDIO_ERRORS)
  140. {
  141. if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
  142. {
  143. cmd->err = RT_EOK;
  144. }
  145. else
  146. {
  147. cmd->err = -RT_ERROR;
  148. }
  149. }
  150. else
  151. {
  152. cmd->err = RT_EOK;
  153. }
  154. if (status & SDMMC_IT_CTIMEOUT)
  155. {
  156. cmd->err = -RT_ETIMEOUT;
  157. }
  158. if (status & SDMMC_IT_DCRCFAIL)
  159. {
  160. data->err = -RT_ERROR;
  161. }
  162. if (status & SDMMC_IT_DTIMEOUT)
  163. {
  164. data->err = -RT_ETIMEOUT;
  165. }
  166. if (cmd->err == RT_EOK)
  167. {
  168. LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
  169. }
  170. else
  171. {
  172. LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
  173. status,
  174. status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "",
  175. status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "",
  176. status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "",
  177. status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "",
  178. status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "",
  179. status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "",
  180. status == 0 ? "NULL" : "",
  181. cmd->cmd_code,
  182. cmd->arg,
  183. data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
  184. data ? data->blks * data->blksize : 0,
  185. data ? data->blksize : 0
  186. );
  187. }
  188. }
  189. /**
  190. * @brief This function send command.
  191. * @param sdio rthw_sdio
  192. * @param pkg sdio package
  193. * @retval None
  194. */
  195. static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
  196. {
  197. struct rt_mmcsd_cmd *cmd = pkg->cmd;
  198. struct rt_mmcsd_data *data = cmd->data;
  199. SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance;
  200. rt_uint32_t reg_cmd;
  201. rt_event_control(&sdio->event, RT_IPC_CMD_RESET, RT_NULL);
  202. /* save pkg */
  203. sdio->pkg = pkg;
  204. LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
  205. cmd->cmd_code,
  206. cmd->arg,
  207. resp_type(cmd) == RESP_NONE ? "NONE" : "",
  208. resp_type(cmd) == RESP_R1 ? "R1" : "",
  209. resp_type(cmd) == RESP_R1B ? "R1B" : "",
  210. resp_type(cmd) == RESP_R2 ? "R2" : "",
  211. resp_type(cmd) == RESP_R3 ? "R3" : "",
  212. resp_type(cmd) == RESP_R4 ? "R4" : "",
  213. resp_type(cmd) == RESP_R5 ? "R5" : "",
  214. resp_type(cmd) == RESP_R6 ? "R6" : "",
  215. resp_type(cmd) == RESP_R7 ? "R7" : "",
  216. data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
  217. data ? data->blks * data->blksize : 0,
  218. data ? data->blksize : 0
  219. );
  220. /* open irq */
  221. __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDIO_MASKR_ALL);
  222. reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN;
  223. /* data pre configuration */
  224. if (data != RT_NULL)
  225. {
  226. SCB_CleanInvalidateDCache();
  227. reg_cmd |= SDMMC_CMD_CMDTRANS;
  228. __HAL_SD_DISABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE);
  229. hsd->DTIMER = HW_SDIO_DATATIMEOUT;
  230. hsd->DLEN = data->blks * data->blksize;
  231. hsd->DCTRL = (get_order(data->blksize) << 4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0);
  232. hsd->IDMABASE0 = (rt_uint32_t)cache_buf;
  233. hsd->IDMACTRL = SDMMC_IDMA_IDMAEN;
  234. }
  235. /* config cmd reg */
  236. if (resp_type(cmd) == RESP_NONE)
  237. reg_cmd |= SDMMC_RESPONSE_NO;
  238. else if (resp_type(cmd) == RESP_R2)
  239. reg_cmd |= SDMMC_RESPONSE_LONG;
  240. else
  241. reg_cmd |= SDMMC_RESPONSE_SHORT;
  242. hsd->ARG = cmd->arg;
  243. hsd->CMD = reg_cmd;
  244. /* wait completed */
  245. rthw_sdio_wait_completed(sdio);
  246. /* Waiting for data to be sent to completion */
  247. if (data != RT_NULL)
  248. {
  249. volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
  250. while (count && (hsd->STA & SDMMC_STA_DPSMACT))
  251. {
  252. count--;
  253. }
  254. if ((count == 0) || (hsd->STA & SDIO_ERRORS))
  255. {
  256. cmd->err = -RT_ERROR;
  257. }
  258. }
  259. /* data post configuration */
  260. if (data != RT_NULL)
  261. {
  262. if (data->flags & DATA_DIR_READ)
  263. {
  264. rt_memcpy(data->buf, cache_buf, data->blks * data->blksize);
  265. SCB_CleanInvalidateDCache();
  266. }
  267. }
  268. }
  269. /**
  270. * @brief This function send sdio request.
  271. * @param sdio rthw_sdio
  272. * @param req request
  273. * @retval None
  274. */
  275. static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  276. {
  277. struct sdio_pkg pkg;
  278. struct rthw_sdio *sdio = host->private_data;
  279. struct rt_mmcsd_data *data;
  280. RTHW_SDIO_LOCK(sdio);
  281. if (req->cmd != RT_NULL)
  282. {
  283. rt_memset(&pkg, 0, sizeof(pkg));
  284. data = req->cmd->data;
  285. pkg.cmd = req->cmd;
  286. if (data != RT_NULL)
  287. {
  288. rt_uint32_t size = data->blks * data->blksize;
  289. RT_ASSERT(size <= SDIO_BUFF_SIZE);
  290. if (data->flags & DATA_DIR_WRITE)
  291. {
  292. rt_memcpy(cache_buf, data->buf, size);
  293. }
  294. }
  295. rthw_sdio_send_command(sdio, &pkg);
  296. }
  297. if (req->stop != RT_NULL)
  298. {
  299. rt_memset(&pkg, 0, sizeof(pkg));
  300. pkg.cmd = req->stop;
  301. rthw_sdio_send_command(sdio, &pkg);
  302. }
  303. RTHW_SDIO_UNLOCK(sdio);
  304. mmcsd_req_complete(sdio->host);
  305. }
  306. /**
  307. * @brief This function config sdio.
  308. * @param host rt_mmcsd_host
  309. * @param io_cfg rt_mmcsd_io_cfg
  310. * @retval None
  311. */
  312. static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
  313. {
  314. rt_uint32_t temp, clk_src;
  315. rt_uint32_t clk = io_cfg->clock;
  316. struct rthw_sdio *sdio = host->private_data;
  317. SD_HandleTypeDef *hsd = &sdio->sdio_des.hw_sdio;
  318. SDMMC_InitTypeDef Init = {0};
  319. rt_uint32_t sdmmc_clk = sdio->sdio_des.clk_get();
  320. if (sdmmc_clk < 400 * 1000)
  321. {
  322. LOG_E("The clock rate is too low! rata:%d", sdmmc_clk);
  323. return;
  324. }
  325. if (clk > host->freq_max)
  326. clk = host->freq_max;
  327. if (clk > sdmmc_clk)
  328. {
  329. LOG_W("Setting rate is greater than clock source rate.");
  330. clk = sdmmc_clk;
  331. }
  332. LOG_D("clk:%dK width:%s%s%s power:%s%s%s",
  333. clk / 1000,
  334. io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
  335. io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
  336. io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
  337. io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
  338. io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
  339. io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
  340. );
  341. if (sdmmc_clk != 0U)
  342. {
  343. hsd->Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
  344. /* Configure the SDMMC peripheral */
  345. Init.ClockEdge = hsd->Init.ClockEdge;
  346. Init.ClockPowerSave = hsd->Init.ClockPowerSave;
  347. if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
  348. {
  349. Init.BusWide = SDMMC_BUS_WIDE_4B;
  350. }
  351. else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
  352. {
  353. Init.BusWide = SDMMC_BUS_WIDE_8B;
  354. }
  355. else
  356. {
  357. Init.BusWide = SDMMC_BUS_WIDE_1B;
  358. }
  359. Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
  360. /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
  361. if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
  362. {
  363. Init.ClockDiv = hsd->Init.ClockDiv;
  364. }
  365. //CARD_ULTRA_HIGH_SPEED :UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards and <104Mo/s for SDR104, Spec version 3.01
  366. else if (MMCSD_TIMING_UHS_SDR50 <= io_cfg->timing && io_cfg->timing <= MMCSD_TIMING_UHS_DDR50)
  367. {
  368. /* UltraHigh speed SD card,user Clock div */
  369. Init.ClockDiv = hsd->Init.ClockDiv;
  370. }
  371. //CARD_HIGH_SPEED: High Speed Card <25Mo/s , Spec version 2.00
  372. else if (io_cfg->timing == MMCSD_TIMING_SD_HS)
  373. {
  374. /* High speed SD card, Max Frequency = 50Mhz */
  375. if (hsd->Init.ClockDiv == 0U)
  376. {
  377. if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
  378. {
  379. Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
  380. }
  381. else
  382. {
  383. Init.ClockDiv = hsd->Init.ClockDiv;
  384. }
  385. }
  386. else
  387. {
  388. if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
  389. {
  390. Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
  391. }
  392. else
  393. {
  394. Init.ClockDiv = hsd->Init.ClockDiv;
  395. }
  396. }
  397. }
  398. //CARD_NORMAL_SPEED: Normal Speed Card <12.5Mo/s , Spec Version 1.01
  399. else if (io_cfg->timing == MMCSD_TIMING_LEGACY)
  400. {
  401. /* No High speed SD card, Max Frequency = 25Mhz */
  402. if (hsd->Init.ClockDiv == 0U)
  403. {
  404. if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
  405. {
  406. Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
  407. }
  408. else
  409. {
  410. Init.ClockDiv = hsd->Init.ClockDiv;
  411. }
  412. }
  413. else
  414. {
  415. if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
  416. {
  417. Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
  418. }
  419. else
  420. {
  421. Init.ClockDiv = hsd->Init.ClockDiv;
  422. }
  423. }
  424. }
  425. (void)SDMMC_Init(hsd->Instance, Init);
  426. }
  427. switch ((io_cfg->power_mode)&0X03)
  428. {
  429. case MMCSD_POWER_OFF:
  430. /* Set Power State to OFF */
  431. (void)SDMMC_PowerState_OFF(hsd->Instance);
  432. break;
  433. case MMCSD_POWER_UP:
  434. /* In F4 series chips, 0X01 is reserved bit and has no practical effect.
  435. For F7 series chips, 0X01 is power-on after power-off,The SDMMC disables the function and the card clock stops.
  436. For H7 series chips, 0X03 is the power-on function.
  437. */
  438. case MMCSD_POWER_ON:
  439. /* Set Power State to ON */
  440. (void)SDMMC_PowerState_ON(hsd->Instance);
  441. break;
  442. default:
  443. LOG_W("unknown power mode %d", io_cfg->power_mode);
  444. break;
  445. }
  446. }
  447. /**
  448. * @brief This function update sdio interrupt.
  449. * @param host rt_mmcsd_host
  450. * @param enable
  451. * @retval None
  452. */
  453. void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
  454. {
  455. struct rthw_sdio *sdio = host->private_data;
  456. if (enable)
  457. {
  458. LOG_D("enable sdio irq");
  459. __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT);
  460. }
  461. else
  462. {
  463. LOG_D("disable sdio irq");
  464. __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT);
  465. }
  466. }
  467. /**
  468. * @brief This function detect sdcard.
  469. * @param host rt_mmcsd_host
  470. * @retval 0x01
  471. */
  472. static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
  473. {
  474. LOG_D("try to detect device");
  475. return 0x01;
  476. }
  477. /**
  478. * @brief This function interrupt process function.
  479. * @param host rt_mmcsd_host
  480. * @retval None
  481. */
  482. void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
  483. {
  484. struct rthw_sdio *sdio = host->private_data;
  485. rt_uint32_t intstatus = sdio->sdio_des.hw_sdio.Instance->STA;
  486. /* clear irq flag*/
  487. __HAL_SD_CLEAR_FLAG(&sdio->sdio_des.hw_sdio, intstatus);
  488. rt_event_send(&sdio->event, intstatus);
  489. }
  490. static const struct rt_mmcsd_host_ops ops =
  491. {
  492. rthw_sdio_request,
  493. rthw_sdio_iocfg,
  494. rthw_sd_detect,
  495. rthw_sdio_irq_update,
  496. };
  497. /**
  498. * @brief This function create mmcsd host.
  499. * @param sdio_des stm32_sdio_des
  500. * @retval rt_mmcsd_host
  501. */
  502. struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
  503. {
  504. struct rt_mmcsd_host *host;
  505. struct rthw_sdio *sdio = RT_NULL;
  506. if (sdio_des == RT_NULL)
  507. {
  508. LOG_E("L:%d F:%s",(sdio_des == RT_NULL ? "sdio_des is NULL" : ""));
  509. return RT_NULL;
  510. }
  511. sdio = rt_malloc(sizeof(struct rthw_sdio));
  512. if (sdio == RT_NULL)
  513. {
  514. LOG_E("L:%d F:%s malloc rthw_sdio fail");
  515. return RT_NULL;
  516. }
  517. rt_memset(sdio, 0, sizeof(struct rthw_sdio));
  518. host = mmcsd_alloc_host();
  519. if (host == RT_NULL)
  520. {
  521. LOG_E("L:%d F:%s mmcsd alloc host fail");
  522. rt_free(sdio);
  523. return RT_NULL;
  524. }
  525. rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
  526. #ifdef BSP_USING_SDIO1
  527. if(sdio_des->hw_sdio.Instance == SDMMC1)
  528. {
  529. rt_event_init(&sdio->event, "sdio1", RT_IPC_FLAG_FIFO);
  530. rt_mutex_init(&sdio->mutex, "sdio1", RT_IPC_FLAG_PRIO);
  531. }
  532. #endif /* BSP_USING_SDIO1 */
  533. #ifdef BSP_USING_SDIO2
  534. if(sdio_des->hw_sdio.Instance == SDMMC2)
  535. {
  536. rt_event_init(&sdio->event, "sdio2", RT_IPC_FLAG_FIFO);
  537. rt_mutex_init(&sdio->mutex, "sdio2", RT_IPC_FLAG_PRIO);
  538. }
  539. #endif /* BSP_USING_SDIO2 */
  540. /* set host default attributes */
  541. host->ops = &ops;
  542. host->freq_min = 400 * 1000;
  543. host->freq_max = SDIO_MAX_FREQ;
  544. host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
  545. #ifndef SDIO_USING_1_BIT
  546. host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED;
  547. #else
  548. host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
  549. #endif
  550. host->max_seg_size = SDIO_BUFF_SIZE;
  551. host->max_dma_segs = 1;
  552. host->max_blk_size = 512;
  553. host->max_blk_count = 512;
  554. /* link up host and sdio */
  555. sdio->host = host;
  556. host->private_data = sdio;
  557. rthw_sdio_irq_update(host, 1);
  558. /* ready to change */
  559. mmcsd_change(host);
  560. return host;
  561. }
  562. /**
  563. * @brief This function get stm32 sdio clock.
  564. * @param hw_sdio: stm32_sdio
  565. * @retval PCLK2Freq
  566. */
  567. static rt_uint32_t stm32_sdio_clock_get(void)
  568. {
  569. return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
  570. }
  571. void SDMMC1_IRQHandler(void)
  572. {
  573. /* enter interrupt */
  574. rt_interrupt_enter();
  575. /* Process All SDIO Interrupt Sources */
  576. rthw_sdio_irq_process(host1);
  577. /* leave interrupt */
  578. rt_interrupt_leave();
  579. }
  580. void SDMMC2_IRQHandler(void)
  581. {
  582. /* enter interrupt */
  583. rt_interrupt_enter();
  584. /* Process All SDIO Interrupt Sources */
  585. rthw_sdio_irq_process(host2);
  586. /* leave interrupt */
  587. rt_interrupt_leave();
  588. }
  589. int rt_hw_sdio_init(void)
  590. {
  591. #ifdef BSP_USING_SDIO1
  592. struct stm32_sdio_des sdio_des1 = {0};
  593. sdio_des1.hw_sdio.Instance = SDMMC1;
  594. HAL_SD_MspInit(&sdio_des1.hw_sdio);
  595. HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0);
  596. HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
  597. sdio_des1.clk_get = stm32_sdio_clock_get;
  598. host1 = sdio_host_create(&sdio_des1);
  599. if (host1 == RT_NULL)
  600. {
  601. LOG_E("host1 create fail");
  602. return -RT_ERROR;
  603. }
  604. #endif /* BSP_USING_SDIO1 */
  605. #ifdef BSP_USING_SDIO2
  606. struct stm32_sdio_des sdio_des2 = {0};
  607. sdio_des2.hw_sdio.Instance = SDMMC2;
  608. HAL_SD_MspInit(&sdio_des2.hw_sdio);
  609. HAL_NVIC_SetPriority(SDMMC2_IRQn, 2, 0);
  610. HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
  611. sdio_des2.clk_get = stm32_sdio_clock_get;
  612. host2 = sdio_host_create(&sdio_des2);
  613. if (host2 == RT_NULL)
  614. {
  615. LOG_E("host2 create fail");
  616. return -RT_ERROR;
  617. }
  618. #endif /* BSP_USING_SDIO2 */
  619. return RT_EOK;
  620. }
  621. INIT_DEVICE_EXPORT(rt_hw_sdio_init);
  622. void stm32_mmcsd_change(void)
  623. {
  624. #ifdef BSP_USING_SDIO1
  625. mmcsd_change(host1);
  626. #endif /* BSP_USING_SDIO2 */
  627. #ifdef BSP_USING_SDIO2
  628. mmcsd_change(host2);
  629. #endif /* BSP_USING_SDIO2 */
  630. }
  631. #endif /* RT_USING_SDIO */