drv_spi.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375
  1. /*
  2. * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-07-01 lik first version
  9. */
  10. #include "drv_spi.h"
  11. #ifdef RT_USING_SPI
  12. #ifdef BSP_USING_SPI
  13. //#define DRV_DEBUG
  14. #define LOG_TAG "drv.spi"
  15. #include <drv_log.h>
  16. #if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1)
  17. #error "Please define at least one BSP_USING_SPIx"
  18. /* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
  19. #endif
  20. struct swm_spi_cs
  21. {
  22. GPIO_TypeDef *GPIOx;
  23. uint32_t gpio_pin;
  24. };
  25. struct swm_spi_cfg
  26. {
  27. const char *name;
  28. SPI_TypeDef *SPIx;
  29. SPI_InitStructure spi_initstruct;
  30. };
  31. /* swm spi dirver class */
  32. struct swm_spi_device
  33. {
  34. struct swm_spi_cfg *spi_cfg;
  35. struct rt_spi_configuration *configure;
  36. struct rt_spi_bus spi_bus;
  37. };
  38. #ifdef BSP_USING_SPI0
  39. #ifndef SPI0_BUS_CONFIG
  40. #define SPI0_BUS_CONFIG \
  41. { \
  42. .name = "spi0", \
  43. .SPIx = SPI0, \
  44. .spi_initstruct.clkDiv = SPI_CLKDIV_16, \
  45. .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
  46. .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
  47. .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \
  48. .spi_initstruct.WordSize = 8, \
  49. .spi_initstruct.Master = 1, \
  50. .spi_initstruct.RXThreshold = 0, \
  51. .spi_initstruct.RXThresholdIEn = 0, \
  52. .spi_initstruct.TXThreshold = 0, \
  53. .spi_initstruct.TXThresholdIEn = 0, \
  54. .spi_initstruct.TXCompleteIEn = 0, \
  55. }
  56. #endif /* SPI0_BUS_CONFIG */
  57. #endif /* BSP_USING_SPI0 */
  58. #ifdef BSP_USING_SPI1
  59. #ifndef SPI1_BUS_CONFIG
  60. #define SPI1_BUS_CONFIG \
  61. { \
  62. .name = "spi1", \
  63. .SPIx = SPI1, \
  64. .spi_initstruct.clkDiv = SPI_CLKDIV_16, \
  65. .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
  66. .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
  67. .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \
  68. .spi_initstruct.WordSize = 8, \
  69. .spi_initstruct.Master = 1, \
  70. .spi_initstruct.RXThreshold = 0, \
  71. .spi_initstruct.RXThresholdIEn = 0, \
  72. .spi_initstruct.TXThreshold = 0, \
  73. .spi_initstruct.TXThresholdIEn = 0, \
  74. .spi_initstruct.TXCompleteIEn = 0, \
  75. }
  76. #endif /* SPI1_BUS_CONFIG */
  77. #endif /* BSP_USING_SPI1 */
  78. static struct swm_spi_cfg swm_spi_cfg[] =
  79. {
  80. #ifdef BSP_USING_SPI0
  81. SPI0_BUS_CONFIG,
  82. #endif
  83. #ifdef BSP_USING_SPI1
  84. SPI1_BUS_CONFIG,
  85. #endif
  86. };
  87. static struct swm_spi_device spi_bus_obj[sizeof(swm_spi_cfg) / sizeof(swm_spi_cfg[0])] = {0};
  88. static rt_err_t swm_spi_configure(struct rt_spi_device *device,
  89. struct rt_spi_configuration *configure)
  90. {
  91. RT_ASSERT(device != RT_NULL);
  92. RT_ASSERT(configure != RT_NULL);
  93. struct swm_spi_device *spi_drv = rt_container_of(device->bus, struct swm_spi_device, spi_bus);
  94. spi_drv->configure = configure;
  95. struct swm_spi_cfg *spi_cfg = spi_drv->spi_cfg;
  96. if (configure->mode & RT_SPI_SLAVE)
  97. {
  98. spi_cfg->spi_initstruct.Master = 0;
  99. }
  100. else
  101. {
  102. spi_cfg->spi_initstruct.Master = 1;
  103. }
  104. if (configure->mode & RT_SPI_3WIRE)
  105. {
  106. return -RT_EINVAL;
  107. }
  108. if (configure->data_width == 8)
  109. {
  110. spi_cfg->spi_initstruct.WordSize = 8;
  111. }
  112. else if (configure->data_width == 16)
  113. {
  114. spi_cfg->spi_initstruct.WordSize = 16;
  115. }
  116. else
  117. {
  118. return -RT_EIO;
  119. }
  120. if (configure->mode & RT_SPI_CPHA)
  121. {
  122. spi_cfg->spi_initstruct.SampleEdge = SPI_SECOND_EDGE;
  123. }
  124. else
  125. {
  126. spi_cfg->spi_initstruct.SampleEdge = SPI_FIRST_EDGE;
  127. }
  128. if (configure->mode & RT_SPI_CPOL)
  129. {
  130. spi_cfg->spi_initstruct.IdleLevel = SPI_HIGH_LEVEL;
  131. }
  132. else
  133. {
  134. spi_cfg->spi_initstruct.IdleLevel = SPI_LOW_LEVEL;
  135. }
  136. if (configure->max_hz >= SystemCoreClock / 2)
  137. {
  138. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_2;
  139. }
  140. else if (configure->max_hz >= SystemCoreClock / 4)
  141. {
  142. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_4;
  143. }
  144. else if (configure->max_hz >= SystemCoreClock / 8)
  145. {
  146. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_8;
  147. }
  148. else if (configure->max_hz >= SystemCoreClock / 16)
  149. {
  150. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_16;
  151. }
  152. else if (configure->max_hz >= SystemCoreClock / 32)
  153. {
  154. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_32;
  155. }
  156. else if (configure->max_hz >= SystemCoreClock / 64)
  157. {
  158. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_64;
  159. }
  160. else if (configure->max_hz >= SystemCoreClock / 128)
  161. {
  162. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_128;
  163. }
  164. else if (configure->max_hz >= SystemCoreClock / 256)
  165. {
  166. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_256;
  167. }
  168. else
  169. {
  170. /* min prescaler 512 */
  171. spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_512;
  172. }
  173. SPI_Init(spi_cfg->SPIx, &(spi_cfg->spi_initstruct));
  174. SPI_Open(spi_cfg->SPIx);
  175. LOG_D("%s init done", spi_cfg->name);
  176. return RT_EOK;
  177. }
  178. #define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2)
  179. #define SPISEND_1(reg, ptr, datalen) \
  180. do \
  181. { \
  182. if (datalen == 8) \
  183. { \
  184. (reg) = *(rt_uint8_t *)(ptr); \
  185. } \
  186. else \
  187. { \
  188. (reg) = *(rt_uint16_t *)(ptr); \
  189. } \
  190. } while (0)
  191. #define SPIRECV_1(reg, ptr, datalen) \
  192. do \
  193. { \
  194. if (datalen == 8) \
  195. { \
  196. *(rt_uint8_t *)(ptr) = (reg); \
  197. } \
  198. else \
  199. { \
  200. *(rt_uint16_t *)(ptr) = reg; \
  201. } \
  202. } while (0)
  203. static rt_err_t swm_spi_txrx1b(struct swm_spi_device *spi_drv, void *rcvb, const void *sndb)
  204. {
  205. rt_uint32_t padrcv = 0;
  206. rt_uint32_t padsnd = 0xFF;
  207. if (!rcvb && !sndb)
  208. {
  209. return -RT_ERROR;
  210. }
  211. if (!rcvb)
  212. {
  213. rcvb = &padrcv;
  214. }
  215. if (!sndb)
  216. {
  217. sndb = &padsnd;
  218. }
  219. while (SPI_IsTXFull(spi_drv->spi_cfg->SPIx))
  220. ;
  221. SPISEND_1(spi_drv->spi_cfg->SPIx->DATA, sndb, spi_drv->spi_cfg->spi_initstruct.WordSize);
  222. while (SPI_IsRXEmpty(spi_drv->spi_cfg->SPIx))
  223. ;
  224. SPIRECV_1(spi_drv->spi_cfg->SPIx->DATA, rcvb, spi_drv->spi_cfg->spi_initstruct.WordSize);
  225. return RT_EOK;
  226. }
  227. static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
  228. {
  229. rt_err_t res;
  230. RT_ASSERT(device != RT_NULL);
  231. RT_ASSERT(device->bus != RT_NULL);
  232. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  233. RT_ASSERT(message != RT_NULL);
  234. struct swm_spi_device *spi_drv = rt_container_of(device->bus, struct swm_spi_device, spi_bus);
  235. struct swm_spi_cfg *spi_cfg = spi_drv->spi_cfg;
  236. struct swm_spi_cs *cs = device->parent.user_data;
  237. if (message->cs_take)
  238. {
  239. GPIO_ClrBit(cs->GPIOx, cs->gpio_pin);
  240. }
  241. LOG_D("%s transfer prepare and start", spi_cfg->name);
  242. LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
  243. spi_cfg->name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length);
  244. const rt_uint8_t *sndb = message->send_buf;
  245. rt_uint8_t *rcvb = message->recv_buf;
  246. rt_int32_t length = message->length;
  247. while (length)
  248. {
  249. res = swm_spi_txrx1b(spi_drv, rcvb, sndb);
  250. if (rcvb)
  251. {
  252. rcvb += SPISTEP(spi_cfg->spi_initstruct.WordSize);
  253. }
  254. if (sndb)
  255. {
  256. sndb += SPISTEP(spi_cfg->spi_initstruct.WordSize);
  257. }
  258. if (res != RT_EOK)
  259. {
  260. break;
  261. }
  262. length--;
  263. }
  264. /* Wait until Busy flag is reset before disabling SPI */
  265. while (!SPI_IsTXEmpty(spi_cfg->SPIx) && !SPI_IsRXEmpty(spi_cfg->SPIx))
  266. ;
  267. if (message->cs_release)
  268. {
  269. GPIO_SetBit(cs->GPIOx, cs->gpio_pin);
  270. }
  271. return message->length - length;
  272. }
  273. static const struct rt_spi_ops swm_spi_ops =
  274. {
  275. .configure = swm_spi_configure,
  276. .xfer = swm_spi_xfer,
  277. };
  278. //cannot be used before completion init
  279. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint32_t cs_gpio_pin)
  280. {
  281. RT_ASSERT(bus_name != RT_NULL);
  282. RT_ASSERT(device_name != RT_NULL);
  283. rt_err_t result;
  284. struct rt_spi_device *spi_device;
  285. struct swm_spi_cs *cs_pin;
  286. GPIO_Init(cs_gpiox, cs_gpio_pin, 1, 1, 0, 0);
  287. GPIO_SetBit(cs_gpiox, cs_gpio_pin);
  288. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  289. RT_ASSERT(spi_device != RT_NULL);
  290. cs_pin = (struct swm_spi_cs *)rt_malloc(sizeof(struct swm_spi_cs));
  291. RT_ASSERT(cs_pin != RT_NULL);
  292. cs_pin->GPIOx = cs_gpiox;
  293. cs_pin->gpio_pin = cs_gpio_pin;
  294. result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  295. if (result != RT_EOK)
  296. {
  297. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  298. }
  299. RT_ASSERT(result == RT_EOK);
  300. LOG_D("%s attach to %s done", device_name, bus_name);
  301. return result;
  302. }
  303. int swm_spi_init(void)
  304. {
  305. rt_err_t result;
  306. #ifdef BSP_USING_SPI0
  307. PORT_Init(PORTM, PIN2, PORTM_PIN2_SPI0_SCLK, 0);
  308. PORT_Init(PORTM, PIN4, PORTM_PIN4_SPI0_MISO, 1);
  309. PORT_Init(PORTM, PIN5, PORTM_PIN5_SPI0_MOSI, 0);
  310. #endif //BSP_USING_SPI0
  311. #ifdef BSP_USING_SPI1
  312. PORT_Init(PORTB, PIN2, PORTB_PIN2_SPI1_SCLK, 0);
  313. PORT_Init(PORTB, PIN3, PORTB_PIN3_SPI1_MISO, 1);
  314. PORT_Init(PORTB, PIN4, PORTB_PIN4_SPI1_MOSI, 0);
  315. #endif //BSP_USING_SPI1
  316. for (int i = 0; i < sizeof(swm_spi_cfg) / sizeof(swm_spi_cfg[0]); i++)
  317. {
  318. spi_bus_obj[i].spi_cfg = &swm_spi_cfg[i];
  319. spi_bus_obj[i].spi_bus.parent.user_data = &swm_spi_cfg[i];
  320. result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, swm_spi_cfg[i].name, &swm_spi_ops);
  321. if (result != RT_EOK)
  322. {
  323. LOG_E("%s bus register fail.", swm_spi_cfg[i].name);
  324. }
  325. else
  326. {
  327. LOG_D("%s bus register success.", swm_spi_cfg[i].name);
  328. }
  329. }
  330. return result;
  331. }
  332. INIT_BOARD_EXPORT(swm_spi_init);
  333. #endif /* BSP_USING_SPI */
  334. #endif /* RT_USING_SPI */