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nand_port.h

nand_port.h 2.6 KB
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  1. /*
    2. 

  2.  * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  *
    6. 

  6.  * Change Logs:
    7. 

  7.  * Date           Author       Notes
    8. 

  8.  * 2023-03-01     CDT          first version
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __NAND_PORT_H__
    12. 

  12. #define __NAND_PORT_H__
    13. 

  13. 

  14. /******************** NAND chip information ***********************************/
    15. 

  15. #define NAND_BYTES_PER_PAGE             2048UL
    16. 

  16. #define NAND_SPARE_AREA_SIZE            64UL
    17. 

  17. #define NAND_PAGES_PER_BLOCK            64UL
    18. 

  18. #define NAND_BYTES_PER_BLOCK            (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE)
    19. 

  19. #define NAND_BLOCKS_PER_PLANE           1024UL
    20. 

  20. #define NAND_PLANE_PER_DEVICE           2UL
    21. 

  21. #define NAND_DEVICE_BLOCKS              (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE)
    22. 

  22. #define NAND_DEVICE_PAGES               (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK)
    23. 

  23. 

  24. /******************** EXMC_NFC configure **************************************/
    25. 

  25. /* chip: EXMC_NFC_BANK0~7 */
    26. 

  26. #define NAND_EXMC_NFC_BANK              EXMC_NFC_BANK0
    27. 

  27. 

  28. /* density:2Gbit */
    29. 

  29. #define NAND_EXMC_NFC_BANK_CAPACITY     EXMC_NFC_BANK_CAPACITY_2GBIT
    30. 

  30. 

  31. /* device width: 8-bit */
    32. 

  32. #define NAND_EXMC_NFC_MEMORY_WIDTH      EXMC_NFC_MEMORY_WIDTH_8BIT
    33. 

  33. 

  34. /* page size: 2KByte */
    35. 

  35. #define NAND_EXMC_NFC_PAGE_SIZE         EXMC_NFC_PAGE_SIZE_2KBYTE
    36. 

  36. 

  37. /* row address cycle: 3 */
    38. 

  38. #define NAND_EXMC_NFC_ROW_ADDR_CYCLE    EXMC_NFC_3_ROW_ADDR_CYCLE
    39. 

  39. 

  40. /* ECC mode */
    41. 

  41. #define NAND_EXMC_NFC_ECC_MD            EXMC_NFC_1BIT_ECC
    42. 

  42. 

  43. /* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */
    44. 

  44. /* TS: ALE/CLE/CE setup time(min=10ns) */
    45. 

  45. #define NAND_TS                         1U
    46. 

  46. 

  47. /* TWP: WE# pulse width (min=10ns) */
    48. 

  48. #define NAND_TWP                        1U
    49. 

  49. 

  50. /* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */
    51. 

  51. #define NAND_TRP                        2U
    52. 

  52. 

  53. /* TTH: ALE/CLE/CE hold time (min=5ns) */
    54. 

  54. #define NAND_TH                         1U
    55. 

  55. 

  56. /* TWH: WE# pulse width HIGH (min=10ns) */
    57. 

  57. #define NAND_TWH                        1U
    58. 

  58. 

  59. /* TRH: RE# pulse width HIGH (min=7ns) */
    60. 

  60. #define NAND_TRH                        1U
    61. 

  61. 

  62. /* TRR: Ready to RE# LOW (min=20ns) */
    63. 

  63. #define NAND_TRR                        2U
    64. 

  64. 

  65. /* TWB: WE# HIGH to busy (max=100ns) */
    66. 

  66. #define NAND_TWB                        1U
    67. 

  67. 

  68. /* TWB: WE# HIGH to busy (max=100ns) */
    69. 

  69. #define NAND_TRB                        1U
    70. 

  70. 

  71. /* TCCS: Change read column and Change write column delay */
    72. 

  72. #define NAND_TCCS                       5U
    73. 

  73. 

  74. /* TWTR: WE# HIGH to RE# LOW (min=60ns) */
    75. 

  75. #define NAND_TWTR                       4U
    76. 

  76. 

  77. /* TRTW: RE# HIGH to WE# LOW (min=100ns) */
    78. 

  78. #define NAND_TRTW                       7U
    79. 

  79. 

  80. /* TADL: ALE to data start (min=70ns) */
    81. 

  81. #define NAND_TADL                       5U
    82. 

  82. 

  83. #endif
    84.