drv_eth.h 8.0 KB

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  1. /*
  2. * Copyright (c) 2006-2020, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-10-30 bigmagic first version
  9. */
  10. #ifndef __DRV_ETH_H__
  11. #define __DRV_ETH_H__
  12. #define MAC_REG (void *)(0xfd580000)
  13. //#define BIT(nr) (1UL << (nr))
  14. #define SYS_REV_CTRL (0x00)
  15. #define SYS_PORT_CTRL (0x04)
  16. #define PORT_MODE_EXT_GPHY (3)
  17. #define GENET_SYS_OFF (0x0000)
  18. #define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08)
  19. #define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c)
  20. #define GENET_EXT_OFF (0x0080)
  21. #define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c)
  22. #define RGMII_LINK BIT(4)
  23. #define OOB_DISABLE BIT(5)
  24. #define RGMII_MODE_EN BIT(6)
  25. #define ID_MODE_DIS BIT(16)
  26. #define GENET_RBUF_OFF (0x0300)
  27. #define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4)
  28. #define RBUF_CTRL (GENET_RBUF_OFF + 0x00)
  29. #define RBUF_ALIGN_2B BIT(1)
  30. #define GENET_UMAC_OFF (0x0800)
  31. #define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580)
  32. #define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014)
  33. #define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c)
  34. #define UMAC_MAC1 (GENET_UMAC_OFF + 0x010)
  35. #define UMAC_CMD (GENET_UMAC_OFF + 0x008)
  36. #define MDIO_CMD (GENET_UMAC_OFF + 0x614)
  37. #define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334)
  38. #define MDIO_START_BUSY BIT(29)
  39. #define MDIO_READ_FAIL BIT(28)
  40. #define MDIO_RD (2 << 26)
  41. #define MDIO_WR BIT(26)
  42. #define MDIO_PMD_SHIFT (21)
  43. #define MDIO_PMD_MASK (0x1f)
  44. #define MDIO_REG_SHIFT (16)
  45. #define MDIO_REG_MASK (0x1f)
  46. #define CMD_TX_EN BIT(0)
  47. #define CMD_RX_EN BIT(1)
  48. #define UMAC_SPEED_10 (0)
  49. #define UMAC_SPEED_100 (1)
  50. #define UMAC_SPEED_1000 (2)
  51. #define UMAC_SPEED_2500 (3)
  52. #define CMD_SPEED_SHIFT (2)
  53. #define CMD_SPEED_MASK (3)
  54. #define CMD_SW_RESET BIT(13)
  55. #define CMD_LCL_LOOP_EN BIT(15)
  56. #define CMD_TX_EN BIT(0)
  57. #define CMD_RX_EN BIT(1)
  58. #define MIB_RESET_RX BIT(0)
  59. #define MIB_RESET_RUNT BIT(1)
  60. #define MIB_RESET_TX BIT(2)
  61. /* total number of Buffer Descriptors, same for Rx/Tx */
  62. #define TOTAL_DESCS (256)
  63. #define RX_DESCS TOTAL_DESCS
  64. #define TX_DESCS TOTAL_DESCS
  65. #define DEFAULT_Q (0x10)
  66. #define ETH_DATA_LEN (1500)
  67. #define ETH_HLEN (14)
  68. #define VLAN_HLEN (4)
  69. #define ETH_FCS_LEN (4)
  70. /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
  71. * 1536 is multiple of 256 bytes
  72. */
  73. #define ENET_BRCM_TAG_LEN (6)
  74. #define ENET_PAD (8)
  75. #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \
  76. VLAN_HLEN + ENET_BRCM_TAG_LEN + \
  77. ETH_FCS_LEN + ENET_PAD)
  78. /* Tx/Rx Dma Descriptor common bits */
  79. #define DMA_EN BIT(0)
  80. #define DMA_RING_BUF_EN_SHIFT (0x01)
  81. #define DMA_RING_BUF_EN_MASK (0xffff)
  82. #define DMA_BUFLENGTH_MASK (0x0fff)
  83. #define DMA_BUFLENGTH_SHIFT (16)
  84. #define DMA_RING_SIZE_SHIFT (16)
  85. #define DMA_OWN (0x8000)
  86. #define DMA_EOP (0x4000)
  87. #define DMA_SOP (0x2000)
  88. #define DMA_WRAP (0x1000)
  89. #define DMA_MAX_BURST_LENGTH (0x8)
  90. /* Tx specific DMA descriptor bits */
  91. #define DMA_TX_UNDERRUN (0x0200)
  92. #define DMA_TX_APPEND_CRC (0x0040)
  93. #define DMA_TX_OW_CRC (0x0020)
  94. #define DMA_TX_DO_CSUM (0x0010)
  95. #define DMA_TX_QTAG_SHIFT (7)
  96. /* DMA rings size */
  97. #define DMA_RING_SIZE (0x40)
  98. #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1))
  99. /* DMA descriptor */
  100. #define DMA_DESC_LENGTH_STATUS (0x00)
  101. #define DMA_DESC_ADDRESS_LO (0x04)
  102. #define DMA_DESC_ADDRESS_HI (0x08)
  103. #define DMA_DESC_SIZE (12)
  104. #define GENET_RX_OFF (0x2000)
  105. #define GENET_RDMA_REG_OFF \
  106. (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
  107. #define GENET_TX_OFF (0x4000)
  108. #define GENET_TDMA_REG_OFF \
  109. (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
  110. #define DMA_FC_THRESH_HI (RX_DESCS >> 4)
  111. #define DMA_FC_THRESH_LO (5)
  112. #define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \
  113. DMA_FC_THRESH_HI)
  114. #define DMA_XOFF_THRESHOLD_SHIFT (16)
  115. #define TDMA_RING_REG_BASE \
  116. (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
  117. #define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00)
  118. #define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08)
  119. #define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c)
  120. #define DMA_RING_BUF_SIZE (0x10)
  121. #define DMA_START_ADDR (0x14)
  122. #define DMA_END_ADDR (0x1c)
  123. #define DMA_MBUF_DONE_THRESH (0x24)
  124. #define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28)
  125. #define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c)
  126. #define RDMA_RING_REG_BASE \
  127. (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
  128. #define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00)
  129. #define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08)
  130. #define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c)
  131. #define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28)
  132. #define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c)
  133. #define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE)
  134. #define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE)
  135. #define DMA_RING_CFG (0x00)
  136. #define DMA_CTRL (0x04)
  137. #define DMA_SCB_BURST_SIZE (0x0c)
  138. #define RX_BUF_LENGTH (2048)
  139. #define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS)
  140. #define RX_BUF_OFFSET (2)
  141. #define PHY_INTERFACE_MODE_RGMII (7)
  142. #define PHY_INTERFACE_MODE_RGMII_RXID (9)
  143. #define BCM54213PE_MII_CONTROL (0x00)
  144. #define BCM54213PE_MII_STATUS (0x01)
  145. #define BCM54213PE_PHY_IDENTIFIER_HIGH (0x02)
  146. #define BCM54213PE_PHY_IDENTIFIER_LOW (0x03)
  147. #define BCM54213PE_AUTO_NEGOTIATION_ADV (0x04)
  148. #define BCM54213PE_AUTO_NEGOTIATION_LINK (0x05)
  149. #define BCM54213PE_AUTO_NEGOTIATION_EXPANSION (0x06)
  150. #define BCM54213PE_NEXT_PAGE_TX (0x07)
  151. #define BCM54213PE_PARTNER_RX (0x08)
  152. #define BCM54213PE_CONTROL (0x09)
  153. #define BCM54213PE_STATUS (0x0A)
  154. #define BCM54213PE_IEEE_EXTENDED_STATUS (0x0F)
  155. #define BCM54213PE_PHY_EXTENDED_CONTROL (0x10)
  156. #define BCM54213PE_PHY_EXTENDED_STATUS (0x11)
  157. #define BCM54213PE_RECEIVE_ERROR_COUNTER (0x12)
  158. #define BCM54213PE_FALSE_C_S_COUNTER (0x13)
  159. #define BCM54213PE_RECEIVE_NOT_OK_COUNTER (0x14)
  160. #define BCM54213PE_VERSION_B1 (0x600d84a2)
  161. #define BCM54213PE_VERSION_X (0x600d84a0)
  162. //BCM54213PE_MII_CONTROL
  163. #define MII_CONTROL_PHY_RESET (1 << 15)
  164. #define MII_CONTROL_AUTO_NEGOTIATION_ENABLED (1 << 12)
  165. #define MII_CONTROL_AUTO_NEGOTIATION_RESTART (1 << 9)
  166. #define MII_CONTROL_PHY_FULL_DUPLEX (1 << 8)
  167. #define MII_CONTROL_SPEED_SELECTION (1 << 6)
  168. //BCM54213PE_MII_STATUS
  169. #define MII_STATUS_LINK_UP (1 << 2)
  170. //BCM54213PE_CONTROL
  171. #define CONTROL_FULL_DUPLEX_CAPABILITY (1 << 9)
  172. #define CONTROL_HALF_DUPLEX_CAPABILITY (1 << 8)
  173. #define SPEED_1000 (1000)
  174. #define SPEED_100 (100)
  175. #define SPEED_10 (10)
  176. #endif/* __DRV_ETH_H__ */