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i2c.c 34 KB

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  1. //*****************************************************************************
  2. //
  3. // i2c.c - Driver for Inter-IC (I2C) bus block.
  4. //
  5. // Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
  9. // exclusively on LMI's microcontroller products.
  10. //
  11. // The software is owned by LMI and/or its suppliers, and is protected under
  12. // applicable copyright laws. All rights are reserved. You may not combine
  13. // this software with "viral" open-source software in order to form a larger
  14. // program. Any use in violation of the foregoing restrictions may subject
  15. // the user to criminal sanctions under applicable laws, as well as to civil
  16. // liability for the breach of the terms and conditions of this license.
  17. //
  18. // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  19. // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  20. // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  21. // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  22. // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  23. //
  24. // This is part of revision 4694 of the Stellaris Peripheral Driver Library.
  25. //
  26. //*****************************************************************************
  27. //*****************************************************************************
  28. //
  29. //! \addtogroup i2c_api
  30. //! @{
  31. //
  32. //*****************************************************************************
  33. #include "inc/hw_i2c.h"
  34. #include "inc/hw_ints.h"
  35. #include "inc/hw_memmap.h"
  36. #include "inc/hw_sysctl.h"
  37. #include "inc/hw_types.h"
  38. #include "driverlib/debug.h"
  39. #include "driverlib/i2c.h"
  40. #include "driverlib/interrupt.h"
  41. //*****************************************************************************
  42. //
  43. //! Initializes the I2C Master block.
  44. //!
  45. //! \param ulBase is the base address of the I2C Master module.
  46. //! \param ulI2CClk is the rate of the clock supplied to the I2C module.
  47. //! \param bFast set up for fast data transfers
  48. //!
  49. //! This function initializes operation of the I2C Master block. Upon
  50. //! successful initialization of the I2C block, this function will have set the
  51. //! bus speed for the master, and will have enabled the I2C Master block.
  52. //!
  53. //! If the parameter \e bFast is \b true, then the master block will be set up
  54. //! to transfer data at 400 kbps; otherwise, it will be set up to transfer data
  55. //! at 100 kbps.
  56. //!
  57. //! The peripheral clock will be the same as the processor clock. This will be
  58. //! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
  59. //! if it is constant and known (to save the code/execution overhead of a call
  60. //! to SysCtlClockGet()).
  61. //!
  62. //! This function replaces the original I2CMasterInit() API and performs the
  63. //! same actions. A macro is provided in <tt>i2c.h</tt> to map the original
  64. //! API to this API.
  65. //!
  66. //! \return None.
  67. //
  68. //*****************************************************************************
  69. void
  70. I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
  71. tBoolean bFast)
  72. {
  73. unsigned long ulSCLFreq;
  74. unsigned long ulTPR;
  75. //
  76. // Check the arguments.
  77. //
  78. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  79. //
  80. // Must enable the device before doing anything else.
  81. //
  82. I2CMasterEnable(ulBase);
  83. //
  84. // Get the desired SCL speed.
  85. //
  86. if(bFast == true)
  87. {
  88. ulSCLFreq = 400000;
  89. }
  90. else
  91. {
  92. ulSCLFreq = 100000;
  93. }
  94. //
  95. // Compute the clock divider that achieves the fastest speed less than or
  96. // equal to the desired speed. The numerator is biased to favor a larger
  97. // clock divider so that the resulting clock is always less than or equal
  98. // to the desired clock, never greater.
  99. //
  100. ulTPR = ((ulI2CClk + (2 * 10 * ulSCLFreq) - 1) / (2 * 10 * ulSCLFreq)) - 1;
  101. HWREG(ulBase + I2C_O_MTPR) = ulTPR;
  102. }
  103. //*****************************************************************************
  104. //
  105. //! Initializes the I2C Slave block.
  106. //!
  107. //! \param ulBase is the base address of the I2C Slave module.
  108. //! \param ucSlaveAddr 7-bit slave address
  109. //!
  110. //! This function initializes operation of the I2C Slave block. Upon
  111. //! successful initialization of the I2C blocks, this function will have set
  112. //! the slave address and have enabled the I2C Slave block.
  113. //!
  114. //! The parameter \e ucSlaveAddr is the value that will be compared against the
  115. //! slave address sent by an I2C master.
  116. //!
  117. //! \return None.
  118. //
  119. //*****************************************************************************
  120. void
  121. I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)
  122. {
  123. //
  124. // Check the arguments.
  125. //
  126. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  127. ASSERT(!(ucSlaveAddr & 0x80));
  128. //
  129. // Must enable the device before doing anything else.
  130. //
  131. I2CSlaveEnable(ulBase);
  132. //
  133. // Set up the slave address.
  134. //
  135. HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr;
  136. }
  137. //*****************************************************************************
  138. //
  139. //! Enables the I2C Master block.
  140. //!
  141. //! \param ulBase is the base address of the I2C Master module.
  142. //!
  143. //! This will enable operation of the I2C Master block.
  144. //!
  145. //! \return None.
  146. //
  147. //*****************************************************************************
  148. void
  149. I2CMasterEnable(unsigned long ulBase)
  150. {
  151. //
  152. // Check the arguments.
  153. //
  154. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  155. //
  156. // Enable the master block.
  157. //
  158. HWREG(ulBase + I2C_O_MCR) |= I2C_MCR_MFE;
  159. }
  160. //*****************************************************************************
  161. //
  162. //! Enables the I2C Slave block.
  163. //!
  164. //! \param ulBase is the base address of the I2C Slave module.
  165. //!
  166. //! This will enable operation of the I2C Slave block.
  167. //!
  168. //! \return None.
  169. //
  170. //*****************************************************************************
  171. void
  172. I2CSlaveEnable(unsigned long ulBase)
  173. {
  174. //
  175. // Check the arguments.
  176. //
  177. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  178. //
  179. // Enable the clock to the slave block.
  180. //
  181. HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) |=
  182. I2C_MCR_SFE;
  183. //
  184. // Enable the slave.
  185. //
  186. HWREG(ulBase + I2C_O_SCSR) = I2C_SCSR_DA;
  187. }
  188. //*****************************************************************************
  189. //
  190. //! Disables the I2C master block.
  191. //!
  192. //! \param ulBase is the base address of the I2C Master module.
  193. //!
  194. //! This will disable operation of the I2C master block.
  195. //!
  196. //! \return None.
  197. //
  198. //*****************************************************************************
  199. void
  200. I2CMasterDisable(unsigned long ulBase)
  201. {
  202. //
  203. // Check the arguments.
  204. //
  205. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  206. //
  207. // Disable the master block.
  208. //
  209. HWREG(ulBase + I2C_O_MCR) &= ~(I2C_MCR_MFE);
  210. }
  211. //*****************************************************************************
  212. //
  213. //! Disables the I2C slave block.
  214. //!
  215. //! \param ulBase is the base address of the I2C Slave module.
  216. //!
  217. //! This will disable operation of the I2C slave block.
  218. //!
  219. //! \return None.
  220. //
  221. //*****************************************************************************
  222. void
  223. I2CSlaveDisable(unsigned long ulBase)
  224. {
  225. //
  226. // Check the arguments.
  227. //
  228. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  229. //
  230. // Disable the slave.
  231. //
  232. HWREG(ulBase + I2C_O_SCSR) = 0;
  233. //
  234. // Disable the clock to the slave block.
  235. //
  236. HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) &=
  237. ~(I2C_MCR_SFE);
  238. }
  239. //*****************************************************************************
  240. //
  241. //! Registers an interrupt handler for the I2C module.
  242. //!
  243. //! \param ulBase is the base address of the I2C Master module.
  244. //! \param pfnHandler is a pointer to the function to be called when the
  245. //! I2C interrupt occurs.
  246. //!
  247. //! This sets the handler to be called when an I2C interrupt occurs. This will
  248. //! enable the global interrupt in the interrupt controller; specific I2C
  249. //! interrupts must be enabled via I2CMasterIntEnable() and
  250. //! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
  251. //! responsibility to clear the interrupt source via I2CMasterIntClear() and
  252. //! I2CSlaveIntClear().
  253. //!
  254. //! \sa IntRegister() for important information about registering interrupt
  255. //! handlers.
  256. //!
  257. //! \return None.
  258. //
  259. //*****************************************************************************
  260. void
  261. I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
  262. {
  263. unsigned long ulInt;
  264. //
  265. // Check the arguments.
  266. //
  267. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  268. //
  269. // Determine the interrupt number based on the I2C port.
  270. //
  271. ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1;
  272. //
  273. // Register the interrupt handler, returning an error if an error occurs.
  274. //
  275. IntRegister(ulInt, pfnHandler);
  276. //
  277. // Enable the I2C interrupt.
  278. //
  279. IntEnable(ulInt);
  280. }
  281. //*****************************************************************************
  282. //
  283. //! Unregisters an interrupt handler for the I2C module.
  284. //!
  285. //! \param ulBase is the base address of the I2C Master module.
  286. //!
  287. //! This function will clear the handler to be called when an I2C interrupt
  288. //! occurs. This will also mask off the interrupt in the interrupt controller
  289. //! so that the interrupt handler no longer is called.
  290. //!
  291. //! \sa IntRegister() for important information about registering interrupt
  292. //! handlers.
  293. //!
  294. //! \return None.
  295. //
  296. //*****************************************************************************
  297. void
  298. I2CIntUnregister(unsigned long ulBase)
  299. {
  300. unsigned long ulInt;
  301. //
  302. // Check the arguments.
  303. //
  304. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  305. //
  306. // Determine the interrupt number based on the I2C port.
  307. //
  308. ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1;
  309. //
  310. // Disable the interrupt.
  311. //
  312. IntDisable(ulInt);
  313. //
  314. // Unregister the interrupt handler.
  315. //
  316. IntUnregister(ulInt);
  317. }
  318. //*****************************************************************************
  319. //
  320. //! Enables the I2C Master interrupt.
  321. //!
  322. //! \param ulBase is the base address of the I2C Master module.
  323. //!
  324. //! Enables the I2C Master interrupt source.
  325. //!
  326. //! \return None.
  327. //
  328. //*****************************************************************************
  329. void
  330. I2CMasterIntEnable(unsigned long ulBase)
  331. {
  332. //
  333. // Check the arguments.
  334. //
  335. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  336. //
  337. // Enable the master interrupt.
  338. //
  339. HWREG(ulBase + I2C_O_MIMR) = 1;
  340. }
  341. //*****************************************************************************
  342. //
  343. //! Enables the I2C Slave interrupt.
  344. //!
  345. //! \param ulBase is the base address of the I2C Slave module.
  346. //!
  347. //! Enables the I2C Slave interrupt source.
  348. //!
  349. //! \return None.
  350. //
  351. //*****************************************************************************
  352. void
  353. I2CSlaveIntEnable(unsigned long ulBase)
  354. {
  355. //
  356. // Check the arguments.
  357. //
  358. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  359. //
  360. // Enable the slave interrupt.
  361. //
  362. HWREG(ulBase + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;
  363. }
  364. //*****************************************************************************
  365. //
  366. //! Enables individual I2C Slave interrupt sources.
  367. //!
  368. //! \param ulBase is the base address of the I2C Slave module.
  369. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
  370. //!
  371. //! Enables the indicated I2C Slave interrupt sources. Only the sources that
  372. //! are enabled can be reflected to the processor interrupt; disabled sources
  373. //! have no effect on the processor.
  374. //!
  375. //! The \e ulIntFlags parameter is the logical OR of any of the following:
  376. //!
  377. //! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt
  378. //! - \b I2C_SLAVE_INT_START - Start condition detected interrupt
  379. //! - \b I2C_SLAVE_INT_DATA - Data interrupt
  380. //!
  381. //! \return None.
  382. //
  383. //*****************************************************************************
  384. void
  385. I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags)
  386. {
  387. //
  388. // Check the arguments.
  389. //
  390. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  391. //
  392. // Enable the slave interrupt.
  393. //
  394. HWREG(ulBase + I2C_O_SIMR) |= ulIntFlags;
  395. }
  396. //*****************************************************************************
  397. //
  398. //! Disables the I2C Master interrupt.
  399. //!
  400. //! \param ulBase is the base address of the I2C Master module.
  401. //!
  402. //! Disables the I2C Master interrupt source.
  403. //!
  404. //! \return None.
  405. //
  406. //*****************************************************************************
  407. void
  408. I2CMasterIntDisable(unsigned long ulBase)
  409. {
  410. //
  411. // Check the arguments.
  412. //
  413. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  414. //
  415. // Disable the master interrupt.
  416. //
  417. HWREG(ulBase + I2C_O_MIMR) = 0;
  418. }
  419. //*****************************************************************************
  420. //
  421. //! Disables the I2C Slave interrupt.
  422. //!
  423. //! \param ulBase is the base address of the I2C Slave module.
  424. //!
  425. //! Disables the I2C Slave interrupt source.
  426. //!
  427. //! \return None.
  428. //
  429. //*****************************************************************************
  430. void
  431. I2CSlaveIntDisable(unsigned long ulBase)
  432. {
  433. //
  434. // Check the arguments.
  435. //
  436. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  437. //
  438. // Disable the slave interrupt.
  439. //
  440. HWREG(ulBase + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;
  441. }
  442. //*****************************************************************************
  443. //
  444. //! Disables individual I2C Slave interrupt sources.
  445. //!
  446. //! \param ulBase is the base address of the I2C Slave module.
  447. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
  448. //!
  449. //! Disables the indicated I2C Slave interrupt sources. Only the sources that
  450. //! are enabled can be reflected to the processor interrupt; disabled sources
  451. //! have no effect on the processor.
  452. //!
  453. //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
  454. //! parameter to I2CSlaveIntEnableEx().
  455. //!
  456. //! \return None.
  457. //
  458. //*****************************************************************************
  459. void
  460. I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags)
  461. {
  462. //
  463. // Check the arguments.
  464. //
  465. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  466. //
  467. // Disable the slave interrupt.
  468. //
  469. HWREG(ulBase + I2C_O_SIMR) &= ~ulIntFlags;
  470. }
  471. //*****************************************************************************
  472. //
  473. //! Gets the current I2C Master interrupt status.
  474. //!
  475. //! \param ulBase is the base address of the I2C Master module.
  476. //! \param bMasked is false if the raw interrupt status is requested and
  477. //! true if the masked interrupt status is requested.
  478. //!
  479. //! This returns the interrupt status for the I2C Master module. Either the
  480. //! raw interrupt status or the status of interrupts that are allowed to
  481. //! reflect to the processor can be returned.
  482. //!
  483. //! \return The current interrupt status, returned as \b true if active
  484. //! or \b false if not active.
  485. //
  486. //*****************************************************************************
  487. tBoolean
  488. I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)
  489. {
  490. //
  491. // Check the arguments.
  492. //
  493. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  494. //
  495. // Return either the interrupt status or the raw interrupt status as
  496. // requested.
  497. //
  498. if(bMasked)
  499. {
  500. return((HWREG(ulBase + I2C_O_MMIS)) ? true : false);
  501. }
  502. else
  503. {
  504. return((HWREG(ulBase + I2C_O_MRIS)) ? true : false);
  505. }
  506. }
  507. //*****************************************************************************
  508. //
  509. //! Gets the current I2C Slave interrupt status.
  510. //!
  511. //! \param ulBase is the base address of the I2C Slave module.
  512. //! \param bMasked is false if the raw interrupt status is requested and
  513. //! true if the masked interrupt status is requested.
  514. //!
  515. //! This returns the interrupt status for the I2C Slave module. Either the raw
  516. //! interrupt status or the status of interrupts that are allowed to reflect to
  517. //! the processor can be returned.
  518. //!
  519. //! \return The current interrupt status, returned as \b true if active
  520. //! or \b false if not active.
  521. //
  522. //*****************************************************************************
  523. tBoolean
  524. I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)
  525. {
  526. //
  527. // Check the arguments.
  528. //
  529. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  530. //
  531. // Return either the interrupt status or the raw interrupt status as
  532. // requested.
  533. //
  534. if(bMasked)
  535. {
  536. return((HWREG(ulBase + I2C_O_SMIS)) ? true : false);
  537. }
  538. else
  539. {
  540. return((HWREG(ulBase + I2C_O_SRIS)) ? true : false);
  541. }
  542. }
  543. //*****************************************************************************
  544. //
  545. //! Gets the current I2C Slave interrupt status.
  546. //!
  547. //! \param ulBase is the base address of the I2C Slave module.
  548. //! \param bMasked is false if the raw interrupt status is requested and
  549. //! true if the masked interrupt status is requested.
  550. //!
  551. //! This returns the interrupt status for the I2C Slave module. Either the raw
  552. //! interrupt status or the status of interrupts that are allowed to reflect to
  553. //! the processor can be returned.
  554. //!
  555. //! \return Returns the current interrupt status, enumerated as a bit field of
  556. //! values described in I2CSlaveIntEnableEx().
  557. //
  558. //*****************************************************************************
  559. unsigned long
  560. I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked)
  561. {
  562. unsigned long ulValue;
  563. //
  564. // Check the arguments.
  565. //
  566. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  567. //
  568. // Return either the interrupt status or the raw interrupt status as
  569. // requested.
  570. //
  571. if(bMasked)
  572. {
  573. //
  574. // Workaround for I2C slave masked interrupt status register errata
  575. // (7.1) for Dustdevil Rev A0 devices.
  576. //
  577. if(CLASS_IS_DUSTDEVIL && REVISION_IS_A0)
  578. {
  579. ulValue = HWREG(ulBase + I2C_O_SRIS);
  580. return(ulValue & HWREG(ulBase + I2C_O_SIMR));
  581. }
  582. else
  583. {
  584. return(HWREG(ulBase + I2C_O_SMIS));
  585. }
  586. }
  587. else
  588. {
  589. return(HWREG(ulBase + I2C_O_SRIS));
  590. }
  591. }
  592. //*****************************************************************************
  593. //
  594. //! Clears I2C Master interrupt sources.
  595. //!
  596. //! \param ulBase is the base address of the I2C Master module.
  597. //!
  598. //! The I2C Master interrupt source is cleared, so that it no longer asserts.
  599. //! This must be done in the interrupt handler to keep it from being called
  600. //! again immediately upon exit.
  601. //!
  602. //! \note Since there is a write buffer in the Cortex-M3 processor, it may take
  603. //! several clock cycles before the interrupt source is actually cleared.
  604. //! Therefore, it is recommended that the interrupt source be cleared early in
  605. //! the interrupt handler (as opposed to the very last action) to avoid
  606. //! returning from the interrupt handler before the interrupt source is
  607. //! actually cleared. Failure to do so may result in the interrupt handler
  608. //! being immediately reentered (since NVIC still sees the interrupt source
  609. //! asserted).
  610. //!
  611. //! \return None.
  612. //
  613. //*****************************************************************************
  614. void
  615. I2CMasterIntClear(unsigned long ulBase)
  616. {
  617. //
  618. // Check the arguments.
  619. //
  620. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  621. //
  622. // Clear the I2C master interrupt source.
  623. //
  624. HWREG(ulBase + I2C_O_MICR) = I2C_MICR_IC;
  625. //
  626. // Workaround for I2C master interrupt clear errata for rev B Stellaris
  627. // devices. For later devices, this write is ignored and therefore
  628. // harmless (other than the slight performance hit).
  629. //
  630. HWREG(ulBase + I2C_O_MMIS) = I2C_MICR_IC;
  631. }
  632. //*****************************************************************************
  633. //
  634. //! Clears I2C Slave interrupt sources.
  635. //!
  636. //! \param ulBase is the base address of the I2C Slave module.
  637. //!
  638. //! The I2C Slave interrupt source is cleared, so that it no longer asserts.
  639. //! This must be done in the interrupt handler to keep it from being called
  640. //! again immediately upon exit.
  641. //!
  642. //! \note Since there is a write buffer in the Cortex-M3 processor, it may take
  643. //! several clock cycles before the interrupt source is actually cleared.
  644. //! Therefore, it is recommended that the interrupt source be cleared early in
  645. //! the interrupt handler (as opposed to the very last action) to avoid
  646. //! returning from the interrupt handler before the interrupt source is
  647. //! actually cleared. Failure to do so may result in the interrupt handler
  648. //! being immediately reentered (since NVIC still sees the interrupt source
  649. //! asserted).
  650. //!
  651. //! \return None.
  652. //
  653. //*****************************************************************************
  654. void
  655. I2CSlaveIntClear(unsigned long ulBase)
  656. {
  657. //
  658. // Check the arguments.
  659. //
  660. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  661. //
  662. // Clear the I2C slave interrupt source.
  663. //
  664. HWREG(ulBase + I2C_O_SICR) = I2C_SICR_DATAIC;
  665. }
  666. //*****************************************************************************
  667. //
  668. //! Clears I2C Slave interrupt sources.
  669. //!
  670. //! \param ulBase is the base address of the I2C Slave module.
  671. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
  672. //!
  673. //! The specified I2C Slave interrupt sources are cleared, so that they no
  674. //! longer assert. This must be done in the interrupt handler to keep it from
  675. //! being called again immediately upon exit.
  676. //!
  677. //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
  678. //! parameter to I2CSlaveIntEnableEx().
  679. //!
  680. //! \note Since there is a write buffer in the Cortex-M3 processor, it may take
  681. //! several clock cycles before the interrupt source is actually cleared.
  682. //! Therefore, it is recommended that the interrupt source be cleared early in
  683. //! the interrupt handler (as opposed to the very last action) to avoid
  684. //! returning from the interrupt handler before the interrupt source is
  685. //! actually cleared. Failure to do so may result in the interrupt handler
  686. //! being immediately reentered (since NVIC still sees the interrupt source
  687. //! asserted).
  688. //!
  689. //! \return None.
  690. //
  691. //*****************************************************************************
  692. void
  693. I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags)
  694. {
  695. //
  696. // Check the arguments.
  697. //
  698. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  699. //
  700. // Clear the I2C slave interrupt source.
  701. //
  702. HWREG(ulBase + I2C_O_SICR) = ulIntFlags;
  703. }
  704. //*****************************************************************************
  705. //
  706. //! Sets the address that the I2C Master will place on the bus.
  707. //!
  708. //! \param ulBase is the base address of the I2C Master module.
  709. //! \param ucSlaveAddr 7-bit slave address
  710. //! \param bReceive flag indicating the type of communication with the slave
  711. //!
  712. //! This function will set the address that the I2C Master will place on the
  713. //! bus when initiating a transaction. When the \e bReceive parameter is set
  714. //! to \b true, the address will indicate that the I2C Master is initiating a
  715. //! read from the slave; otherwise the address will indicate that the I2C
  716. //! Master is initiating a write to the slave.
  717. //!
  718. //! \return None.
  719. //
  720. //*****************************************************************************
  721. void
  722. I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,
  723. tBoolean bReceive)
  724. {
  725. //
  726. // Check the arguments.
  727. //
  728. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  729. ASSERT(!(ucSlaveAddr & 0x80));
  730. //
  731. // Set the address of the slave with which the master will communicate.
  732. //
  733. HWREG(ulBase + I2C_O_MSA) = (ucSlaveAddr << 1) | bReceive;
  734. }
  735. //*****************************************************************************
  736. //
  737. //! Indicates whether or not the I2C Master is busy.
  738. //!
  739. //! \param ulBase is the base address of the I2C Master module.
  740. //!
  741. //! This function returns an indication of whether or not the I2C Master is
  742. //! busy transmitting or receiving data.
  743. //!
  744. //! \return Returns \b true if the I2C Master is busy; otherwise, returns
  745. //! \b false.
  746. //
  747. //*****************************************************************************
  748. tBoolean
  749. I2CMasterBusy(unsigned long ulBase)
  750. {
  751. //
  752. // Check the arguments.
  753. //
  754. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  755. //
  756. // Return the busy status.
  757. //
  758. if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSY)
  759. {
  760. return(true);
  761. }
  762. else
  763. {
  764. return(false);
  765. }
  766. }
  767. //*****************************************************************************
  768. //
  769. //! Indicates whether or not the I2C bus is busy.
  770. //!
  771. //! \param ulBase is the base address of the I2C Master module.
  772. //!
  773. //! This function returns an indication of whether or not the I2C bus is busy.
  774. //! This function can be used in a multi-master environment to determine if
  775. //! another master is currently using the bus.
  776. //!
  777. //! \return Returns \b true if the I2C bus is busy; otherwise, returns
  778. //! \b false.
  779. //
  780. //*****************************************************************************
  781. tBoolean
  782. I2CMasterBusBusy(unsigned long ulBase)
  783. {
  784. //
  785. // Check the arguments.
  786. //
  787. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  788. //
  789. // Return the bus busy status.
  790. //
  791. if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSBSY)
  792. {
  793. return(true);
  794. }
  795. else
  796. {
  797. return(false);
  798. }
  799. }
  800. //*****************************************************************************
  801. //
  802. //! Controls the state of the I2C Master module.
  803. //!
  804. //! \param ulBase is the base address of the I2C Master module.
  805. //! \param ulCmd command to be issued to the I2C Master module
  806. //!
  807. //! This function is used to control the state of the Master module send and
  808. //! receive operations. The \e ucCmd parameter can be one of the following
  809. //! values:
  810. //!
  811. //! - \b I2C_MASTER_CMD_SINGLE_SEND
  812. //! - \b I2C_MASTER_CMD_SINGLE_RECEIVE
  813. //! - \b I2C_MASTER_CMD_BURST_SEND_START
  814. //! - \b I2C_MASTER_CMD_BURST_SEND_CONT
  815. //! - \b I2C_MASTER_CMD_BURST_SEND_FINISH
  816. //! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
  817. //! - \b I2C_MASTER_CMD_BURST_RECEIVE_START
  818. //! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT
  819. //! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH
  820. //! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
  821. //!
  822. //! \return None.
  823. //
  824. //*****************************************************************************
  825. void
  826. I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)
  827. {
  828. //
  829. // Check the arguments.
  830. //
  831. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  832. ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||
  833. (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
  834. (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||
  835. (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
  836. (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
  837. (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
  838. (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
  839. (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
  840. (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
  841. (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
  842. //
  843. // Send the command.
  844. //
  845. HWREG(ulBase + I2C_O_MCS) = ulCmd;
  846. }
  847. //*****************************************************************************
  848. //
  849. //! Gets the error status of the I2C Master module.
  850. //!
  851. //! \param ulBase is the base address of the I2C Master module.
  852. //!
  853. //! This function is used to obtain the error status of the Master module send
  854. //! and receive operations.
  855. //!
  856. //! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE,
  857. //! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or
  858. //! \b I2C_MASTER_ERR_ARB_LOST.
  859. //
  860. //*****************************************************************************
  861. unsigned long
  862. I2CMasterErr(unsigned long ulBase)
  863. {
  864. unsigned long ulErr;
  865. //
  866. // Check the arguments.
  867. //
  868. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  869. //
  870. // Get the raw error state
  871. //
  872. ulErr = HWREG(ulBase + I2C_O_MCS);
  873. //
  874. // If the I2C master is busy, then all the other bit are invalid, and
  875. // don't have an error to report.
  876. //
  877. if(ulErr & I2C_MCS_BUSY)
  878. {
  879. return(I2C_MASTER_ERR_NONE);
  880. }
  881. //
  882. // Check for errors.
  883. //
  884. if(ulErr & I2C_MCS_ERROR)
  885. {
  886. return(ulErr & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK));
  887. }
  888. else
  889. {
  890. return(I2C_MASTER_ERR_NONE);
  891. }
  892. }
  893. //*****************************************************************************
  894. //
  895. //! Transmits a byte from the I2C Master.
  896. //!
  897. //! \param ulBase is the base address of the I2C Master module.
  898. //! \param ucData data to be transmitted from the I2C Master
  899. //!
  900. //! This function will place the supplied data into I2C Master Data Register.
  901. //!
  902. //! \return None.
  903. //
  904. //*****************************************************************************
  905. void
  906. I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)
  907. {
  908. //
  909. // Check the arguments.
  910. //
  911. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  912. //
  913. // Write the byte.
  914. //
  915. HWREG(ulBase + I2C_O_MDR) = ucData;
  916. }
  917. //*****************************************************************************
  918. //
  919. //! Receives a byte that has been sent to the I2C Master.
  920. //!
  921. //! \param ulBase is the base address of the I2C Master module.
  922. //!
  923. //! This function reads a byte of data from the I2C Master Data Register.
  924. //!
  925. //! \return Returns the byte received from by the I2C Master, cast as an
  926. //! unsigned long.
  927. //
  928. //*****************************************************************************
  929. unsigned long
  930. I2CMasterDataGet(unsigned long ulBase)
  931. {
  932. //
  933. // Check the arguments.
  934. //
  935. ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
  936. //
  937. // Read a byte.
  938. //
  939. return(HWREG(ulBase + I2C_O_MDR));
  940. }
  941. //*****************************************************************************
  942. //
  943. //! Gets the I2C Slave module status
  944. //!
  945. //! \param ulBase is the base address of the I2C Slave module.
  946. //!
  947. //! This function will return the action requested from a master, if any.
  948. //! Possible values are:
  949. //!
  950. //! - \b I2C_SLAVE_ACT_NONE
  951. //! - \b I2C_SLAVE_ACT_RREQ
  952. //! - \b I2C_SLAVE_ACT_TREQ
  953. //! - \b I2C_SLAVE_ACT_RREQ_FBR
  954. //!
  955. //! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been
  956. //! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that
  957. //! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ
  958. //! to indicate that an I2C master has requested that the I2C Slave module send
  959. //! data, and \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent
  960. //! data to the I2C slave and the first byte following the slave's own address
  961. //! has been received.
  962. //
  963. //*****************************************************************************
  964. unsigned long
  965. I2CSlaveStatus(unsigned long ulBase)
  966. {
  967. //
  968. // Check the arguments.
  969. //
  970. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  971. //
  972. // Return the slave status.
  973. //
  974. return(HWREG(ulBase + I2C_O_SCSR));
  975. }
  976. //*****************************************************************************
  977. //
  978. //! Transmits a byte from the I2C Slave.
  979. //!
  980. //! \param ulBase is the base address of the I2C Slave module.
  981. //! \param ucData data to be transmitted from the I2C Slave
  982. //!
  983. //! This function will place the supplied data into I2C Slave Data Register.
  984. //!
  985. //! \return None.
  986. //
  987. //*****************************************************************************
  988. void
  989. I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)
  990. {
  991. //
  992. // Check the arguments.
  993. //
  994. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  995. //
  996. // Write the byte.
  997. //
  998. HWREG(ulBase + I2C_O_SDR) = ucData;
  999. }
  1000. //*****************************************************************************
  1001. //
  1002. //! Receives a byte that has been sent to the I2C Slave.
  1003. //!
  1004. //! \param ulBase is the base address of the I2C Slave module.
  1005. //!
  1006. //! This function reads a byte of data from the I2C Slave Data Register.
  1007. //!
  1008. //! \return Returns the byte received from by the I2C Slave, cast as an
  1009. //! unsigned long.
  1010. //
  1011. //*****************************************************************************
  1012. unsigned long
  1013. I2CSlaveDataGet(unsigned long ulBase)
  1014. {
  1015. //
  1016. // Check the arguments.
  1017. //
  1018. ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
  1019. //
  1020. // Read a byte.
  1021. //
  1022. return(HWREG(ulBase + I2C_O_SDR));
  1023. }
  1024. //*****************************************************************************
  1025. //
  1026. // Close the Doxygen group.
  1027. //! @}
  1028. //
  1029. //*****************************************************************************