uart.c 53 KB

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  1. //*****************************************************************************
  2. //
  3. // uart.c - Driver for the UART.
  4. //
  5. // Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
  9. // exclusively on LMI's microcontroller products.
  10. //
  11. // The software is owned by LMI and/or its suppliers, and is protected under
  12. // applicable copyright laws. All rights are reserved. You may not combine
  13. // this software with "viral" open-source software in order to form a larger
  14. // program. Any use in violation of the foregoing restrictions may subject
  15. // the user to criminal sanctions under applicable laws, as well as to civil
  16. // liability for the breach of the terms and conditions of this license.
  17. //
  18. // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  19. // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  20. // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  21. // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  22. // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  23. //
  24. // This is part of revision 4694 of the Stellaris Peripheral Driver Library.
  25. //
  26. //*****************************************************************************
  27. //*****************************************************************************
  28. //
  29. //! \addtogroup uart_api
  30. //! @{
  31. //
  32. //*****************************************************************************
  33. #include "inc/hw_ints.h"
  34. #include "inc/hw_memmap.h"
  35. #include "inc/hw_sysctl.h"
  36. #include "inc/hw_types.h"
  37. #include "inc/hw_uart.h"
  38. #include "driverlib/debug.h"
  39. #include "driverlib/interrupt.h"
  40. #include "driverlib/uart.h"
  41. //*****************************************************************************
  42. //
  43. // The system clock divider defining the maximum baud rate supported by the
  44. // UART.
  45. //
  46. //*****************************************************************************
  47. #define UART_CLK_DIVIDER ((CLASS_IS_SANDSTORM || \
  48. (CLASS_IS_FURY && REVISION_IS_A2) || \
  49. (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \
  50. 16 : 8)
  51. //*****************************************************************************
  52. //
  53. //! \internal
  54. //! Checks a UART base address.
  55. //!
  56. //! \param ulBase is the base address of the UART port.
  57. //!
  58. //! This function determines if a UART port base address is valid.
  59. //!
  60. //! \return Returns \b true if the base address is valid and \b false
  61. //! otherwise.
  62. //
  63. //*****************************************************************************
  64. #ifdef DEBUG
  65. static tBoolean
  66. UARTBaseValid(unsigned long ulBase)
  67. {
  68. return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
  69. (ulBase == UART2_BASE));
  70. }
  71. #endif
  72. //*****************************************************************************
  73. //
  74. //! Sets the type of parity.
  75. //!
  76. //! \param ulBase is the base address of the UART port.
  77. //! \param ulParity specifies the type of parity to use.
  78. //!
  79. //! Sets the type of parity to use for transmitting and expect when receiving.
  80. //! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
  81. //! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
  82. //! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
  83. //! parity bit; it will always be either be one or zero based on the mode.
  84. //!
  85. //! \return None.
  86. //
  87. //*****************************************************************************
  88. void
  89. UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
  90. {
  91. //
  92. // Check the arguments.
  93. //
  94. ASSERT(UARTBaseValid(ulBase));
  95. ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
  96. (ulParity == UART_CONFIG_PAR_EVEN) ||
  97. (ulParity == UART_CONFIG_PAR_ODD) ||
  98. (ulParity == UART_CONFIG_PAR_ONE) ||
  99. (ulParity == UART_CONFIG_PAR_ZERO));
  100. //
  101. // Set the parity mode.
  102. //
  103. HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &
  104. ~(UART_LCRH_SPS | UART_LCRH_EPS |
  105. UART_LCRH_PEN)) | ulParity);
  106. }
  107. //*****************************************************************************
  108. //
  109. //! Gets the type of parity currently being used.
  110. //!
  111. //! \param ulBase is the base address of the UART port.
  112. //!
  113. //! This function gets the type of parity used for transmitting data, and
  114. //! expected when receiving data.
  115. //!
  116. //! \return Returns the current parity settings, specified as one of
  117. //! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
  118. //! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
  119. //
  120. //*****************************************************************************
  121. unsigned long
  122. UARTParityModeGet(unsigned long ulBase)
  123. {
  124. //
  125. // Check the arguments.
  126. //
  127. ASSERT(UARTBaseValid(ulBase));
  128. //
  129. // Return the current parity setting.
  130. //
  131. return(HWREG(ulBase + UART_O_LCRH) &
  132. (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
  133. }
  134. //*****************************************************************************
  135. //
  136. //! Sets the FIFO level at which interrupts are generated.
  137. //!
  138. //! \param ulBase is the base address of the UART port.
  139. //! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of
  140. //! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
  141. //! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
  142. //! \param ulRxLevel is the receive FIFO interrupt level, specified as one of
  143. //! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
  144. //! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
  145. //!
  146. //! This function sets the FIFO level at which transmit and receive interrupts
  147. //! will be generated.
  148. //!
  149. //! \return None.
  150. //
  151. //*****************************************************************************
  152. void
  153. UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
  154. unsigned long ulRxLevel)
  155. {
  156. //
  157. // Check the arguments.
  158. //
  159. ASSERT(UARTBaseValid(ulBase));
  160. ASSERT((ulTxLevel == UART_FIFO_TX1_8) ||
  161. (ulTxLevel == UART_FIFO_TX2_8) ||
  162. (ulTxLevel == UART_FIFO_TX4_8) ||
  163. (ulTxLevel == UART_FIFO_TX6_8) ||
  164. (ulTxLevel == UART_FIFO_TX7_8));
  165. ASSERT((ulRxLevel == UART_FIFO_RX1_8) ||
  166. (ulRxLevel == UART_FIFO_RX2_8) ||
  167. (ulRxLevel == UART_FIFO_RX4_8) ||
  168. (ulRxLevel == UART_FIFO_RX6_8) ||
  169. (ulRxLevel == UART_FIFO_RX7_8));
  170. //
  171. // Set the FIFO interrupt levels.
  172. //
  173. HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel;
  174. }
  175. //*****************************************************************************
  176. //
  177. //! Gets the FIFO level at which interrupts are generated.
  178. //!
  179. //! \param ulBase is the base address of the UART port.
  180. //! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
  181. //! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
  182. //! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or UART_FIFO_TX7_8.
  183. //! \param pulRxLevel is a pointer to storage for the receive FIFO level,
  184. //! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
  185. //! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
  186. //!
  187. //! This function gets the FIFO level at which transmit and receive interrupts
  188. //! will be generated.
  189. //!
  190. //! \return None.
  191. //
  192. //*****************************************************************************
  193. void
  194. UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
  195. unsigned long *pulRxLevel)
  196. {
  197. unsigned long ulTemp;
  198. //
  199. // Check the arguments.
  200. //
  201. ASSERT(UARTBaseValid(ulBase));
  202. //
  203. // Read the FIFO level register.
  204. //
  205. ulTemp = HWREG(ulBase + UART_O_IFLS);
  206. //
  207. // Extract the transmit and receive FIFO levels.
  208. //
  209. *pulTxLevel = ulTemp & UART_IFLS_TX_M;
  210. *pulRxLevel = ulTemp & UART_IFLS_RX_M;
  211. }
  212. //*****************************************************************************
  213. //
  214. //! Sets the configuration of a UART.
  215. //!
  216. //! \param ulBase is the base address of the UART port.
  217. //! \param ulUARTClk is the rate of the clock supplied to the UART module.
  218. //! \param ulBaud is the desired baud rate.
  219. //! \param ulConfig is the data format for the port (number of data bits,
  220. //! number of stop bits, and parity).
  221. //!
  222. //! This function will configure the UART for operation in the specified data
  223. //! format. The baud rate is provided in the \e ulBaud parameter and the data
  224. //! format in the \e ulConfig parameter.
  225. //!
  226. //! The \e ulConfig parameter is the logical OR of three values: the number of
  227. //! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
  228. //! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
  229. //! select from eight to five data bits per byte (respectively).
  230. //! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
  231. //! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
  232. //! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
  233. //! select the parity mode (no parity bit, even parity bit, odd parity bit,
  234. //! parity bit always one, and parity bit always zero, respectively).
  235. //!
  236. //! The peripheral clock will be the same as the processor clock. This will be
  237. //! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
  238. //! if it is constant and known (to save the code/execution overhead of a call
  239. //! to SysCtlClockGet()).
  240. //!
  241. //! This function replaces the original UARTConfigSet() API and performs the
  242. //! same actions. A macro is provided in <tt>uart.h</tt> to map the original
  243. //! API to this API.
  244. //!
  245. //! \return None.
  246. //
  247. //*****************************************************************************
  248. void
  249. UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
  250. unsigned long ulBaud, unsigned long ulConfig)
  251. {
  252. unsigned long ulDiv;
  253. //
  254. // Check the arguments.
  255. //
  256. ASSERT(UARTBaseValid(ulBase));
  257. ASSERT(ulBaud != 0);
  258. ASSERT(ulUARTClk >= (ulBaud * UART_CLK_DIVIDER));
  259. //
  260. // Stop the UART.
  261. //
  262. UARTDisable(ulBase);
  263. //
  264. // Is the required baud rate greater than the maximum rate supported
  265. // without the use of high speed mode?
  266. //
  267. if((ulBaud * 16) > ulUARTClk)
  268. {
  269. //
  270. // Enable high speed mode.
  271. //
  272. HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE;
  273. //
  274. // Half the supplied baud rate to compensate for enabling high speed
  275. // mode. This allows the following code to be common to both cases.
  276. //
  277. ulBaud /= 2;
  278. }
  279. else
  280. {
  281. //
  282. // Disable high speed mode.
  283. //
  284. HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE);
  285. }
  286. //
  287. // Compute the fractional baud rate divider.
  288. //
  289. ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
  290. //
  291. // Set the baud rate.
  292. //
  293. HWREG(ulBase + UART_O_IBRD) = ulDiv / 64;
  294. HWREG(ulBase + UART_O_FBRD) = ulDiv % 64;
  295. //
  296. // Set parity, data length, and number of stop bits.
  297. //
  298. HWREG(ulBase + UART_O_LCRH) = ulConfig;
  299. //
  300. // Clear the flags register.
  301. //
  302. HWREG(ulBase + UART_O_FR) = 0;
  303. //
  304. // Start the UART.
  305. //
  306. UARTEnable(ulBase);
  307. }
  308. //*****************************************************************************
  309. //
  310. //! Gets the current configuration of a UART.
  311. //!
  312. //! \param ulBase is the base address of the UART port.
  313. //! \param ulUARTClk is the rate of the clock supplied to the UART module.
  314. //! \param pulBaud is a pointer to storage for the baud rate.
  315. //! \param pulConfig is a pointer to storage for the data format.
  316. //!
  317. //! The baud rate and data format for the UART is determined, given an
  318. //! explicitly provided peripheral clock (hence the ExpClk suffix). The
  319. //! returned baud rate is the actual baud rate; it may not be the exact baud
  320. //! rate requested or an ``official'' baud rate. The data format returned in
  321. //! \e pulConfig is enumerated the same as the \e ulConfig parameter of
  322. //! UARTConfigSetExpClk().
  323. //!
  324. //! The peripheral clock will be the same as the processor clock. This will be
  325. //! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
  326. //! if it is constant and known (to save the code/execution overhead of a call
  327. //! to SysCtlClockGet()).
  328. //!
  329. //! This function replaces the original UARTConfigGet() API and performs the
  330. //! same actions. A macro is provided in <tt>uart.h</tt> to map the original
  331. //! API to this API.
  332. //!
  333. //! \return None.
  334. //
  335. //*****************************************************************************
  336. void
  337. UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
  338. unsigned long *pulBaud, unsigned long *pulConfig)
  339. {
  340. unsigned long ulInt, ulFrac;
  341. //
  342. // Check the arguments.
  343. //
  344. ASSERT(UARTBaseValid(ulBase));
  345. //
  346. // Compute the baud rate.
  347. //
  348. ulInt = HWREG(ulBase + UART_O_IBRD);
  349. ulFrac = HWREG(ulBase + UART_O_FBRD);
  350. *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
  351. //
  352. // See if high speed mode enabled.
  353. //
  354. if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE)
  355. {
  356. //
  357. // High speed mode is enabled so the actual baud rate is actually
  358. // double what was just calculated.
  359. //
  360. *pulBaud *= 2;
  361. }
  362. //
  363. // Get the parity, data length, and number of stop bits.
  364. //
  365. *pulConfig = (HWREG(ulBase + UART_O_LCRH) &
  366. (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
  367. UART_LCRH_EPS | UART_LCRH_PEN));
  368. }
  369. //*****************************************************************************
  370. //
  371. //! Enables transmitting and receiving.
  372. //!
  373. //! \param ulBase is the base address of the UART port.
  374. //!
  375. //! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
  376. //! FIFOs.
  377. //!
  378. //! \return None.
  379. //
  380. //*****************************************************************************
  381. void
  382. UARTEnable(unsigned long ulBase)
  383. {
  384. //
  385. // Check the arguments.
  386. //
  387. ASSERT(UARTBaseValid(ulBase));
  388. //
  389. // Enable the FIFO.
  390. //
  391. HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
  392. //
  393. // Enable RX, TX, and the UART.
  394. //
  395. HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
  396. UART_CTL_RXE);
  397. }
  398. //*****************************************************************************
  399. //
  400. //! Disables transmitting and receiving.
  401. //!
  402. //! \param ulBase is the base address of the UART port.
  403. //!
  404. //! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
  405. //! transmission of the current character, and flushes the transmit FIFO.
  406. //!
  407. //! \return None.
  408. //
  409. //*****************************************************************************
  410. void
  411. UARTDisable(unsigned long ulBase)
  412. {
  413. //
  414. // Check the arguments.
  415. //
  416. ASSERT(UARTBaseValid(ulBase));
  417. //
  418. // Wait for end of TX.
  419. //
  420. while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
  421. {
  422. }
  423. //
  424. // Disable the FIFO.
  425. //
  426. HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
  427. //
  428. // Disable the UART.
  429. //
  430. HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
  431. UART_CTL_RXE);
  432. }
  433. //*****************************************************************************
  434. //
  435. //! Enables the transmit and receive FIFOs.
  436. //!
  437. //! \param ulBase is the base address of the UART port.
  438. //!
  439. //! This functions enables the transmit and receive FIFOs in the UART.
  440. //!
  441. //! \return None.
  442. //
  443. //*****************************************************************************
  444. void
  445. UARTFIFOEnable(unsigned long ulBase)
  446. {
  447. //
  448. // Check the arguments.
  449. //
  450. ASSERT(UARTBaseValid(ulBase));
  451. //
  452. // Enable the FIFO.
  453. //
  454. HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
  455. }
  456. //*****************************************************************************
  457. //
  458. //! Disables the transmit and receive FIFOs.
  459. //!
  460. //! \param ulBase is the base address of the UART port.
  461. //!
  462. //! This functions disables the transmit and receive FIFOs in the UART.
  463. //!
  464. //! \return None.
  465. //
  466. //*****************************************************************************
  467. void
  468. UARTFIFODisable(unsigned long ulBase)
  469. {
  470. //
  471. // Check the arguments.
  472. //
  473. ASSERT(UARTBaseValid(ulBase));
  474. //
  475. // Disable the FIFO.
  476. //
  477. HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
  478. }
  479. //*****************************************************************************
  480. //
  481. //! Enables SIR (IrDA) mode on the specified UART.
  482. //!
  483. //! \param ulBase is the base address of the UART port.
  484. //! \param bLowPower indicates if SIR Low Power Mode is to be used.
  485. //!
  486. //! Enables the SIREN control bit for IrDA mode on the UART. If the
  487. //! \e bLowPower flag is set, then SIRLP bit will also be set.
  488. //!
  489. //! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
  490. //!
  491. //! \return None.
  492. //
  493. //*****************************************************************************
  494. void
  495. UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
  496. {
  497. //
  498. // Check the arguments.
  499. //
  500. ASSERT(UARTBaseValid(ulBase));
  501. //
  502. // Enable SIR and SIRLP (if appropriate).
  503. //
  504. if(bLowPower)
  505. {
  506. HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP);
  507. }
  508. else
  509. {
  510. HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN);
  511. }
  512. }
  513. //*****************************************************************************
  514. //
  515. //! Disables SIR (IrDA) mode on the specified UART.
  516. //!
  517. //! \param ulBase is the base address of the UART port.
  518. //!
  519. //! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
  520. //!
  521. //! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
  522. //!
  523. //! \return None.
  524. //
  525. //*****************************************************************************
  526. void
  527. UARTDisableSIR(unsigned long ulBase)
  528. {
  529. //
  530. // Check the arguments.
  531. //
  532. ASSERT(UARTBaseValid(ulBase));
  533. //
  534. // Disable SIR and SIRLP (if appropriate).
  535. //
  536. HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP);
  537. }
  538. //*****************************************************************************
  539. //
  540. //! Enables ISO 7816 smart card mode on the specified UART.
  541. //!
  542. //! \param ulBase is the base address of the UART port.
  543. //!
  544. //! Enables the SMART control bit for ISO 7816 smart card mode on the UART.
  545. //! This call also sets 8 bit word length and even parity as required by ISO
  546. //! 7816.
  547. //!
  548. //! \note The availability of ISO 7816 smart card mode varies with the
  549. //! Stellaris part and UART in use. Please consult the datasheet for the part
  550. //! you are using to determine whether this support is available.
  551. //!
  552. //! \return None.
  553. //
  554. //*****************************************************************************
  555. void
  556. UARTSmartCardEnable(unsigned long ulBase)
  557. {
  558. unsigned long ulVal;
  559. //
  560. // Check the arguments.
  561. //
  562. ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
  563. ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
  564. (ulBase == UART2_BASE));
  565. //
  566. // Set 8 bit word length, even parity, 2 stop bits (even though the STP2
  567. // bit is ignored when in smartcard mode, this lets the caller read back
  568. // the actual setting in use).
  569. //
  570. ulVal = HWREG(ulBase + UART_O_LCRH);
  571. ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
  572. UART_LCRH_WLEN_M);
  573. ulVal |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_STP2;
  574. HWREG(ulBase + UART_O_LCRH) = ulVal;
  575. //
  576. // Enable SMART mode.
  577. //
  578. HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART;
  579. }
  580. //*****************************************************************************
  581. //
  582. //! Disables ISO 7816 smart card mode on the specified UART.
  583. //!
  584. //! \param ulBase is the base address of the UART port.
  585. //!
  586. //! Clears the SMART (ISO 7816 smart card) bits in the UART control register.
  587. //!
  588. //! \note The availability of ISO 7816 smart card mode varies with the
  589. //! Stellaris part and UART in use. Please consult the datasheet for the part
  590. //! you are using to determine whether this support is available.
  591. //!
  592. //! \return None.
  593. //
  594. //*****************************************************************************
  595. void
  596. UARTSmartCardDisable(unsigned long ulBase)
  597. {
  598. //
  599. // Check the arguments.
  600. //
  601. ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
  602. ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
  603. (ulBase == UART2_BASE));
  604. //
  605. // Disable the SMART bit.
  606. //
  607. HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART;
  608. }
  609. //*****************************************************************************
  610. //
  611. //! Sets the states of the DTR and/or RTS modem control signals.
  612. //!
  613. //! \param ulBase is the base address of the UART port.
  614. //! \param ulControl is a bit-mapped flag indicating which modem control bits
  615. //! should be set.
  616. //!
  617. //! Sets the states of the DTR or RTS modem handshake outputs from the UART.
  618. //!
  619. //! The \e ulControl parameter is the logical OR of any of the following:
  620. //!
  621. //! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
  622. //! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
  623. //!
  624. //! \note The availability of hardware modem handshake signals varies with the
  625. //! Stellaris part and UART in use. Please consult the datasheet for the part
  626. //! you are using to determine whether this support is available.
  627. //!
  628. //! \return None.
  629. //
  630. //*****************************************************************************
  631. void
  632. UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
  633. {
  634. unsigned long ulTemp;
  635. //
  636. // Check the arguments.
  637. //
  638. ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
  639. ASSERT(ulBase == UART1_BASE);
  640. ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
  641. //
  642. // Set the appropriate modem control output bits.
  643. //
  644. ulTemp = HWREG(ulBase + UART_O_CTL);
  645. ulTemp |= (ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
  646. HWREG(ulBase + UART_O_CTL) = ulTemp;
  647. }
  648. //*****************************************************************************
  649. //
  650. //! Clears the states of the DTR and/or RTS modem control signals.
  651. //!
  652. //! \param ulBase is the base address of the UART port.
  653. //! \param ulControl is a bit-mapped flag indicating which modem control bits
  654. //! should be set.
  655. //!
  656. //! Clears the states of the DTR or RTS modem handshake outputs from the UART.
  657. //!
  658. //! The \e ulControl parameter is the logical OR of any of the following:
  659. //!
  660. //! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
  661. //! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
  662. //!
  663. //! \note The availability of hardware modem handshake signals varies with the
  664. //! Stellaris part and UART in use. Please consult the datasheet for the part
  665. //! you are using to determine whether this support is available.
  666. //!
  667. //! \return None.
  668. //
  669. //*****************************************************************************
  670. void
  671. UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
  672. {
  673. unsigned long ulTemp;
  674. //
  675. // Check the arguments.
  676. //
  677. ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
  678. ASSERT(ulBase == UART1_BASE);
  679. ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
  680. //
  681. // Set the appropriate modem control output bits.
  682. //
  683. ulTemp = HWREG(ulBase + UART_O_CTL);
  684. ulTemp &= ~(ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
  685. HWREG(ulBase + UART_O_CTL) = ulTemp;
  686. }
  687. //*****************************************************************************
  688. //
  689. //! Gets the states of the DTR and RTS modem control signals.
  690. //!
  691. //! \param ulBase is the base address of the UART port.
  692. //!
  693. //! Returns the current states of each of the two UART modem control signals,
  694. //! DTR and RTS.
  695. //!
  696. //! \note The availability of hardware modem handshake signals varies with the
  697. //! Stellaris part and UART in use. Please consult the datasheet for the part
  698. //! you are using to determine whether this support is available.
  699. //!
  700. //! \return Returns the states of the handshake output signals. This will be a
  701. //! logical logical OR combination of values \b UART_OUTPUT_RTS and
  702. //! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
  703. //! associated signal is asserted.
  704. //
  705. //*****************************************************************************
  706. unsigned long
  707. UARTModemControlGet(unsigned long ulBase)
  708. {
  709. //
  710. // Check the arguments.
  711. //
  712. ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
  713. ASSERT(ulBase == UART1_BASE);
  714. return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
  715. }
  716. //*****************************************************************************
  717. //
  718. //! Gets the states of the RI, DCD, DSR and CTS modem status signals.
  719. //!
  720. //! \param ulBase is the base address of the UART port.
  721. //!
  722. //! Returns the current states of each of the four UART modem status signals,
  723. //! RI, DCD, DSR and CTS.
  724. //!
  725. //! \note The availability of hardware modem handshake signals varies with the
  726. //! Stellaris part and UART in use. Please consult the datasheet for the part
  727. //! you are using to determine whether this support is available.
  728. //!
  729. //! \return Returns the states of the handshake output signals. This will be a
  730. //! logical logical OR combination of values \b UART_INPUT_RI, \b
  731. //! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
  732. //! presence of each flag indicates that the associated signal is asserted.
  733. //
  734. //*****************************************************************************
  735. unsigned long
  736. UARTModemStatusGet(unsigned long ulBase)
  737. {
  738. //
  739. // Check the arguments.
  740. //
  741. ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
  742. ASSERT(ulBase == UART1_BASE);
  743. return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD |
  744. UART_INPUT_CTS | UART_INPUT_DSR));
  745. }
  746. //*****************************************************************************
  747. //
  748. //! Sets the UART hardware flow control mode to be used.
  749. //!
  750. //! \param ulBase is the base address of the UART port.
  751. //! \param ulMode indicates the flow control modes to be used. This is a
  752. //! logical OR combination of values \b UART_FLOWCONTROL_TX and \b
  753. //! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
  754. //! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
  755. //!
  756. //! Sets the required hardware flow control modes. If \e ulMode contains
  757. //! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS
  758. //! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX,
  759. //! the RTS output is controlled by the hardware and is asserted only when
  760. //! there is space available in the receive FIFO. If no hardware flow control
  761. //! is required, UART_FLOWCONTROL_NONE should be passed.
  762. //!
  763. //! \note The availability of hardware flow control varies with the Stellaris
  764. //! part and UART in use. Please consult the datasheet for the part you are
  765. //! using to determine whether this support is available.
  766. //!
  767. //! \return None.
  768. //
  769. //*****************************************************************************
  770. void
  771. UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
  772. {
  773. //
  774. // Check the arguments.
  775. //
  776. ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
  777. ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
  778. (ulBase == UART2_BASE));
  779. ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
  780. //
  781. // Set the flow control mode as requested.
  782. //
  783. HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
  784. ~(UART_FLOWCONTROL_TX |
  785. UART_FLOWCONTROL_RX)) | ulMode);
  786. }
  787. //*****************************************************************************
  788. //
  789. //! Returns the UART hardware flow control mode currently in use.
  790. //!
  791. //! \param ulBase is the base address of the UART port.
  792. //!
  793. //! Returns the current hardware flow control mode.
  794. //!
  795. //! \note The availability of hardware flow control varies with the Stellaris
  796. //! part and UART in use. Please consult the datasheet for the part you are
  797. //! using to determine whether this support is available.
  798. //!
  799. //! \return Returns the current flow control mode in use. This is a
  800. //! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
  801. //! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
  802. //! flow control is in use. If hardware flow control is disabled, \b
  803. //! UART_FLOWCONTROL_NONE will be returned.
  804. //
  805. //*****************************************************************************
  806. unsigned long
  807. UARTFlowControlGet(unsigned long ulBase)
  808. {
  809. //
  810. // Check the arguments.
  811. //
  812. ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
  813. ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
  814. (ulBase == UART2_BASE));
  815. return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
  816. UART_FLOWCONTROL_RX));
  817. }
  818. //*****************************************************************************
  819. //
  820. //! Sets the operating mode for the UART transmit interrupt.
  821. //!
  822. //! \param ulBase is the base address of the UART port.
  823. //! \param ulMode is the operating mode for the transmit interrupt. It may be
  824. //! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle
  825. //! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO
  826. //! level.
  827. //!
  828. //! This function allows the mode of the UART transmit interrupt to be set. By
  829. //! default, the transmit interrupt is asserted when the FIFO level falls past
  830. //! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
  831. //! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
  832. //! transmit interrupt will only be asserted once the transmitter is completely
  833. //! idle - the transmit FIFO is empty and all bits, including any stop bits,
  834. //! have cleared the transmitter.
  835. //!
  836. //! \note The availability of end-of-transmission mode varies with the
  837. //! Stellaris part in use. Please consult the datasheet for the part you are
  838. //! using to determine whether this support is available.
  839. //!
  840. //! \return None.
  841. //
  842. //*****************************************************************************
  843. void
  844. UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
  845. {
  846. //
  847. // Check the arguments.
  848. //
  849. ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
  850. (ulBase == UART2_BASE));
  851. ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
  852. (ulMode == UART_TXINT_MODE_FIFO));
  853. //
  854. // Set or clear the EOT bit of the UART control register as appropriate.
  855. //
  856. HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
  857. ~(UART_TXINT_MODE_EOT |
  858. UART_TXINT_MODE_FIFO)) | ulMode);
  859. }
  860. //*****************************************************************************
  861. //
  862. //! Returns the current operating mode for the UART transmit interrupt.
  863. //!
  864. //! \param ulBase is the base address of the UART port.
  865. //!
  866. //! This function returns the current operating mode for the UART transmit
  867. //! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the
  868. //! transmit interrupt is currently set to be asserted once the transmitter is
  869. //! completely idle - the transmit FIFO is empty and all bits, including any
  870. //! stop bits, have cleared the transmitter. The return value will be \b
  871. //! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
  872. //! level of the transmit FIFO.
  873. //!
  874. //! \note The availability of end-of-transmission mode varies with the
  875. //! Stellaris part in use. Please consult the datasheet for the part you are
  876. //! using to determine whether this support is available.
  877. //!
  878. //! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
  879. //
  880. //*****************************************************************************
  881. unsigned long
  882. UARTTxIntModeGet(unsigned long ulBase)
  883. {
  884. //
  885. // Check the arguments.
  886. //
  887. ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
  888. (ulBase == UART2_BASE));
  889. //
  890. // Return the current transmit interrupt mode.
  891. //
  892. return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT |
  893. UART_TXINT_MODE_FIFO));
  894. }
  895. //*****************************************************************************
  896. //
  897. //! Determines if there are any characters in the receive FIFO.
  898. //!
  899. //! \param ulBase is the base address of the UART port.
  900. //!
  901. //! This function returns a flag indicating whether or not there is data
  902. //! available in the receive FIFO.
  903. //!
  904. //! \return Returns \b true if there is data in the receive FIFO, and \b false
  905. //! if there is no data in the receive FIFO.
  906. //
  907. //*****************************************************************************
  908. tBoolean
  909. UARTCharsAvail(unsigned long ulBase)
  910. {
  911. //
  912. // Check the arguments.
  913. //
  914. ASSERT(UARTBaseValid(ulBase));
  915. //
  916. // Return the availability of characters.
  917. //
  918. return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
  919. }
  920. //*****************************************************************************
  921. //
  922. //! Determines if there is any space in the transmit FIFO.
  923. //!
  924. //! \param ulBase is the base address of the UART port.
  925. //!
  926. //! This function returns a flag indicating whether or not there is space
  927. //! available in the transmit FIFO.
  928. //!
  929. //! \return Returns \b true if there is space available in the transmit FIFO,
  930. //! and \b false if there is no space available in the transmit FIFO.
  931. //
  932. //*****************************************************************************
  933. tBoolean
  934. UARTSpaceAvail(unsigned long ulBase)
  935. {
  936. //
  937. // Check the arguments.
  938. //
  939. ASSERT(UARTBaseValid(ulBase));
  940. //
  941. // Return the availability of space.
  942. //
  943. return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
  944. }
  945. //*****************************************************************************
  946. //
  947. //! Receives a character from the specified port.
  948. //!
  949. //! \param ulBase is the base address of the UART port.
  950. //!
  951. //! Gets a character from the receive FIFO for the specified port.
  952. //!
  953. //! This function replaces the original UARTCharNonBlockingGet() API and
  954. //! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
  955. //! the original API to this API.
  956. //!
  957. //! \return Returns the character read from the specified port, cast as a
  958. //! \e long. A \b -1 will be returned if there are no characters present in
  959. //! the receive FIFO. The UARTCharsAvail() function should be called before
  960. //! attempting to call this function.
  961. //
  962. //*****************************************************************************
  963. long
  964. UARTCharGetNonBlocking(unsigned long ulBase)
  965. {
  966. //
  967. // Check the arguments.
  968. //
  969. ASSERT(UARTBaseValid(ulBase));
  970. //
  971. // See if there are any characters in the receive FIFO.
  972. //
  973. if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
  974. {
  975. //
  976. // Read and return the next character.
  977. //
  978. return(HWREG(ulBase + UART_O_DR));
  979. }
  980. else
  981. {
  982. //
  983. // There are no characters, so return a failure.
  984. //
  985. return(-1);
  986. }
  987. }
  988. //*****************************************************************************
  989. //
  990. //! Waits for a character from the specified port.
  991. //!
  992. //! \param ulBase is the base address of the UART port.
  993. //!
  994. //! Gets a character from the receive FIFO for the specified port. If there
  995. //! are no characters available, this function will wait until a character is
  996. //! received before returning.
  997. //!
  998. //! \return Returns the character read from the specified port, cast as an
  999. //! \e long.
  1000. //
  1001. //*****************************************************************************
  1002. long
  1003. UARTCharGet(unsigned long ulBase)
  1004. {
  1005. //
  1006. // Check the arguments.
  1007. //
  1008. ASSERT(UARTBaseValid(ulBase));
  1009. //
  1010. // Wait until a char is available.
  1011. //
  1012. while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
  1013. {
  1014. }
  1015. //
  1016. // Now get the char.
  1017. //
  1018. return(HWREG(ulBase + UART_O_DR));
  1019. }
  1020. //*****************************************************************************
  1021. //
  1022. //! Sends a character to the specified port.
  1023. //!
  1024. //! \param ulBase is the base address of the UART port.
  1025. //! \param ucData is the character to be transmitted.
  1026. //!
  1027. //! Writes the character \e ucData to the transmit FIFO for the specified port.
  1028. //! This function does not block, so if there is no space available, then a
  1029. //! \b false is returned, and the application will have to retry the function
  1030. //! later.
  1031. //!
  1032. //! This function replaces the original UARTCharNonBlockingPut() API and
  1033. //! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
  1034. //! the original API to this API.
  1035. //!
  1036. //! \return Returns \b true if the character was successfully placed in the
  1037. //! transmit FIFO, and \b false if there was no space available in the transmit
  1038. //! FIFO.
  1039. //
  1040. //*****************************************************************************
  1041. tBoolean
  1042. UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
  1043. {
  1044. //
  1045. // Check the arguments.
  1046. //
  1047. ASSERT(UARTBaseValid(ulBase));
  1048. //
  1049. // See if there is space in the transmit FIFO.
  1050. //
  1051. if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
  1052. {
  1053. //
  1054. // Write this character to the transmit FIFO.
  1055. //
  1056. HWREG(ulBase + UART_O_DR) = ucData;
  1057. //
  1058. // Success.
  1059. //
  1060. return(true);
  1061. }
  1062. else
  1063. {
  1064. //
  1065. // There is no space in the transmit FIFO, so return a failure.
  1066. //
  1067. return(false);
  1068. }
  1069. }
  1070. //*****************************************************************************
  1071. //
  1072. //! Waits to send a character from the specified port.
  1073. //!
  1074. //! \param ulBase is the base address of the UART port.
  1075. //! \param ucData is the character to be transmitted.
  1076. //!
  1077. //! Sends the character \e ucData to the transmit FIFO for the specified port.
  1078. //! If there is no space available in the transmit FIFO, this function will
  1079. //! wait until there is space available before returning.
  1080. //!
  1081. //! \return None.
  1082. //
  1083. //*****************************************************************************
  1084. void
  1085. UARTCharPut(unsigned long ulBase, unsigned char ucData)
  1086. {
  1087. //
  1088. // Check the arguments.
  1089. //
  1090. ASSERT(UARTBaseValid(ulBase));
  1091. //
  1092. // Wait until space is available.
  1093. //
  1094. while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
  1095. {
  1096. }
  1097. //
  1098. // Send the char.
  1099. //
  1100. HWREG(ulBase + UART_O_DR) = ucData;
  1101. }
  1102. //*****************************************************************************
  1103. //
  1104. //! Causes a BREAK to be sent.
  1105. //!
  1106. //! \param ulBase is the base address of the UART port.
  1107. //! \param bBreakState controls the output level.
  1108. //!
  1109. //! Calling this function with \e bBreakState set to \b true will assert a
  1110. //! break condition on the UART. Calling this function with \e bBreakState set
  1111. //! to \b false will remove the break condition. For proper transmission of a
  1112. //! break command, the break must be asserted for at least two complete frames.
  1113. //!
  1114. //! \return None.
  1115. //
  1116. //*****************************************************************************
  1117. void
  1118. UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
  1119. {
  1120. //
  1121. // Check the arguments.
  1122. //
  1123. ASSERT(UARTBaseValid(ulBase));
  1124. //
  1125. // Set the break condition as requested.
  1126. //
  1127. HWREG(ulBase + UART_O_LCRH) =
  1128. (bBreakState ?
  1129. (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) :
  1130. (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK)));
  1131. }
  1132. //*****************************************************************************
  1133. //
  1134. //! Determines whether the UART transmitter is busy or not.
  1135. //!
  1136. //! \param ulBase is the base address of the UART port.
  1137. //!
  1138. //! Allows the caller to determine whether all transmitted bytes have cleared
  1139. //! the transmitter hardware. If \b false is returned, the transmit FIFO is
  1140. //! empty and all bits of the last transmitted character, including all stop
  1141. //! bits, have left the hardware shift register.
  1142. //!
  1143. //! \return Returns \b true if the UART is transmitting or \b false if all
  1144. //! transmissions are complete.
  1145. //
  1146. //*****************************************************************************
  1147. tBoolean
  1148. UARTBusy(unsigned long ulBase)
  1149. {
  1150. //
  1151. // Check the argument.
  1152. //
  1153. ASSERT(UARTBaseValid(ulBase));
  1154. //
  1155. // Determine if the UART is busy.
  1156. //
  1157. return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false);
  1158. }
  1159. //*****************************************************************************
  1160. //
  1161. //! Registers an interrupt handler for a UART interrupt.
  1162. //!
  1163. //! \param ulBase is the base address of the UART port.
  1164. //! \param pfnHandler is a pointer to the function to be called when the
  1165. //! UART interrupt occurs.
  1166. //!
  1167. //! This function does the actual registering of the interrupt handler. This
  1168. //! will enable the global interrupt in the interrupt controller; specific UART
  1169. //! interrupts must be enabled via UARTIntEnable(). It is the interrupt
  1170. //! handler's responsibility to clear the interrupt source.
  1171. //!
  1172. //! \sa IntRegister() for important information about registering interrupt
  1173. //! handlers.
  1174. //!
  1175. //! \return None.
  1176. //
  1177. //*****************************************************************************
  1178. void
  1179. UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
  1180. {
  1181. unsigned long ulInt;
  1182. //
  1183. // Check the arguments.
  1184. //
  1185. ASSERT(UARTBaseValid(ulBase));
  1186. //
  1187. // Determine the interrupt number based on the UART port.
  1188. //
  1189. ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
  1190. ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
  1191. //
  1192. // Register the interrupt handler.
  1193. //
  1194. IntRegister(ulInt, pfnHandler);
  1195. //
  1196. // Enable the UART interrupt.
  1197. //
  1198. IntEnable(ulInt);
  1199. }
  1200. //*****************************************************************************
  1201. //
  1202. //! Unregisters an interrupt handler for a UART interrupt.
  1203. //!
  1204. //! \param ulBase is the base address of the UART port.
  1205. //!
  1206. //! This function does the actual unregistering of the interrupt handler. It
  1207. //! will clear the handler to be called when a UART interrupt occurs. This
  1208. //! will also mask off the interrupt in the interrupt controller so that the
  1209. //! interrupt handler no longer is called.
  1210. //!
  1211. //! \sa IntRegister() for important information about registering interrupt
  1212. //! handlers.
  1213. //!
  1214. //! \return None.
  1215. //
  1216. //*****************************************************************************
  1217. void
  1218. UARTIntUnregister(unsigned long ulBase)
  1219. {
  1220. unsigned long ulInt;
  1221. //
  1222. // Check the arguments.
  1223. //
  1224. ASSERT(UARTBaseValid(ulBase));
  1225. //
  1226. // Determine the interrupt number based on the UART port.
  1227. //
  1228. ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
  1229. ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
  1230. //
  1231. // Disable the interrupt.
  1232. //
  1233. IntDisable(ulInt);
  1234. //
  1235. // Unregister the interrupt handler.
  1236. //
  1237. IntUnregister(ulInt);
  1238. }
  1239. //*****************************************************************************
  1240. //
  1241. //! Enables individual UART interrupt sources.
  1242. //!
  1243. //! \param ulBase is the base address of the UART port.
  1244. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
  1245. //!
  1246. //! Enables the indicated UART interrupt sources. Only the sources that are
  1247. //! enabled can be reflected to the processor interrupt; disabled sources have
  1248. //! no effect on the processor.
  1249. //!
  1250. //! The \e ulIntFlags parameter is the logical OR of any of the following:
  1251. //!
  1252. //! - \b UART_INT_OE - Overrun Error interrupt
  1253. //! - \b UART_INT_BE - Break Error interrupt
  1254. //! - \b UART_INT_PE - Parity Error interrupt
  1255. //! - \b UART_INT_FE - Framing Error interrupt
  1256. //! - \b UART_INT_RT - Receive Timeout interrupt
  1257. //! - \b UART_INT_TX - Transmit interrupt
  1258. //! - \b UART_INT_RX - Receive interrupt
  1259. //! - \b UART_INT_DSR - DSR interrupt
  1260. //! - \b UART_INT_DCD - DCD interrupt
  1261. //! - \b UART_INT_CTS - CTS interrupt
  1262. //! - \b UART_INT_RI - RI interrupt
  1263. //!
  1264. //! \return None.
  1265. //
  1266. //*****************************************************************************
  1267. void
  1268. UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
  1269. {
  1270. //
  1271. // Check the arguments.
  1272. //
  1273. ASSERT(UARTBaseValid(ulBase));
  1274. //
  1275. // Enable the specified interrupts.
  1276. //
  1277. HWREG(ulBase + UART_O_IM) |= ulIntFlags;
  1278. }
  1279. //*****************************************************************************
  1280. //
  1281. //! Disables individual UART interrupt sources.
  1282. //!
  1283. //! \param ulBase is the base address of the UART port.
  1284. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
  1285. //!
  1286. //! Disables the indicated UART interrupt sources. Only the sources that are
  1287. //! enabled can be reflected to the processor interrupt; disabled sources have
  1288. //! no effect on the processor.
  1289. //!
  1290. //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
  1291. //! parameter to UARTIntEnable().
  1292. //!
  1293. //! \return None.
  1294. //
  1295. //*****************************************************************************
  1296. void
  1297. UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
  1298. {
  1299. //
  1300. // Check the arguments.
  1301. //
  1302. ASSERT(UARTBaseValid(ulBase));
  1303. //
  1304. // Disable the specified interrupts.
  1305. //
  1306. HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
  1307. }
  1308. //*****************************************************************************
  1309. //
  1310. //! Gets the current interrupt status.
  1311. //!
  1312. //! \param ulBase is the base address of the UART port.
  1313. //! \param bMasked is false if the raw interrupt status is required and true
  1314. //! if the masked interrupt status is required.
  1315. //!
  1316. //! This returns the interrupt status for the specified UART. Either the raw
  1317. //! interrupt status or the status of interrupts that are allowed to reflect to
  1318. //! the processor can be returned.
  1319. //!
  1320. //! \return Returns the current interrupt status, enumerated as a bit field of
  1321. //! values described in UARTIntEnable().
  1322. //
  1323. //*****************************************************************************
  1324. unsigned long
  1325. UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
  1326. {
  1327. //
  1328. // Check the arguments.
  1329. //
  1330. ASSERT(UARTBaseValid(ulBase));
  1331. //
  1332. // Return either the interrupt status or the raw interrupt status as
  1333. // requested.
  1334. //
  1335. if(bMasked)
  1336. {
  1337. return(HWREG(ulBase + UART_O_MIS));
  1338. }
  1339. else
  1340. {
  1341. return(HWREG(ulBase + UART_O_RIS));
  1342. }
  1343. }
  1344. //*****************************************************************************
  1345. //
  1346. //! Clears UART interrupt sources.
  1347. //!
  1348. //! \param ulBase is the base address of the UART port.
  1349. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
  1350. //!
  1351. //! The specified UART interrupt sources are cleared, so that they no longer
  1352. //! assert. This must be done in the interrupt handler to keep it from being
  1353. //! called again immediately upon exit.
  1354. //!
  1355. //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
  1356. //! parameter to UARTIntEnable().
  1357. //!
  1358. //! \note Since there is a write buffer in the Cortex-M3 processor, it may take
  1359. //! several clock cycles before the interrupt source is actually cleared.
  1360. //! Therefore, it is recommended that the interrupt source be cleared early in
  1361. //! the interrupt handler (as opposed to the very last action) to avoid
  1362. //! returning from the interrupt handler before the interrupt source is
  1363. //! actually cleared. Failure to do so may result in the interrupt handler
  1364. //! being immediately reentered (since NVIC still sees the interrupt source
  1365. //! asserted).
  1366. //!
  1367. //! \return None.
  1368. //
  1369. //*****************************************************************************
  1370. void
  1371. UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
  1372. {
  1373. //
  1374. // Check the arguments.
  1375. //
  1376. ASSERT(UARTBaseValid(ulBase));
  1377. //
  1378. // Clear the requested interrupt sources.
  1379. //
  1380. HWREG(ulBase + UART_O_ICR) = ulIntFlags;
  1381. }
  1382. //*****************************************************************************
  1383. //
  1384. //! Enable UART DMA operation.
  1385. //!
  1386. //! \param ulBase is the base address of the UART port.
  1387. //! \param ulDMAFlags is a bit mask of the DMA features to enable.
  1388. //!
  1389. //! The specified UART DMA features are enabled. The UART can be
  1390. //! configured to use DMA for transmit or receive, and to disable
  1391. //! receive if an error occurs. The \e ulDMAFlags parameter is the
  1392. //! logical OR of any of the following values:
  1393. //!
  1394. //! - UART_DMA_RX - enable DMA for receive
  1395. //! - UART_DMA_TX - enable DMA for transmit
  1396. //! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
  1397. //!
  1398. //! \note The uDMA controller must also be set up before DMA can be used
  1399. //! with the UART.
  1400. //!
  1401. //! \return None.
  1402. //
  1403. //*****************************************************************************
  1404. void
  1405. UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
  1406. {
  1407. //
  1408. // Check the arguments.
  1409. //
  1410. ASSERT(UARTBaseValid(ulBase));
  1411. //
  1412. // Set the requested bits in the UART DMA control register.
  1413. //
  1414. HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags;
  1415. }
  1416. //*****************************************************************************
  1417. //
  1418. //! Disable UART DMA operation.
  1419. //!
  1420. //! \param ulBase is the base address of the UART port.
  1421. //! \param ulDMAFlags is a bit mask of the DMA features to disable.
  1422. //!
  1423. //! This function is used to disable UART DMA features that were enabled
  1424. //! by UARTDMAEnable(). The specified UART DMA features are disabled. The
  1425. //! \e ulDMAFlags parameter is the logical OR of any of the following values:
  1426. //!
  1427. //! - UART_DMA_RX - disable DMA for receive
  1428. //! - UART_DMA_TX - disable DMA for transmit
  1429. //! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
  1430. //!
  1431. //! \return None.
  1432. //
  1433. //*****************************************************************************
  1434. void
  1435. UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
  1436. {
  1437. //
  1438. // Check the arguments.
  1439. //
  1440. ASSERT(UARTBaseValid(ulBase));
  1441. //
  1442. // Clear the requested bits in the UART DMA control register.
  1443. //
  1444. HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags;
  1445. }
  1446. //*****************************************************************************
  1447. //
  1448. //! Gets current receiver errors.
  1449. //!
  1450. //! \param ulBase is the base address of the UART port.
  1451. //!
  1452. //! This function returns the current state of each of the 4 receiver error
  1453. //! sources. The returned errors are equivalent to the four error bits
  1454. //! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
  1455. //! with the exception that the overrun error is set immediately the overrun
  1456. //! occurs rather than when a character is next read.
  1457. //!
  1458. //! \return Returns a logical OR combination of the receiver error flags,
  1459. //! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
  1460. //! and \b UART_RXERROR_OVERRUN.
  1461. //
  1462. //*****************************************************************************
  1463. unsigned long
  1464. UARTRxErrorGet(unsigned long ulBase)
  1465. {
  1466. //
  1467. // Check the arguments.
  1468. //
  1469. ASSERT(UARTBaseValid(ulBase));
  1470. //
  1471. // Return the current value of the receive status register.
  1472. //
  1473. return(HWREG(ulBase + UART_O_RSR) & 0x0000000F);
  1474. }
  1475. //*****************************************************************************
  1476. //
  1477. //! Clears all reported receiver errors.
  1478. //!
  1479. //! \param ulBase is the base address of the UART port.
  1480. //!
  1481. //! This function is used to clear all receiver error conditions reported via
  1482. //! UARTRxErrorGet(). If using the overrun, framing error, parity error or
  1483. //! break interrupts, this function must be called after clearing the interrupt
  1484. //! to ensure that later errors of the same type trigger another interrupt.
  1485. //!
  1486. //! \return None.
  1487. //
  1488. //*****************************************************************************
  1489. void
  1490. UARTRxErrorClear(unsigned long ulBase)
  1491. {
  1492. //
  1493. // Check the arguments.
  1494. //
  1495. ASSERT(UARTBaseValid(ulBase));
  1496. //
  1497. // Any write to the Error Clear Register will clear all bits which are
  1498. // currently set.
  1499. //
  1500. HWREG(ulBase + UART_O_ECR) = 0;
  1501. }
  1502. //*****************************************************************************
  1503. //
  1504. // Close the Doxygen group.
  1505. //! @}
  1506. //
  1507. //*****************************************************************************