hw_ssi.h 11 KB

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  1. //*****************************************************************************
  2. //
  3. // hw_ssi.h - Macros used when accessing the SSI hardware.
  4. //
  5. // Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
  9. // exclusively on LMI's microcontroller products.
  10. //
  11. // The software is owned by LMI and/or its suppliers, and is protected under
  12. // applicable copyright laws. All rights are reserved. You may not combine
  13. // this software with "viral" open-source software in order to form a larger
  14. // program. Any use in violation of the foregoing restrictions may subject
  15. // the user to criminal sanctions under applicable laws, as well as to civil
  16. // liability for the breach of the terms and conditions of this license.
  17. //
  18. // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  19. // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  20. // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  21. // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  22. // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  23. //
  24. // This is part of revision 4694 of the Stellaris Firmware Development Package.
  25. //
  26. //*****************************************************************************
  27. #ifndef __HW_SSI_H__
  28. #define __HW_SSI_H__
  29. //*****************************************************************************
  30. //
  31. // The following are defines for the SSI register offsets.
  32. //
  33. //*****************************************************************************
  34. #define SSI_O_CR0 0x00000000 // Control register 0
  35. #define SSI_O_CR1 0x00000004 // Control register 1
  36. #define SSI_O_DR 0x00000008 // Data register
  37. #define SSI_O_SR 0x0000000C // Status register
  38. #define SSI_O_CPSR 0x00000010 // Clock prescale register
  39. #define SSI_O_IM 0x00000014 // Int mask set and clear register
  40. #define SSI_O_RIS 0x00000018 // Raw interrupt register
  41. #define SSI_O_MIS 0x0000001C // Masked interrupt register
  42. #define SSI_O_ICR 0x00000020 // Interrupt clear register
  43. #define SSI_O_DMACTL 0x00000024 // SSI DMA Control
  44. //*****************************************************************************
  45. //
  46. // The following are defines for the bit fields in the SSI Control register 0.
  47. //
  48. //*****************************************************************************
  49. #define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
  50. #define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
  51. #define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
  52. #define SSI_CR0_FRF_M 0x00000030 // Frame format mask
  53. #define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
  54. #define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
  55. #define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
  56. #define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
  57. #define SSI_CR0_DSS_4 0x00000003 // 4 bit data
  58. #define SSI_CR0_DSS_5 0x00000004 // 5 bit data
  59. #define SSI_CR0_DSS_6 0x00000005 // 6 bit data
  60. #define SSI_CR0_DSS_7 0x00000006 // 7 bit data
  61. #define SSI_CR0_DSS_8 0x00000007 // 8 bit data
  62. #define SSI_CR0_DSS_9 0x00000008 // 9 bit data
  63. #define SSI_CR0_DSS_10 0x00000009 // 10 bit data
  64. #define SSI_CR0_DSS_11 0x0000000A // 11 bit data
  65. #define SSI_CR0_DSS_12 0x0000000B // 12 bit data
  66. #define SSI_CR0_DSS_13 0x0000000C // 13 bit data
  67. #define SSI_CR0_DSS_14 0x0000000D // 14 bit data
  68. #define SSI_CR0_DSS_15 0x0000000E // 15 bit data
  69. #define SSI_CR0_DSS_16 0x0000000F // 16 bit data
  70. #define SSI_CR0_SCR_S 8
  71. //*****************************************************************************
  72. //
  73. // The following are defines for the bit fields in the SSI Control register 1.
  74. //
  75. //*****************************************************************************
  76. #define SSI_CR1_EOT 0x00000010 // End of Transmission.
  77. #define SSI_CR1_SOD 0x00000008 // Slave mode output disable
  78. #define SSI_CR1_MS 0x00000004 // Master or slave mode select
  79. #define SSI_CR1_SSE 0x00000002 // Sync serial port enable
  80. #define SSI_CR1_LBM 0x00000001 // Loopback mode
  81. //*****************************************************************************
  82. //
  83. // The following are defines for the bit fields in the SSI Status register.
  84. //
  85. //*****************************************************************************
  86. #define SSI_SR_BSY 0x00000010 // SSI busy
  87. #define SSI_SR_RFF 0x00000008 // RX FIFO full
  88. #define SSI_SR_RNE 0x00000004 // RX FIFO not empty
  89. #define SSI_SR_TNF 0x00000002 // TX FIFO not full
  90. #define SSI_SR_TFE 0x00000001 // TX FIFO empty
  91. //*****************************************************************************
  92. //
  93. // The following are defines for the bit fields in the SSI clock prescale
  94. // register.
  95. //
  96. //*****************************************************************************
  97. #define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
  98. #define SSI_CPSR_CPSDVSR_S 0
  99. //*****************************************************************************
  100. //
  101. // The following are defines for the bit fields in the SSI_O_DR register.
  102. //
  103. //*****************************************************************************
  104. #define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
  105. #define SSI_DR_DATA_S 0
  106. //*****************************************************************************
  107. //
  108. // The following are defines for the bit fields in the SSI_O_IM register.
  109. //
  110. //*****************************************************************************
  111. #define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
  112. // Mask.
  113. #define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
  114. #define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
  115. // Mask.
  116. #define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
  117. // Mask.
  118. //*****************************************************************************
  119. //
  120. // The following are defines for the bit fields in the SSI_O_RIS register.
  121. //
  122. //*****************************************************************************
  123. #define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
  124. // Status.
  125. #define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
  126. // Status.
  127. #define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
  128. // Interrupt Status.
  129. #define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
  130. // Interrupt Status.
  131. //*****************************************************************************
  132. //
  133. // The following are defines for the bit fields in the SSI_O_MIS register.
  134. //
  135. //*****************************************************************************
  136. #define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
  137. // Interrupt Status.
  138. #define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
  139. // Interrupt Status.
  140. #define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
  141. // Interrupt Status.
  142. #define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
  143. // Interrupt Status.
  144. //*****************************************************************************
  145. //
  146. // The following are defines for the bit fields in the SSI_O_ICR register.
  147. //
  148. //*****************************************************************************
  149. #define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
  150. // Clear.
  151. #define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
  152. // Clear.
  153. //*****************************************************************************
  154. //
  155. // The following are defines for the bit fields in the SSI_O_DMACTL register.
  156. //
  157. //*****************************************************************************
  158. #define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
  159. #define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
  160. //*****************************************************************************
  161. //
  162. // The following definitions are deprecated.
  163. //
  164. //*****************************************************************************
  165. #ifndef DEPRECATED
  166. //*****************************************************************************
  167. //
  168. // The following are deprecated defines for the bit fields in the SSI Control
  169. // register 0.
  170. //
  171. //*****************************************************************************
  172. #define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
  173. #define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
  174. #define SSI_CR0_DSS 0x0000000F // Data size select
  175. //*****************************************************************************
  176. //
  177. // The following are deprecated defines for the bit fields in the SSI clock
  178. // prescale register.
  179. //
  180. //*****************************************************************************
  181. #define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
  182. //*****************************************************************************
  183. //
  184. // The following are deprecated defines for the SSI controller's FIFO size.
  185. //
  186. //*****************************************************************************
  187. #define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
  188. #define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
  189. //*****************************************************************************
  190. //
  191. // The following are deprecated defines for the bit fields in the interrupt
  192. // mask set and clear, raw interrupt, masked interrupt, and interrupt clear
  193. // registers.
  194. //
  195. //*****************************************************************************
  196. #define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
  197. #define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
  198. #define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
  199. #define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
  200. #endif
  201. #endif // __HW_SSI_H__