context_gcc.S 4.1 KB

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  1. /*
  2. * File : context_gcc.S
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2009, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2009-10-11 Bernard first version
  13. */
  14. /**
  15. * @addtogroup STM32
  16. */
  17. /*@{*/
  18. .cpu cortex-m3
  19. .fpu softvfp
  20. .syntax unified
  21. .thumb
  22. .text
  23. .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
  24. .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
  25. .equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
  26. .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
  27. /*
  28. * rt_base_t rt_hw_interrupt_disable();
  29. */
  30. .global rt_hw_interrupt_disable
  31. .type rt_hw_interrupt_disable, %function
  32. rt_hw_interrupt_disable:
  33. MRS r0, PRIMASK
  34. CPSID I
  35. BX LR
  36. /*
  37. * void rt_hw_interrupt_enable(rt_base_t level);
  38. */
  39. .global rt_hw_interrupt_enable
  40. .type rt_hw_interrupt_enable, %function
  41. rt_hw_interrupt_enable:
  42. MSR PRIMASK, r0
  43. BX LR
  44. /*
  45. * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
  46. * r0 --> from
  47. * r1 --> to
  48. */
  49. .global rt_hw_context_switch_interrupt
  50. .type rt_hw_context_switch_interrupt, %function
  51. .global rt_hw_context_switch
  52. .type rt_hw_context_switch, %function
  53. rt_hw_context_switch_interrupt:
  54. rt_hw_context_switch:
  55. /* set rt_thread_switch_interrput_flag to 1 */
  56. LDR r2, =rt_thread_switch_interrput_flag
  57. LDR r3, [r2]
  58. CMP r3, #1
  59. BEQ _reswitch
  60. MOV r3, #1
  61. STR r3, [r2]
  62. LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
  63. STR r0, [r2]
  64. _reswitch:
  65. LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
  66. STR r1, [r2]
  67. LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
  68. LDR r1, =NVIC_PENDSVSET
  69. STR r1, [r0]
  70. BX LR
  71. /* r0 --> swith from thread stack
  72. * r1 --> swith to thread stack
  73. * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
  74. */
  75. .global rt_hw_pend_sv
  76. .type rt_hw_pend_sv, %function
  77. rt_hw_pend_sv:
  78. /* disable interrupt to protect context switch */
  79. MRS r2, PRIMASK
  80. CPSID I
  81. /* get rt_thread_switch_interrupt_flag */
  82. LDR r0, =rt_thread_switch_interrput_flag
  83. LDR r1, [r0]
  84. CBZ r1, pendsv_exit /* pendsv already handled */
  85. /* clear rt_thread_switch_interrput_flag to 0 */
  86. MOV r1, #0x00
  87. STR r1, [r0]
  88. LDR r0, =rt_interrupt_from_thread
  89. LDR r1, [r0]
  90. CBZ r1, swtich_to_thread /* skip register save at the first time */
  91. MRS r1, psp /* get from thread stack pointer */
  92. STMFD r1!, {r4 - r11} /* push r4 - r11 register */
  93. LDR r0, [r0]
  94. STR r1, [r0] /* update from thread stack pointer */
  95. swtich_to_thread:
  96. LDR r1, =rt_interrupt_to_thread
  97. LDR r1, [r1]
  98. LDR r1, [r1] /* load thread stack pointer */
  99. LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
  100. MSR psp, r1 /* update stack pointer */
  101. pendsv_exit:
  102. /* restore interrupt */
  103. MSR PRIMASK, r2
  104. ORR lr, lr, #0x04
  105. BX lr
  106. /*
  107. * void rt_hw_context_switch_to(rt_uint32 to);
  108. * r0 --> to
  109. */
  110. .global rt_hw_context_switch_to
  111. .type rt_hw_context_switch_to, %function
  112. rt_hw_context_switch_to:
  113. LDR r1, =rt_interrupt_to_thread
  114. STR r0, [r1]
  115. /* set from thread to 0 */
  116. LDR r1, =rt_interrupt_from_thread
  117. MOV r0, #0x0
  118. STR r0, [r1]
  119. /* set interrupt flag to 1 */
  120. LDR r1, =rt_thread_switch_interrput_flag
  121. MOV r0, #1
  122. STR r0, [r1]
  123. /* set the PendSV exception priority */
  124. LDR r0, =NVIC_SYSPRI2
  125. LDR r1, =NVIC_PENDSV_PRI
  126. STR r1, [r0]
  127. LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
  128. LDR r1, =NVIC_PENDSVSET
  129. STR r1, [r0]
  130. CPSIE I /* enable interrupts at processor level */
  131. /* never reach here! */
  132. /* compatible with old version */
  133. .global rt_hw_interrupt_thread_switch
  134. .type rt_hw_interrupt_thread_switch, %function
  135. rt_hw_interrupt_thread_switch:
  136. BX lr
  137. NOP