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rt-thread
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libcpu
/
mips
/
jz47xx
/
jz47xx.h

jz47xx.h 9.6 KB
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  1. #ifndef __JZ47XX_H__
    2. 

  2. #define __JZ47XX_H__
    3. 

  3. 

  4. #include "../common/mipsregs.h"
    5. 

  5. 

  6. #define __REG8(addr)	*((volatile unsigned char *)(addr))
    7. 

  7. #define __REG16(addr)	*((volatile unsigned short *)(addr))
    8. 

  8. #define __REG32(addr)	*((volatile unsigned int *)(addr))
    9. 

  9. 

  10. #define	HARB_BASE	0xB3000000
    11. 

  11. #define	EMC_BASE	0xB3010000
    12. 

  12. #define	DMAC_BASE	0xB3020000
    13. 

  13. #define	UHC_BASE	0xB3030000
    14. 

  14. #define	UDC_BASE	0xB3040000
    15. 

  15. #define	LCD_BASE	0xB3050000
    16. 

  16. #define	CIM_BASE	0xB3060000
    17. 

  17. #define	ETH_BASE	0xB3100000
    18. 

  18. #define	NBM_BASE	0xB3F00000
    19. 

  19. 

  20. #define	CPM_BASE	0xB0000000
    21. 

  21. #define	INTC_BASE	0xB0001000
    22. 

  22. #define TCU_BASE	0xB0002000
    23. 

  23. #define	RTC_BASE	0xB0003000
    24. 

  24. #define	GPIO_BASE	0xB0010000
    25. 

  25. #define	AIC_BASE	0xB0020000
    26. 

  26. #define	MSC_BASE	0xB0021000
    27. 

  27. #define	UART0_BASE	0xB0030000
    28. 

  28. #define	UART1_BASE	0xB0031000
    29. 

  29. #define	UART2_BASE	0xB0032000
    30. 

  30. #define	UART3_BASE	0xB0033000
    31. 

  31. #define	FIR_BASE	0xB0040000
    32. 

  32. #define	SCC_BASE	0xB0041000
    33. 

  33. #define	SCC0_BASE	0xB0041000
    34. 

  34. #define	I2C_BASE	0xB0042000
    35. 

  35. #define	SSI_BASE	0xB0043000
    36. 

  36. #define	SCC1_BASE	0xB0044000
    37. 

  37. #define	PWM0_BASE	0xB0050000
    38. 

  38. #define	PWM1_BASE	0xB0051000
    39. 

  39. #define	DES_BASE	0xB0060000
    40. 

  40. #define	UPRT_BASE	0xB0061000
    41. 

  41. #define KBC_BASE	0xB0062000
    42. 

  42. 

  43. /* CPM Register */
    44. 

  44. #define CPM_CPCCR			__REG32(CPM_BASE + 0x00)	/* Clock Control Register */
    45. 

  45. #define CPM_LCR				__REG32(CPM_BASE + 0x04)	/* Low Power Control Register */
    46. 

  46. #define CPM_RSR				__REG32(CPM_BASE + 0x08)	/* Reset Status Register */
    47. 

  47. #define CPM_CPPCR			__REG32(CPM_BASE + 0x10)	/* PLL Control Register */
    48. 

  48. #define CPM_CPPSR			__REG32(CPM_BASE + 0x14)	/* PLL Switch and Status Register */
    49. 

  49. #define CPM_CLKGR			__REG32(CPM_BASE + 0x20)	/* Clock Gate Register */
    50. 

  50. #define CPM_OPCR			__REG32(CPM_BASE + 0x24)	/* Osillator and Power Control Register */
    51. 

  51. #define CPM_I2SCDR			__REG32(CPM_BASE + 0x60)	/* I2S Device Clock Divider Register */
    52. 

  52. #define CPM_LPCDR			__REG32(CPM_BASE + 0x64)	/* LCD Pixel Clock Divider Register */
    53. 

  53. #define CPM_MSCCDR			__REG32(CPM_BASE + 0x68)	/* MSC Clock Divider Register */
    54. 

  54. #define CPM_SSICDR			__REG32(CPM_BASE + 0x74)	/* SSI Clock Divider Register */
    55. 

  55. #define CPM_CIMCDR			__REG32(CPM_BASE + 0x7C)	/* CIM MCLK Clock Divider Register */
    56. 

  56. 

  57. /* Interrupt Controller Regester */
    58. 

  58. #define INTC_ISR			__REG32(INTC_BASE + 0x00)
    59. 

  59. #define INTC_IMR			__REG32(INTC_BASE + 0x04)
    60. 

  60. #define INTC_IMSR			__REG32(INTC_BASE + 0x08)
    61. 

  61. #define INTC_IMCR			__REG32(INTC_BASE + 0x0c)
    62. 

  62. #define INTC_IPR			__REG32(INTC_BASE + 0x10)
    63. 

  63. 

  64. /* TCU Register */
    65. 

  65. #define TCU_TSTR			__REG32(TCU_BASE + 0xF0)
    66. 

  66. #define TCU_TSTSR			__REG32(TCU_BASE + 0xF4)
    67. 

  67. #define TCU_TSTCR			__REG32(TCU_BASE + 0xF8)
    68. 

  68. #define TCU_TSR				__REG32(TCU_BASE + 0x1C)
    69. 

  69. #define TCU_TSSR			__REG32(TCU_BASE + 0x2C)
    70. 

  70. #define TCU_TSCR			__REG32(TCU_BASE + 0x3C)
    71. 

  71. #define TCU_TER				__REG32(TCU_BASE + 0x10)
    72. 

  72. #define TCU_TESR			__REG32(TCU_BASE + 0x14)
    73. 

  73. #define TCU_TECR			__REG32(TCU_BASE + 0x18)
    74. 

  74. #define TCU_TFR				__REG32(TCU_BASE + 0x20)
    75. 

  75. #define TCU_TFSR			__REG32(TCU_BASE + 0x24)
    76. 

  76. #define TCU_TFCR			__REG32(TCU_BASE + 0x28)
    77. 

  77. #define TCU_TMR				__REG32(TCU_BASE + 0x30)
    78. 

  78. #define TCU_TMSR			__REG32(TCU_BASE + 0x34)
    79. 

  79. #define TCU_TMCR			__REG32(TCU_BASE + 0x38)
    80. 

  80. #define TCU_TDFR0_OFFSET	0x40
    81. 

  81. #define TCU_TDFR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TDFR0_OFFSET)
    82. 

  82. #define TCU_TDHR0_OFFSET	0x44
    83. 

  83. #define TCU_TDHR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TDHR0_OFFSET)
    84. 

  84. #define TCU_TCNT0_OFFSET	0x48
    85. 

  85. #define TCU_TCNT(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TCNT0_OFFSET)
    86. 

  86. #define TCU_TCSR0_OFFSET	0x4C
    87. 

  87. #define TCU_TCSR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TCSR0_OFFSET)
    88. 

  88. 

  89. /* TCU Register Definitions */
    90. 

  90. #define TCU_TCSR_PWM_SD         (1 << 9)
    91. 

  91. #define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
    92. 

  92. #define TCU_TCSR_PWM_EN         (1 << 7)
    93. 

  93. #define TCU_TCSR_PRESCALE_BIT   3
    94. 

  94. #define TCU_TCSR_PRESCALE_MASK  (0x7 << TCU_TCSR_PRESCALE_BIT)
    95. 

  95. #define TCU_TCSR_PRESCALE1      (0x0 << TCU_TCSR_PRESCALE_BIT)
    96. 

  96. #define TCU_TCSR_PRESCALE4      (0x1 << TCU_TCSR_PRESCALE_BIT)
    97. 

  97. #define TCU_TCSR_PRESCALE16     (0x2 << TCU_TCSR_PRESCALE_BIT)
    98. 

  98. #define TCU_TCSR_PRESCALE64     (0x3 << TCU_TCSR_PRESCALE_BIT)
    99. 

  99. #define TCU_TCSR_PRESCALE256    (0x4 << TCU_TCSR_PRESCALE_BIT)
    100. 

  100. #define TCU_TCSR_PRESCALE1024   (0x5 << TCU_TCSR_PRESCALE_BIT)
    101. 

  101. #define TCU_TCSR_EXT_EN         (1 << 2)
    102. 

  102. #define TCU_TCSR_RTC_EN         (1 << 1)
    103. 

  103. #define TCU_TCSR_PCK_EN         (1 << 0)
    104. 

  104. 

  105. #define TCU_TER_OSTEN   (1 << 15)
    106. 

  106. #define TCU_TER_TCEN5   (1 << 5)
    107. 

  107. #define TCU_TER_TCEN4   (1 << 4)
    108. 

  108. #define TCU_TER_TCEN3   (1 << 3)
    109. 

  109. #define TCU_TER_TCEN2   (1 << 2)
    110. 

  110. #define TCU_TER_TCEN1   (1 << 1)
    111. 

  111. #define TCU_TER_TCEN0   (1 << 0)
    112. 

  112. 

  113. #define TCU_TESR_OSTST  (1 << 15)
    114. 

  114. #define TCU_TESR_TCST5  (1 << 5)
    115. 

  115. #define TCU_TESR_TCST4  (1 << 4)
    116. 

  116. #define TCU_TESR_TCST3  (1 << 3)
    117. 

  117. #define TCU_TESR_TCST2  (1 << 2)
    118. 

  118. #define TCU_TESR_TCST1  (1 << 1)
    119. 

  119. #define TCU_TESR_TCST0  (1 << 0)
    120. 

  120. 

  121. #define TCU_TECR_OSTCL  (1 << 15)
    122. 

  122. #define TCU_TECR_TCCL5  (1 << 5)
    123. 

  123. #define TCU_TECR_TCCL4  (1 << 4)
    124. 

  124. #define TCU_TECR_TCCL3  (1 << 3)
    125. 

  125. #define TCU_TECR_TCCL2  (1 << 2)
    126. 

  126. #define TCU_TECR_TCCL1  (1 << 1)
    127. 

  127. #define TCU_TECR_TCCL0  (1 << 0)
    128. 

  128. 

  129. #define TCU_TFR_HFLAG5  (1 << 21)
    130. 

  130. #define TCU_TFR_HFLAG4  (1 << 20)
    131. 

  131. #define TCU_TFR_HFLAG3  (1 << 19)
    132. 

  132. #define TCU_TFR_HFLAG2  (1 << 18)
    133. 

  133. #define TCU_TFR_HFLAG1  (1 << 17)
    134. 

  134. #define TCU_TFR_HFLAG0  (1 << 16)
    135. 

  135. #define TCU_TFR_FFLAG5  (1 << 5)
    136. 

  136. #define TCU_TFR_FFLAG4  (1 << 4)
    137. 

  137. #define TCU_TFR_FFLAG3  (1 << 3)
    138. 

  138. #define TCU_TFR_FFLAG2  (1 << 2)
    139. 

  139. #define TCU_TFR_FFLAG1  (1 << 1)
    140. 

  140. #define TCU_TFR_FFLAG0  (1 << 0)
    141. 

  141. 

  142. #define TCU_TFSR_HFLAG5 (1 << 21)
    143. 

  143. #define TCU_TFSR_HFLAG4 (1 << 20)
    144. 

  144. #define TCU_TFSR_HFLAG3 (1 << 19)
    145. 

  145. #define TCU_TFSR_HFLAG2 (1 << 18)
    146. 

  146. #define TCU_TFSR_HFLAG1 (1 << 17)
    147. 

  147. #define TCU_TFSR_HFLAG0 (1 << 16)
    148. 

  148. #define TCU_TFSR_OSTFLAG (1 << 15)
    149. 

  149. #define TCU_TFSR_FFLAG5 (1 << 5)
    150. 

  150. #define TCU_TFSR_FFLAG4 (1 << 4)
    151. 

  151. #define TCU_TFSR_FFLAG3 (1 << 3)
    152. 

  152. #define TCU_TFSR_FFLAG2 (1 << 2)
    153. 

  153. #define TCU_TFSR_FFLAG1 (1 << 1)
    154. 

  154. #define TCU_TFSR_FFLAG0 (1 << 0)
    155. 

  155. 

  156. #define TCU_TFCR_HFLAG5 (1 << 21)
    157. 

  157. #define TCU_TFCR_HFLAG4 (1 << 20)
    158. 

  158. #define TCU_TFCR_HFLAG3 (1 << 19)
    159. 

  159. #define TCU_TFCR_HFLAG2 (1 << 18)
    160. 

  160. #define TCU_TFCR_HFLAG1 (1 << 17)
    161. 

  161. #define TCU_TFCR_HFLAG0 (1 << 16)
    162. 

  162. #define TCU_TFCR_OSTFLAG (1 << 15)
    163. 

  163. #define TCU_TFCR_FFLAG5 (1 << 5)
    164. 

  164. #define TCU_TFCR_FFLAG4 (1 << 4)
    165. 

  165. #define TCU_TFCR_FFLAG3 (1 << 3)
    166. 

  166. #define TCU_TFCR_FFLAG2 (1 << 2)
    167. 

  167. #define TCU_TFCR_FFLAG1 (1 << 1)
    168. 

  168. #define TCU_TFCR_FFLAG0 (1 << 0)
    169. 

  169. 

  170. #define TCU_TMR_HMASK5  (1 << 21)
    171. 

  171. #define TCU_TMR_HMASK4  (1 << 20)
    172. 

  172. #define TCU_TMR_HMASK3  (1 << 19)
    173. 

  173. #define TCU_TMR_HMASK2  (1 << 18)
    174. 

  174. #define TCU_TMR_HMASK1  (1 << 17)
    175. 

  175. #define TCU_TMR_HMASK0  (1 << 16)
    176. 

  176. #define TCU_TMR_OSTMASK (1 << 15)
    177. 

  177. #define TCU_TMR_FMASK5  (1 << 5)
    178. 

  178. #define TCU_TMR_FMASK4  (1 << 4)
    179. 

  179. #define TCU_TMR_FMASK3  (1 << 3)
    180. 

  180. #define TCU_TMR_FMASK2  (1 << 2)
    181. 

  181. #define TCU_TMR_FMASK1  (1 << 1)
    182. 

  182. #define TCU_TMR_FMASK0  (1 << 0)
    183. 

  183. 

  184. #define TCU_TMSR_HMST5  (1 << 21)
    185. 

  185. #define TCU_TMSR_HMST4  (1 << 20)
    186. 

  186. #define TCU_TMSR_HMST3  (1 << 19)
    187. 

  187. #define TCU_TMSR_HMST2  (1 << 18)
    188. 

  188. #define TCU_TMSR_HMST1  (1 << 17)
    189. 

  189. #define TCU_TMSR_HMST0  (1 << 16)
    190. 

  190. #define TCU_TMSR_OSTMST (1 << 15)
    191. 

  191. #define TCU_TMSR_FMST5  (1 << 5)
    192. 

  192. #define TCU_TMSR_FMST4  (1 << 4)
    193. 

  193. #define TCU_TMSR_FMST3  (1 << 3)
    194. 

  194. #define TCU_TMSR_FMST2  (1 << 2)
    195. 

  195. #define TCU_TMSR_FMST1  (1 << 1)
    196. 

  196. #define TCU_TMSR_FMST0  (1 << 0)
    197. 

  197. 

  198. #define TCU_TMCR_HMCL5  (1 << 21)
    199. 

  199. #define TCU_TMCR_HMCL4  (1 << 20)
    200. 

  200. #define TCU_TMCR_HMCL3  (1 << 19)
    201. 

  201. #define TCU_TMCR_HMCL2  (1 << 18)
    202. 

  202. #define TCU_TMCR_HMCL1  (1 << 17)
    203. 

  203. #define TCU_TMCR_HMCL0  (1 << 16)
    204. 

  204. #define TCU_TMCR_OSTMCL (1 << 15)
    205. 

  205. #define TCU_TMCR_FMCL5  (1 << 5)
    206. 

  206. #define TCU_TMCR_FMCL4  (1 << 4)
    207. 

  207. #define TCU_TMCR_FMCL3  (1 << 3)
    208. 

  208. #define TCU_TMCR_FMCL2  (1 << 2)
    209. 

  209. #define TCU_TMCR_FMCL1  (1 << 1)
    210. 

  210. #define TCU_TMCR_FMCL0  (1 << 0)
    211. 

  211. 

  212. #define TCU_TSR_WDTS    (1 << 16)
    213. 

  213. #define TCU_TSR_STOP5   (1 << 5)
    214. 

  214. #define TCU_TSR_STOP4   (1 << 4)
    215. 

  215. #define TCU_TSR_STOP3   (1 << 3)
    216. 

  216. #define TCU_TSR_STOP2   (1 << 2)
    217. 

  217. #define TCU_TSR_STOP1   (1 << 1)
    218. 

  218. #define TCU_TSR_STOP0   (1 << 0)
    219. 

  219. 

  220. #define TCU_TSSR_WDTSS  (1 << 16)
    221. 

  221. #define TCU_TSSR_STPS5  (1 << 5)
    222. 

  222. #define TCU_TSSR_STPS4  (1 << 4)
    223. 

  223. #define TCU_TSSR_STPS3  (1 << 3)
    224. 

  224. #define TCU_TSSR_STPS2  (1 << 2)
    225. 

  225. #define TCU_TSSR_STPS1  (1 << 1)
    226. 

  226. #define TCU_TSSR_STPS0  (1 << 0)
    227. 

  227. 

  228. #define TCU_TSSR_WDTSC  (1 << 16)
    229. 

  229. #define TCU_TSSR_STPC5  (1 << 5)
    230. 

  230. #define TCU_TSSR_STPC4  (1 << 4)
    231. 

  231. #define TCU_TSSR_STPC3  (1 << 3)
    232. 

  232. #define TCU_TSSR_STPC2  (1 << 2)
    233. 

  233. #define TCU_TSSR_STPC1  (1 << 1)
    234. 

  234. #define TCU_TSSR_STPC0  (1 << 0)
    235. 

  235. 

  236. #define OST_TCSR_CNT_MD                  ( 1 << 15 )
    237. 

  237. #define OST_TCSR_PWM_SHUT_ABRUPT         ( 1 << 9 )
    238. 

  238. #define OST_TCSR_PRESCALE1               ( 0x0 << 3)
    239. 

  239. #define OST_TCSR_PRESCALE4               ( 0x1 << 3)
    240. 

  240. #define OST_TCSR_PRESCALE16              ( 0x2 << 3)
    241. 

  241. #define OST_TCSR_PRESCALE64              ( 0x3 << 3)
    242. 

  242. #define OST_TCSR_PRESCALE256             ( 0x4 << 3)
    243. 

  243. #define OST_TCSR_PRESCALE1024            ( 0x5 << 3)
    244. 

  244. 

  245. /* Uart Register */
    246. 

  246. #define UART_RDR(base)		__REG8((base) + 0x00)	/* R  8b H'xx */
    247. 

  247. #define UART_TDR(base)		__REG8((base) + 0x00)	/* W  8b H'xx */
    248. 

  248. #define UART_DLLR(base)		__REG8((base) + 0x00)	/* RW 8b H'00 */
    249. 

  249. #define UART_DLHR(base)		__REG8((base) + 0x04)	/* RW 8b H'00 */
    250. 

  250. #define UART_IER(base)		__REG8((base) + 0x04)	/* RW 8b H'00 */
    251. 

  251. #define UART_ISR(base)		__REG8((base) + 0x08)	/* R  8b H'01 */
    252. 

  252. #define UART_FCR(base)		__REG8((base) + 0x08)	/* W  8b H'00 */
    253. 

  253. #define UART_LCR(base)		__REG8((base) + 0x0C)	/* RW 8b H'00 */
    254. 

  254. #define UART_MCR(base)		__REG8((base) + 0x10)	/* RW 8b H'00 */
    255. 

  255. #define UART_LSR(base)		__REG8((base) + 0x14)	/* R  8b H'00 */
    256. 

  256. #define UART_MSR(base)		__REG8((base) + 0x18)	/* R  8b H'00 */
    257. 

  257. #define UART_SPR(base)		__REG8((base) + 0x1C)	/* RW 8b H'00 */
    258. 

  258. #define UART_MCR(base)		__REG8((base) + 0x10)	/* RW 8b H'00 */
    259. 

  259. #define UART_SIRCR(base)	__REG8((base) + 0x20)	/* RW 8b H'00 */
    260. 

  260. 

  261. #define SYSTEM_STACK          0x80003fe8		/* the kernel system stack address */
    262. 

  262. 

  263. #endif
    264.