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mips
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soc3210.h

soc3210.h 6.4 KB
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  1. #ifndef __SOC3210_H__
    2. 

  2. #define __SOC3210_H__
    3. 

  3. 

  4. #include "../common/mipsregs.h"
    5. 

  5. 

  6. /* registers */
    7. 

  7. #define __REG8(addr)		*((volatile unsigned char *)(addr))
    8. 

  8. #define __REG16(addr)		*((volatile unsigned short *)(addr))
    9. 

  9. #define __REG32(addr)		*((volatile unsigned int *)(addr))
    10. 

  10. 

  11. #define EMI_BASE			0xBF000000
    12. 

  12. #define NN_BASE				0xBF000040
    13. 

  13. #define LCD_BASE			0xBF001000
    14. 

  14. #define HSB_MISC_BASE		0xBF003200
    15. 

  15. #define SPI_BASE			0xBF004000
    16. 

  16. #define PS2_BASE			0xBF004040
    17. 

  17. #define UART0_BASE			0xBF004080
    18. 

  18. #define UART1_BASE			0xBF004090
    19. 

  19. #define I2C_BASE			0xBF0040D0
    20. 

  20. #define LPB_MISC_BASE		0xBF004100
    21. 

  21. #define AC97_BASE			0xBF004200
    22. 

  22. #define AC97_DMA_BASE		0xBF004280
    23. 

  23. #define CAN1_BASE			0xBF004300
    24. 

  24. #define CAN0_BASE			0xBF004400
    25. 

  25. #define MAC0_BASE			0xBF005200
    26. 

  26. #define MAC1_BASE			0xBF005300
    27. 

  27. 

  28. /* LCD registers */
    29. 

  29. #define LCD_CTRL			__REG32(LCD_BASE + 0x000)
    30. 

  30. #define LCD_STAT			__REG32(LCD_BASE + 0x004)
    31. 

  31. #define LCD_HTIM			__REG32(LCD_BASE + 0x008)
    32. 

  32. #define LCD_VTIM			__REG32(LCD_BASE + 0x00C)
    33. 

  33. #define LCD_HVLEN			__REG32(LCD_BASE + 0x010)
    34. 

  34. #define LCD_VBARA			__REG32(LCD_BASE + 0x014)
    35. 

  35. #define LCD_VBARB			__REG32(LCD_BASE + 0x018)
    36. 

  36. #define LCD_PCLT			__REG32(LCD_BASE + 0x800)
    37. 

  37. 

  38. /* HSB misc registers */
    39. 

  39. #define HSB_MISC_REG		__REG32(HSB_MISC_BASE + 0x00)
    40. 

  40. #define INT_EDGE			__REG32(HSB_MISC_BASE + 0x04)
    41. 

  41. #define INT_STEER			__REG32(HSB_MISC_BASE + 0x08)
    42. 

  42. #define INT_POL				__REG32(HSB_MISC_BASE + 0x0C)
    43. 

  43. #define INT_SET				__REG32(HSB_MISC_BASE + 0x10)
    44. 

  44. #define INT_CLR				__REG32(HSB_MISC_BASE + 0x14)
    45. 

  45. #define INT_EN				__REG32(HSB_MISC_BASE + 0x18)
    46. 

  46. #define INT_ISR				__REG32(HSB_MISC_BASE + 0x1C)
    47. 

  47. #define GPIO_OE_60_29		__REG32(HSB_MISC_BASE + 0x20)
    48. 

  48. #define GPIO_I_60_29		__REG32(HSB_MISC_BASE + 0x24)
    49. 

  49. #define GPIO_O_60_29		__REG32(HSB_MISC_BASE + 0x28)
    50. 

  50. #define HSB_ARB_CFG			__REG32(HSB_MISC_BASE + 0x2C)
    51. 

  51. #define WD_TIMER			__REG32(HSB_MISC_BASE + 0x30)
    52. 

  52. #define WD_CTRL				__REG32(HSB_MISC_BASE + 0x34)
    53. 

  53. 

  54. /* SPI registers */
    55. 

  55. #define SPI_SPCR			__REG8(SPI_BASE + 0x00)
    56. 

  56. #define SPI_SPSR			__REG8(SPI_BASE + 0x01)
    57. 

  57. #define SPI_TX_FIFO			__REG8(SPI_BASE + 0x02)
    58. 

  58. #define SPI_SPER			__REG8(SPI_BASE + 0x03)
    59. 

  59. 

  60. /* PS/2 registers */
    61. 

  61. #define PS2_RIBUF			__REG8(PS2_BASE + 0x00)
    62. 

  62. #define PS2_WOBUF			__REG8(PS2_BASE + 0x00)
    63. 

  63. #define PS2_RSR				__REG8(PS2_BASE + 0x04)
    64. 

  64. #define PS2_WSC				__REG8(PS2_BASE + 0x04)
    65. 

  65. #define PS2_DLL				__REG8(PS2_BASE + 0x08)
    66. 

  66. #define PS2_DLH				__REG8(PS2_BASE + 0x09)
    67. 

  67. #define PS2_DL_KBD			__REG8(PS2_BASE + 0x0A)
    68. 

  68. #define PS2_DL_AUX			__REG8(PS2_BASE + 0x0B)
    69. 

  69. 

  70. /* UART registers */
    71. 

  71. #define UART_DAT(base)		__REG8(base + 0x00)
    72. 

  72. #define UART_IER(base)		__REG8(base + 0x01)
    73. 

  73. #define UART_IIR(base)		__REG8(base + 0x02)
    74. 

  74. #define UART_FCR(base)		__REG8(base + 0x02)
    75. 

  75. #define UART_LCR(base)		__REG8(base + 0x03)
    76. 

  76. #define UART_MCR(base)		__REG8(base + 0x04)
    77. 

  77. #define UART_LSR(base)		__REG8(base + 0x05)
    78. 

  78. #define UART_MSR(base)		__REG8(base + 0x06)
    79. 

  79. 

  80. #define UART_LSB(base)		__REG8(base + 0x00)
    81. 

  81. #define UART_MSB(base)		__REG8(base + 0x01)
    82. 

  82. 

  83. /* UART0 registers */
    84. 

  84. #define UART0_DAT			__REG8(UART0_BASE + 0x00)
    85. 

  85. #define UART0_IER			__REG8(UART0_BASE + 0x01)
    86. 

  86. #define UART0_IIR			__REG8(UART0_BASE + 0x02)
    87. 

  87. #define UART0_FCR			__REG8(UART0_BASE + 0x02)
    88. 

  88. #define UART0_LCR			__REG8(UART0_BASE + 0x03)
    89. 

  89. #define UART0_MCR			__REG8(UART0_BASE + 0x04)
    90. 

  90. #define UART0_LSR			__REG8(UART0_BASE + 0x05)
    91. 

  91. #define UART0_MSR			__REG8(UART0_BASE + 0x06)
    92. 

  92. 

  93. #define UART0_LSB			__REG8(UART0_BASE + 0x00)
    94. 

  94. #define UART0_MSB			__REG8(UART0_BASE + 0x01)
    95. 

  95. 

  96. /* UART1 registers */
    97. 

  97. #define UART1_DAT			__REG8(UART1_BASE + 0x00)
    98. 

  98. #define UART1_IER			__REG8(UART1_BASE + 0x01)
    99. 

  99. #define UART1_IIR			__REG8(UART1_BASE + 0x02)
    100. 

  100. #define UART1_FCR			__REG8(UART1_BASE + 0x02)
    101. 

  101. #define UART1_LCR			__REG8(UART1_BASE + 0x03)
    102. 

  102. #define UART1_MCR			__REG8(UART1_BASE + 0x04)
    103. 

  103. #define UART1_LSR			__REG8(UART1_BASE + 0x05)
    104. 

  104. #define UART1_MSR			__REG8(UART1_BASE + 0x06)
    105. 

  105. 

  106. #define UART1_LSB			__REG8(UART1_BASE + 0x00)
    107. 

  107. #define UART1_MSB			__REG8(UART1_BASE + 0x01)
    108. 

  108. 

  109. /* LPB misc registers */
    110. 

  110. #define GPIO_OE_7_0			__REG8(LPB_MISC_BASE + 0x00)
    111. 

  111. #define GPIO_OE_15_8		__REG8(LPB_MISC_BASE + 0x01)
    112. 

  112. #define GPIO_OE_23_16		__REG8(LPB_MISC_BASE + 0x02)
    113. 

  113. #define GPIO_OE_28_24		__REG8(LPB_MISC_BASE + 0x03)
    114. 

  114. #define GPIO_I_7_0			__REG8(LPB_MISC_BASE + 0x10)
    115. 

  115. #define GPIO_I_15_8			__REG8(LPB_MISC_BASE + 0x11)
    116. 

  116. #define GPIO_I_23_16		__REG8(LPB_MISC_BASE + 0x12)
    117. 

  117. #define GPIO_I_28_24		__REG8(LPB_MISC_BASE + 0x13)
    118. 

  118. #define GPIO_O_7_0			__REG8(LPB_MISC_BASE + 0x20)
    119. 

  119. #define GPIO_O_15_8			__REG8(LPB_MISC_BASE + 0x21)
    120. 

  120. #define GPIO_O_23_16		__REG8(LPB_MISC_BASE + 0x22)
    121. 

  121. #define GPIO_O_28_24		__REG8(LPB_MISC_BASE + 0x23)
    122. 

  122. #define LPB_MISC_CFG		__REG8(LPB_MISC_BASE + 0x40)
    123. 

  123. 

  124. /* MAC0 registers */
    125. 

  125. #define MAC0_BUS_MODE		__REG32(MAC0_BASE + 0x00)
    126. 

  126. #define MAC0_TX_POLL_REQ	__REG32(MAC0_BASE + 0x08)
    127. 

  127. #define MAC0_RX_POLL_REQ	__REG32(MAC0_BASE + 0x10)
    128. 

  128. #define MAC0_RX_LIST_BASE_ADDR	__REG32(MAC0_BASE + 0x18)
    129. 

  129. #define MAC0_TX_LIST_BASE_ADDR	__REG32(MAC0_BASE + 0x20)
    130. 

  130. #define MAC0_STATUS			__REG32(MAC0_BASE + 0x28)
    131. 

  131. #define MAC0_OP_MODE		__REG32(MAC0_BASE + 0x30)
    132. 

  132. #define MAC0_INTERRUPT_EN	__REG32(MAC0_BASE + 0x38)
    133. 

  133. #define MAC0_MISSED_FRAME_STATISTIC	__REG32(MAC0_BASE + 0x40)
    134. 

  134. #define MAC0_SMI_EEPROM_CTL	__REG32(MAC0_BASE + 0x48)
    135. 

  135. #define MAC0_BYTE_ALIGN		__REG32(MAC0_BASE + 0x50)
    136. 

  136. #define MAC0_GPT_IM_CTL		__REG32(MAC0_BASE + 0x58)
    137. 

  137. 

  138. /* MAC1 registers */
    139. 

  139. #define MAC1_BUS_MODE		__REG32(MAC1_BASE + 0x00)
    140. 

  140. #define MAC1_TX_POLL_REQ	__REG32(MAC1_BASE + 0x08)
    141. 

  141. #define MAC1_RX_POLL_REQ	__REG32(MAC1_BASE + 0x10)
    142. 

  142. #define MAC1_RX_LIST_BASE_ADDR	__REG32(MAC1_BASE + 0x18)
    143. 

  143. #define MAC1_TX_LIST_BASE_ADDR	__REG32(MAC1_BASE + 0x20)
    144. 

  144. #define MAC1_STATUS			__REG32(MAC1_BASE + 0x28)
    145. 

  145. #define MAC1_OP_MODE		__REG32(MAC1_BASE + 0x30)
    146. 

  146. #define MAC1_INTERRUPT_EN	__REG32(MAC1_BASE + 0x38)
    147. 

  147. #define MAC1_MISSED_FRAME_STATISTIC	__REG32(MAC1_BASE + 0x40)
    148. 

  148. #define MAC1_SMI_EEPROM_CTL	__REG32(MAC1_BASE + 0x48)
    149. 

  149. #define MAC1_BYTE_ALIGN		__REG32(MAC1_BASE + 0x50)
    150. 

  150. #define MAC1_GPT_IM_CTL		__REG32(MAC1_BASE + 0x58)
    151. 

  151. 

  152. /* Peripheral Interrupt Number */
    153. 

  153. #define IRQ_LCD				0
    154. 

  154. #define IRQ_MAC1			1
    155. 

  155. #define IRQ_MAC2			2
    156. 

  156. #define IRQ_AC97			3
    157. 

  157. #define IRQ_SPI				8
    158. 

  158. #define IRQ_KEY				9
    159. 

  159. #define IRQ_MOUSE			10
    160. 

  160. #define IRQ_UART0			11
    161. 

  161. #define IRQ_UART1			12
    162. 

  162. #define IRQ_I2C				13
    163. 

  163. #define IRQ_CAN0			14
    164. 

  164. #define IRQ_CAN1			15
    165. 

  165. #define IRQ_GPIO15			20
    166. 

  166. #define IRQ_GPIO14			21
    167. 

  167. #define IRQ_GPIO13			22
    168. 

  168. #define IRQ_GPIO12			23
    169. 

  169. 

  170. #define SYSTEM_STACK		0x80003fe8		/* the kernel system stack address */
    171. 

  171. 

  172. #endif
    173.