drv_can.c 30 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-08-05 Xeon Xu the first version
  9. * 2019-01-22 YLZ port from stm324xx-HAL to bsp stm3210x-HAL
  10. * 2019-02-19 YLZ add support EXTID RTR Frame. modify send, recv functions.
  11. * fix bug.port to BSP [stm32]
  12. * 2019-03-27 YLZ support double can channels, support stm32F4xx (only Legacy mode).
  13. * 2019-06-17 YLZ port to new STM32F1xx HAL V1.1.3.
  14. */
  15. #include "drv_can.h"
  16. #ifdef BSP_USING_CAN
  17. #define LOG_TAG "drv_can"
  18. #include <drv_log.h>
  19. /* attention !!! baud calculation example: Tclk / ((ss + bs1 + bs2) * brp) 36 / ((1 + 8 + 3) * 3) = 1MHz*/
  20. #if defined (SOC_SERIES_STM32F1)/* APB1 36MHz(max) */
  21. static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
  22. {
  23. {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 3)},
  24. {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_5TQ | CAN_BS2_3TQ | 5)},
  25. {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 6)},
  26. {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 12)},
  27. {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 24)},
  28. {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 30)},
  29. {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 60)},
  30. {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 150)},
  31. {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 300)}
  32. };
  33. #elif defined (SOC_SERIES_STM32F4)/* APB1 45MHz(max) */
  34. static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
  35. {
  36. {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 3)},
  37. {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_5TQ | 4)},
  38. {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 6)},
  39. {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 12)},
  40. {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 24)},
  41. {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 30)},
  42. {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 60)},
  43. {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 150)},
  44. {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 300)}
  45. };
  46. #elif defined (SOC_SERIES_STM32F7)/* APB1 54MHz(max) */
  47. static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
  48. {
  49. {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 3)},
  50. {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_7TQ | 4)},
  51. {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 6)},
  52. {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 12)},
  53. {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 24)},
  54. {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 30)},
  55. {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 60)},
  56. {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 150)},
  57. {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 300)}
  58. };
  59. #elif defined (SOC_SERIES_STM32L4)/* APB1 80MHz(max) */
  60. static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
  61. {
  62. {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_5TQ | CAN_BS2_2TQ | 10)},
  63. {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_14TQ | CAN_BS2_5TQ | 5)},
  64. {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_7TQ | CAN_BS2_2TQ | 16)},
  65. {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 20)},
  66. {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 40)},
  67. {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 50)},
  68. {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 100)},
  69. {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 250)},
  70. {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 500)}
  71. };
  72. #endif
  73. #ifdef BSP_USING_CAN1
  74. static struct stm32_can drv_can1 =
  75. {
  76. .name = "can1",
  77. .CanHandle.Instance = CAN1,
  78. };
  79. #endif
  80. #ifdef BSP_USING_CAN2
  81. static struct stm32_can drv_can2 =
  82. {
  83. "can2",
  84. .CanHandle.Instance = CAN2,
  85. };
  86. #endif
  87. static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
  88. {
  89. rt_uint32_t len, index;
  90. len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
  91. for (index = 0; index < len; index++)
  92. {
  93. if (can_baud_rate_tab[index].baud_rate == baud)
  94. return index;
  95. }
  96. return 0; /* default baud is CAN1MBaud */
  97. }
  98. static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg)
  99. {
  100. struct stm32_can *drv_can;
  101. rt_uint32_t baud_index;
  102. RT_ASSERT(can);
  103. RT_ASSERT(cfg);
  104. drv_can = (struct stm32_can *)can->parent.user_data;
  105. RT_ASSERT(drv_can);
  106. drv_can->CanHandle.Init.TimeTriggeredMode = DISABLE;
  107. drv_can->CanHandle.Init.AutoBusOff = ENABLE;
  108. drv_can->CanHandle.Init.AutoWakeUp = DISABLE;
  109. drv_can->CanHandle.Init.AutoRetransmission = DISABLE;
  110. drv_can->CanHandle.Init.ReceiveFifoLocked = DISABLE;
  111. drv_can->CanHandle.Init.TransmitFifoPriority = ENABLE;
  112. switch (cfg->mode)
  113. {
  114. case RT_CAN_MODE_NORMAL:
  115. drv_can->CanHandle.Init.Mode = CAN_MODE_NORMAL;
  116. break;
  117. case RT_CAN_MODE_LISEN:
  118. drv_can->CanHandle.Init.Mode = CAN_MODE_SILENT;
  119. break;
  120. case RT_CAN_MODE_LOOPBACK:
  121. drv_can->CanHandle.Init.Mode = CAN_MODE_LOOPBACK;
  122. break;
  123. case RT_CAN_MODE_LOOPBACKANLISEN:
  124. drv_can->CanHandle.Init.Mode = CAN_MODE_SILENT_LOOPBACK;
  125. break;
  126. }
  127. baud_index = get_can_baud_index(cfg->baud_rate);
  128. drv_can->CanHandle.Init.SyncJumpWidth = BAUD_DATA(SJW, baud_index);
  129. drv_can->CanHandle.Init.TimeSeg1 = BAUD_DATA(BS1, baud_index);
  130. drv_can->CanHandle.Init.TimeSeg2 = BAUD_DATA(BS2, baud_index);
  131. drv_can->CanHandle.Init.Prescaler = BAUD_DATA(RRESCL, baud_index);
  132. /* init can */
  133. if (HAL_CAN_Init(&drv_can->CanHandle) != HAL_OK)
  134. {
  135. return -RT_ERROR;
  136. }
  137. /* default filter config */
  138. HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
  139. /* can start */
  140. HAL_CAN_Start(&drv_can->CanHandle);
  141. return RT_EOK;
  142. }
  143. static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
  144. {
  145. rt_uint32_t argval;
  146. struct stm32_can *drv_can;
  147. struct rt_can_filter_config *filter_cfg;
  148. RT_ASSERT(can != RT_NULL);
  149. drv_can = (struct stm32_can *)can->parent.user_data;
  150. RT_ASSERT(drv_can != RT_NULL);
  151. switch (cmd)
  152. {
  153. case RT_DEVICE_CTRL_CLR_INT:
  154. argval = (rt_uint32_t) arg;
  155. if (argval == RT_DEVICE_FLAG_INT_RX)
  156. {
  157. if (CAN1 == drv_can->CanHandle.Instance)
  158. {
  159. HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
  160. HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);
  161. }
  162. #ifdef CAN2
  163. if (CAN2 == drv_can->CanHandle.Instance)
  164. {
  165. HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);
  166. HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn);
  167. }
  168. #endif
  169. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_MSG_PENDING);
  170. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_FULL);
  171. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_OVERRUN);
  172. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_MSG_PENDING);
  173. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_FULL);
  174. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_OVERRUN);
  175. }
  176. else if (argval == RT_DEVICE_FLAG_INT_TX)
  177. {
  178. if (CAN1 == drv_can->CanHandle.Instance)
  179. {
  180. HAL_NVIC_DisableIRQ(CAN1_TX_IRQn);
  181. }
  182. #ifdef CAN2
  183. if (CAN2 == drv_can->CanHandle.Instance)
  184. {
  185. HAL_NVIC_DisableIRQ(CAN2_TX_IRQn);
  186. }
  187. #endif
  188. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_TX_MAILBOX_EMPTY);
  189. }
  190. else if (argval == RT_DEVICE_CAN_INT_ERR)
  191. {
  192. if (CAN1 == drv_can->CanHandle.Instance)
  193. {
  194. NVIC_DisableIRQ(CAN1_SCE_IRQn);
  195. }
  196. #ifdef CAN2
  197. if (CAN2 == drv_can->CanHandle.Instance)
  198. {
  199. NVIC_DisableIRQ(CAN2_SCE_IRQn);
  200. }
  201. #endif
  202. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_WARNING);
  203. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_PASSIVE);
  204. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_BUSOFF);
  205. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_LAST_ERROR_CODE);
  206. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR);
  207. }
  208. break;
  209. case RT_DEVICE_CTRL_SET_INT:
  210. argval = (rt_uint32_t) arg;
  211. if (argval == RT_DEVICE_FLAG_INT_RX)
  212. {
  213. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_MSG_PENDING);
  214. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_FULL);
  215. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_OVERRUN);
  216. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_MSG_PENDING);
  217. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_FULL);
  218. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_OVERRUN);
  219. if (CAN1 == drv_can->CanHandle.Instance)
  220. {
  221. HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 1, 0);
  222. HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
  223. HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 1, 0);
  224. HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);
  225. }
  226. #ifdef CAN2
  227. if (CAN2 == drv_can->CanHandle.Instance)
  228. {
  229. HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 1, 0);
  230. HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);
  231. HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 1, 0);
  232. HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn);
  233. }
  234. #endif
  235. }
  236. else if (argval == RT_DEVICE_FLAG_INT_TX)
  237. {
  238. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_TX_MAILBOX_EMPTY);
  239. if (CAN1 == drv_can->CanHandle.Instance)
  240. {
  241. HAL_NVIC_SetPriority(CAN1_TX_IRQn, 1, 0);
  242. HAL_NVIC_EnableIRQ(CAN1_TX_IRQn);
  243. }
  244. #ifdef CAN2
  245. if (CAN2 == drv_can->CanHandle.Instance)
  246. {
  247. HAL_NVIC_SetPriority(CAN2_TX_IRQn, 1, 0);
  248. HAL_NVIC_EnableIRQ(CAN2_TX_IRQn);
  249. }
  250. #endif
  251. }
  252. else if (argval == RT_DEVICE_CAN_INT_ERR)
  253. {
  254. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_WARNING);
  255. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_PASSIVE);
  256. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_BUSOFF);
  257. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_LAST_ERROR_CODE);
  258. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR);
  259. if (CAN1 == drv_can->CanHandle.Instance)
  260. {
  261. HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 1, 0);
  262. HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);
  263. }
  264. #ifdef CAN2
  265. if (CAN2 == drv_can->CanHandle.Instance)
  266. {
  267. HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 1, 0);
  268. HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn);
  269. }
  270. #endif
  271. }
  272. break;
  273. case RT_CAN_CMD_SET_FILTER:
  274. if (RT_NULL == arg)
  275. {
  276. /* default filter config */
  277. HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
  278. }
  279. else
  280. {
  281. filter_cfg = (struct rt_can_filter_config *)arg;
  282. /* get default filter */
  283. for (int i = 0; i < filter_cfg->count; i++)
  284. {
  285. drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr;
  286. drv_can->FilterConfig.FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
  287. drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) |
  288. (filter_cfg->items[i].ide << 2) |
  289. (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
  290. drv_can->FilterConfig.FilterMaskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
  291. drv_can->FilterConfig.FilterMaskIdLow = filter_cfg->items[i].mask & 0xFFFF;
  292. drv_can->FilterConfig.FilterMode = filter_cfg->items[i].mode;
  293. /* Filter conf */
  294. HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
  295. }
  296. }
  297. break;
  298. case RT_CAN_CMD_SET_MODE:
  299. argval = (rt_uint32_t) arg;
  300. if (argval != RT_CAN_MODE_NORMAL &&
  301. argval != RT_CAN_MODE_LISEN &&
  302. argval != RT_CAN_MODE_LOOPBACK &&
  303. argval != RT_CAN_MODE_LOOPBACKANLISEN)
  304. {
  305. return -RT_ERROR;
  306. }
  307. if (argval != drv_can->device.config.mode)
  308. {
  309. drv_can->device.config.mode = argval;
  310. return _can_config(&drv_can->device, &drv_can->device.config);
  311. }
  312. break;
  313. case RT_CAN_CMD_SET_BAUD:
  314. argval = (rt_uint32_t) arg;
  315. if (argval != CAN1MBaud &&
  316. argval != CAN800kBaud &&
  317. argval != CAN500kBaud &&
  318. argval != CAN250kBaud &&
  319. argval != CAN125kBaud &&
  320. argval != CAN100kBaud &&
  321. argval != CAN50kBaud &&
  322. argval != CAN20kBaud &&
  323. argval != CAN10kBaud)
  324. {
  325. return -RT_ERROR;
  326. }
  327. if (argval != drv_can->device.config.baud_rate)
  328. {
  329. drv_can->device.config.baud_rate = argval;
  330. return _can_config(&drv_can->device, &drv_can->device.config);
  331. }
  332. break;
  333. case RT_CAN_CMD_SET_PRIV:
  334. argval = (rt_uint32_t) arg;
  335. if (argval != RT_CAN_MODE_PRIV &&
  336. argval != RT_CAN_MODE_NOPRIV)
  337. {
  338. return -RT_ERROR;
  339. }
  340. if (argval != drv_can->device.config.privmode)
  341. {
  342. drv_can->device.config.privmode = argval;
  343. return _can_config(&drv_can->device, &drv_can->device.config);
  344. }
  345. break;
  346. case RT_CAN_CMD_GET_STATUS:
  347. {
  348. rt_uint32_t errtype;
  349. errtype = drv_can->CanHandle.Instance->ESR;
  350. drv_can->device.status.rcverrcnt = errtype >> 24;
  351. drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF);
  352. drv_can->device.status.lasterrtype = errtype & 0x70;
  353. drv_can->device.status.errcode = errtype & 0x07;
  354. rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status));
  355. }
  356. break;
  357. }
  358. return RT_EOK;
  359. }
  360. static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
  361. {
  362. CAN_HandleTypeDef *hcan;
  363. hcan = &((struct stm32_can *) can->parent.user_data)->CanHandle;
  364. struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
  365. CAN_TxHeaderTypeDef txheader = {0};
  366. HAL_CAN_StateTypeDef state = hcan->State;
  367. /* Check the parameters */
  368. RT_ASSERT(IS_CAN_DLC(pmsg->len));
  369. if ((state == HAL_CAN_STATE_READY) ||
  370. (state == HAL_CAN_STATE_LISTENING))
  371. {
  372. /*check select mailbox is empty */
  373. switch (1 << box_num)
  374. {
  375. case CAN_TX_MAILBOX0:
  376. if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0) != SET)
  377. {
  378. /* Change CAN state */
  379. hcan->State = HAL_CAN_STATE_ERROR;
  380. /* Return function status */
  381. return -RT_ERROR;
  382. }
  383. break;
  384. case CAN_TX_MAILBOX1:
  385. if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1) != SET)
  386. {
  387. /* Change CAN state */
  388. hcan->State = HAL_CAN_STATE_ERROR;
  389. /* Return function status */
  390. return -RT_ERROR;
  391. }
  392. break;
  393. case CAN_TX_MAILBOX2:
  394. if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2) != SET)
  395. {
  396. /* Change CAN state */
  397. hcan->State = HAL_CAN_STATE_ERROR;
  398. /* Return function status */
  399. return -RT_ERROR;
  400. }
  401. break;
  402. default:
  403. RT_ASSERT(0);
  404. break;
  405. }
  406. if (RT_CAN_STDID == pmsg->ide)
  407. {
  408. txheader.IDE = CAN_ID_STD;
  409. RT_ASSERT(IS_CAN_STDID(pmsg->id));
  410. txheader.StdId = pmsg->id;
  411. }
  412. else
  413. {
  414. txheader.IDE = CAN_ID_EXT;
  415. RT_ASSERT(IS_CAN_EXTID(pmsg->id));
  416. txheader.ExtId = pmsg->id;
  417. }
  418. if (RT_CAN_DTR == pmsg->rtr)
  419. {
  420. txheader.RTR = CAN_RTR_DATA;
  421. }
  422. else
  423. {
  424. txheader.RTR = CAN_RTR_REMOTE;
  425. }
  426. /* clear TIR */
  427. hcan->Instance->sTxMailBox[box_num].TIR &= CAN_TI0R_TXRQ;
  428. /* Set up the Id */
  429. if (RT_CAN_STDID == pmsg->ide)
  430. {
  431. hcan->Instance->sTxMailBox[box_num].TIR |= (txheader.StdId << CAN_TI0R_STID_Pos) | txheader.RTR;
  432. }
  433. else
  434. {
  435. hcan->Instance->sTxMailBox[box_num].TIR |= (txheader.ExtId << CAN_TI0R_EXID_Pos) | txheader.IDE | txheader.RTR;
  436. }
  437. /* Set up the DLC */
  438. hcan->Instance->sTxMailBox[box_num].TDTR = pmsg->len & 0x0FU;
  439. /* Set up the data field */
  440. WRITE_REG(hcan->Instance->sTxMailBox[box_num].TDHR,
  441. ((uint32_t)pmsg->data[7] << CAN_TDH0R_DATA7_Pos) |
  442. ((uint32_t)pmsg->data[6] << CAN_TDH0R_DATA6_Pos) |
  443. ((uint32_t)pmsg->data[5] << CAN_TDH0R_DATA5_Pos) |
  444. ((uint32_t)pmsg->data[4] << CAN_TDH0R_DATA4_Pos));
  445. WRITE_REG(hcan->Instance->sTxMailBox[box_num].TDLR,
  446. ((uint32_t)pmsg->data[3] << CAN_TDL0R_DATA3_Pos) |
  447. ((uint32_t)pmsg->data[2] << CAN_TDL0R_DATA2_Pos) |
  448. ((uint32_t)pmsg->data[1] << CAN_TDL0R_DATA1_Pos) |
  449. ((uint32_t)pmsg->data[0] << CAN_TDL0R_DATA0_Pos));
  450. /* Request transmission */
  451. SET_BIT(hcan->Instance->sTxMailBox[box_num].TIR, CAN_TI0R_TXRQ);
  452. return RT_EOK;
  453. }
  454. else
  455. {
  456. /* Update error code */
  457. hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
  458. return -RT_ERROR;
  459. }
  460. }
  461. static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
  462. {
  463. HAL_StatusTypeDef status;
  464. CAN_HandleTypeDef *hcan;
  465. struct rt_can_msg *pmsg;
  466. CAN_RxHeaderTypeDef rxheader = {0};
  467. RT_ASSERT(can);
  468. hcan = &((struct stm32_can *)can->parent.user_data)->CanHandle;
  469. pmsg = (struct rt_can_msg *) buf;
  470. /* get data */
  471. status = HAL_CAN_GetRxMessage(hcan, fifo, &rxheader, pmsg->data);
  472. if (HAL_OK != status)
  473. return -RT_ERROR;
  474. /* get id */
  475. if (CAN_ID_STD == rxheader.IDE)
  476. {
  477. pmsg->ide = RT_CAN_STDID;
  478. pmsg->id = rxheader.StdId;
  479. }
  480. else
  481. {
  482. pmsg->ide = RT_CAN_EXTID;
  483. pmsg->id = rxheader.ExtId;
  484. }
  485. /* get type */
  486. if (CAN_RTR_DATA == rxheader.RTR)
  487. {
  488. pmsg->rtr = RT_CAN_DTR;
  489. }
  490. else
  491. {
  492. pmsg->rtr = RT_CAN_RTR;
  493. }
  494. /* get len */
  495. pmsg->len = rxheader.DLC;
  496. /* get hdr */
  497. if (hcan->Instance == CAN1)
  498. {
  499. pmsg->hdr = (rxheader.FilterMatchIndex + 1) >> 1;
  500. }
  501. #ifdef CAN2
  502. else if (hcan->Instance == CAN2)
  503. {
  504. pmsg->hdr = (rxheader.FilterMatchIndex >> 1) + 14;
  505. }
  506. #endif
  507. return RT_EOK;
  508. }
  509. static const struct rt_can_ops _can_ops =
  510. {
  511. _can_config,
  512. _can_control,
  513. _can_sendmsg,
  514. _can_recvmsg,
  515. };
  516. static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo)
  517. {
  518. CAN_HandleTypeDef *hcan;
  519. RT_ASSERT(can);
  520. hcan = &((struct stm32_can *) can->parent.user_data)->CanHandle;
  521. switch (fifo)
  522. {
  523. case CAN_RX_FIFO0:
  524. /* save to user list */
  525. if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_MSG_PENDING))
  526. {
  527. rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
  528. }
  529. /* Check FULL flag for FIFO0 */
  530. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FF0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_FULL))
  531. {
  532. /* Clear FIFO0 FULL Flag */
  533. __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
  534. }
  535. /* Check Overrun flag for FIFO0 */
  536. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_OVERRUN))
  537. {
  538. /* Clear FIFO0 Overrun Flag */
  539. __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
  540. rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
  541. }
  542. break;
  543. case CAN_RX_FIFO1:
  544. /* save to user list */
  545. if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_MSG_PENDING))
  546. {
  547. rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
  548. }
  549. /* Check FULL flag for FIFO1 */
  550. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FF1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_FULL))
  551. {
  552. /* Clear FIFO1 FULL Flag */
  553. __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
  554. }
  555. /* Check Overrun flag for FIFO1 */
  556. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_OVERRUN))
  557. {
  558. /* Clear FIFO1 Overrun Flag */
  559. __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
  560. rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
  561. }
  562. break;
  563. }
  564. }
  565. #ifdef BSP_USING_CAN1
  566. /**
  567. * @brief This function handles CAN1 TX interrupts. transmit fifo0/1/2 is empty can trigger this interrupt
  568. */
  569. void CAN1_TX_IRQHandler(void)
  570. {
  571. rt_interrupt_enter();
  572. CAN_HandleTypeDef *hcan;
  573. hcan = &drv_can1.CanHandle;
  574. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP0))
  575. {
  576. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0))
  577. {
  578. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
  579. }
  580. else
  581. {
  582. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
  583. }
  584. /* Write 0 to Clear transmission status flag RQCPx */
  585. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0);
  586. }
  587. else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP1))
  588. {
  589. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1))
  590. {
  591. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
  592. }
  593. else
  594. {
  595. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
  596. }
  597. /* Write 0 to Clear transmission status flag RQCPx */
  598. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP1);
  599. }
  600. else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP2))
  601. {
  602. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))
  603. {
  604. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
  605. }
  606. else
  607. {
  608. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
  609. }
  610. /* Write 0 to Clear transmission status flag RQCPx */
  611. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP2);
  612. }
  613. rt_interrupt_leave();
  614. }
  615. /**
  616. * @brief This function handles CAN1 RX0 interrupts.
  617. */
  618. void CAN1_RX0_IRQHandler(void)
  619. {
  620. rt_interrupt_enter();
  621. _can_rx_isr(&drv_can1.device, CAN_RX_FIFO0);
  622. rt_interrupt_leave();
  623. }
  624. /**
  625. * @brief This function handles CAN1 RX1 interrupts.
  626. */
  627. void CAN1_RX1_IRQHandler(void)
  628. {
  629. rt_interrupt_enter();
  630. _can_rx_isr(&drv_can1.device, CAN_RX_FIFO1);
  631. rt_interrupt_leave();
  632. }
  633. /**
  634. * @brief This function handles CAN1 SCE interrupts.
  635. */
  636. void CAN1_SCE_IRQHandler(void)
  637. {
  638. rt_uint32_t errtype;
  639. CAN_HandleTypeDef *hcan;
  640. hcan = &drv_can1.CanHandle;
  641. errtype = hcan->Instance->ESR;
  642. rt_interrupt_enter();
  643. HAL_CAN_IRQHandler(hcan);
  644. switch ((errtype & 0x70) >> 4)
  645. {
  646. case RT_CAN_BUS_BIT_PAD_ERR:
  647. drv_can1.device.status.bitpaderrcnt++;
  648. break;
  649. case RT_CAN_BUS_FORMAT_ERR:
  650. drv_can1.device.status.formaterrcnt++;
  651. break;
  652. case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */
  653. drv_can1.device.status.ackerrcnt++;
  654. if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
  655. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
  656. else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK1))
  657. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
  658. else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK2))
  659. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
  660. break;
  661. case RT_CAN_BUS_IMPLICIT_BIT_ERR:
  662. case RT_CAN_BUS_EXPLICIT_BIT_ERR:
  663. drv_can1.device.status.biterrcnt++;
  664. break;
  665. case RT_CAN_BUS_CRC_ERR:
  666. drv_can1.device.status.crcerrcnt++;
  667. break;
  668. }
  669. drv_can1.device.status.lasterrtype = errtype & 0x70;
  670. drv_can1.device.status.rcverrcnt = errtype >> 24;
  671. drv_can1.device.status.snderrcnt = (errtype >> 16 & 0xFF);
  672. drv_can1.device.status.errcode = errtype & 0x07;
  673. hcan->Instance->MSR |= CAN_MSR_ERRI;
  674. rt_interrupt_leave();
  675. }
  676. #endif /* BSP_USING_CAN1 */
  677. #ifdef BSP_USING_CAN2
  678. /**
  679. * @brief This function handles CAN2 TX interrupts.
  680. */
  681. void CAN2_TX_IRQHandler(void)
  682. {
  683. rt_interrupt_enter();
  684. CAN_HandleTypeDef *hcan;
  685. hcan = &drv_can2.CanHandle;
  686. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP0))
  687. {
  688. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0))
  689. {
  690. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
  691. }
  692. else
  693. {
  694. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
  695. }
  696. /* Write 0 to Clear transmission status flag RQCPx */
  697. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0);
  698. }
  699. else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP1))
  700. {
  701. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1))
  702. {
  703. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
  704. }
  705. else
  706. {
  707. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
  708. }
  709. /* Write 0 to Clear transmission status flag RQCPx */
  710. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP1);
  711. }
  712. else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP2))
  713. {
  714. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))
  715. {
  716. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
  717. }
  718. else
  719. {
  720. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
  721. }
  722. /* Write 0 to Clear transmission status flag RQCPx */
  723. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP2);
  724. }
  725. rt_interrupt_leave();
  726. }
  727. /**
  728. * @brief This function handles CAN2 RX0 interrupts.
  729. */
  730. void CAN2_RX0_IRQHandler(void)
  731. {
  732. rt_interrupt_enter();
  733. _can_rx_isr(&drv_can2.device, CAN_RX_FIFO0);
  734. rt_interrupt_leave();
  735. }
  736. /**
  737. * @brief This function handles CAN2 RX1 interrupts.
  738. */
  739. void CAN2_RX1_IRQHandler(void)
  740. {
  741. rt_interrupt_enter();
  742. _can_rx_isr(&drv_can2.device, CAN_RX_FIFO1);
  743. rt_interrupt_leave();
  744. }
  745. /**
  746. * @brief This function handles CAN2 SCE interrupts.
  747. */
  748. void CAN2_SCE_IRQHandler(void)
  749. {
  750. rt_uint32_t errtype;
  751. CAN_HandleTypeDef *hcan;
  752. hcan = &drv_can2.CanHandle;
  753. errtype = hcan->Instance->ESR;
  754. rt_interrupt_enter();
  755. HAL_CAN_IRQHandler(hcan);
  756. switch ((errtype & 0x70) >> 4)
  757. {
  758. case RT_CAN_BUS_BIT_PAD_ERR:
  759. drv_can2.device.status.bitpaderrcnt++;
  760. break;
  761. case RT_CAN_BUS_FORMAT_ERR:
  762. drv_can2.device.status.formaterrcnt++;
  763. break;
  764. case RT_CAN_BUS_ACK_ERR:
  765. drv_can2.device.status.ackerrcnt++;
  766. if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
  767. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
  768. else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK1))
  769. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
  770. else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK2))
  771. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
  772. break;
  773. case RT_CAN_BUS_IMPLICIT_BIT_ERR:
  774. case RT_CAN_BUS_EXPLICIT_BIT_ERR:
  775. drv_can2.device.status.biterrcnt++;
  776. break;
  777. case RT_CAN_BUS_CRC_ERR:
  778. drv_can2.device.status.crcerrcnt++;
  779. break;
  780. }
  781. drv_can2.device.status.lasterrtype = errtype & 0x70;
  782. drv_can2.device.status.rcverrcnt = errtype >> 24;
  783. drv_can2.device.status.snderrcnt = (errtype >> 16 & 0xFF);
  784. drv_can2.device.status.errcode = errtype & 0x07;
  785. hcan->Instance->MSR |= CAN_MSR_ERRI;
  786. rt_interrupt_leave();
  787. }
  788. #endif /* BSP_USING_CAN2 */
  789. /**
  790. * @brief Error CAN callback.
  791. * @param hcan pointer to a CAN_HandleTypeDef structure that contains
  792. * the configuration information for the specified CAN.
  793. * @retval None
  794. */
  795. void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
  796. {
  797. __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERROR_WARNING |
  798. CAN_IT_ERROR_PASSIVE |
  799. CAN_IT_BUSOFF |
  800. CAN_IT_LAST_ERROR_CODE |
  801. CAN_IT_ERROR |
  802. CAN_IT_RX_FIFO0_MSG_PENDING |
  803. CAN_IT_RX_FIFO0_OVERRUN |
  804. CAN_IT_RX_FIFO0_FULL |
  805. CAN_IT_RX_FIFO1_MSG_PENDING |
  806. CAN_IT_RX_FIFO1_OVERRUN |
  807. CAN_IT_RX_FIFO1_FULL |
  808. CAN_IT_TX_MAILBOX_EMPTY);
  809. }
  810. int rt_hw_can_init(void)
  811. {
  812. struct can_configure config = CANDEFAULTCONFIG;
  813. config.privmode = RT_CAN_MODE_NOPRIV;
  814. config.ticks = 50;
  815. #ifdef RT_CAN_USING_HDR
  816. config.maxhdr = 14;
  817. #ifdef CAN2
  818. config.maxhdr = 28;
  819. #endif
  820. #endif
  821. /* config default filter */
  822. CAN_FilterTypeDef filterConf = {0};
  823. filterConf.FilterIdHigh = 0x0000;
  824. filterConf.FilterIdLow = 0x0000;
  825. filterConf.FilterMaskIdHigh = 0x0000;
  826. filterConf.FilterMaskIdLow = 0x0000;
  827. filterConf.FilterFIFOAssignment = CAN_FILTER_FIFO0;
  828. filterConf.FilterBank = 0;
  829. filterConf.FilterMode = CAN_FILTERMODE_IDMASK;
  830. filterConf.FilterScale = CAN_FILTERSCALE_32BIT;
  831. filterConf.FilterActivation = ENABLE;
  832. filterConf.SlaveStartFilterBank = 14;
  833. #ifdef BSP_USING_CAN1
  834. filterConf.FilterBank = 0;
  835. drv_can1.FilterConfig = filterConf;
  836. drv_can1.device.config = config;
  837. /* register CAN1 device */
  838. rt_hw_can_register(&drv_can1.device,
  839. drv_can1.name,
  840. &_can_ops,
  841. &drv_can1);
  842. #endif /* BSP_USING_CAN1 */
  843. #ifdef BSP_USING_CAN2
  844. filterConf.FilterBank = filterConf.SlaveStartFilterBank;
  845. drv_can2.FilterConfig = filterConf;
  846. drv_can2.device.config = config;
  847. /* register CAN2 device */
  848. rt_hw_can_register(&drv_can2.device,
  849. drv_can2.name,
  850. &_can_ops,
  851. &drv_can2);
  852. #endif /* BSP_USING_CAN2 */
  853. return 0;
  854. }
  855. INIT_BOARD_EXPORT(rt_hw_can_init);
  856. #endif /* BSP_USING_CAN */
  857. /************************** end of file ******************/