cmem7_flash.c 10 KB

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  1. /**
  2. *****************************************************************************
  3. * @file cmem7_flash.c
  4. *
  5. * @brief CMEM7 flash controller source file
  6. *
  7. *
  8. * @version V1.0
  9. * @date 3. September 2013
  10. *
  11. * @note
  12. *
  13. *****************************************************************************
  14. * @attention
  15. *
  16. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  17. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  18. * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  19. * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  20. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  21. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  22. *
  23. * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
  24. *****************************************************************************
  25. */
  26. #include "cmem7_flash.h"
  27. typedef struct {
  28. union {
  29. uint16_t STATUS; /*!< status register */
  30. struct {
  31. uint16_t WIP: 1; /*!< in writting */
  32. uint16_t WEL: 1; /*!< write enable */
  33. uint16_t BP: 5; /*!< protection region */
  34. uint16_t SRP: 2; /*!< protection mode */
  35. uint16_t QE: 1; /*!< Quad mode */
  36. } STATUS_b; /*!< BitSize */
  37. } INNER;
  38. } FLASH_INNER_STATUS;
  39. #define NS_IN_A_SECOND (1000000000)
  40. #define FLASH_MAX_SIZE 0x800000
  41. #define FLASH_PAGE_SIZE 0x100
  42. #define FLASH_SECTOR_SIZE 0x001000
  43. #define FLASH_BLOCK_32K_SIZE 0x008000
  44. #define FLASH_BLOCK_64K_SIZE 0x010000
  45. #define FLASH_CMD_RD_INNER_STATUS_LOW 0x05
  46. #define FLASH_CMD_RD_INNER_STATUS_HIGH 0x35
  47. #define FLASH_CMD_WR_WRITE_ENABLE 0x06
  48. #define FLASH_CMD_WR_WRITE_DISABLE 0x04
  49. #define FLASH_CME_WR_STATUS_REG 0x01
  50. #define FLASH_CME_ERASE_SECTOR 0x20
  51. #define FLASH_CME_ERASE_BLOCK_32K 0x52
  52. #define FLASH_CME_ERASE_BLOCK_64K 0xD8
  53. #define FLASH_CME_ERASE_CHIP 0xC7
  54. #define FLASH_CME_WR_ENTER_DEEP_PD 0xB9
  55. #define FLASH_CME_WR_EXIT_DEEP_PD 0xAB
  56. #define FLASH_CME_RD_NORMAL 0x03
  57. #define FLASH_CME_RD_FAST 0x0B
  58. #define FLASH_CME_RD_FAST_DUAL 0x3B
  59. #define FLASH_CME_RD_FAST_QUAD 0x6B
  60. #define FLASH_CME_WR 0x02
  61. typedef void (*WAIT)(void);
  62. static WAIT wait;
  63. static void flash_setClock(uint8_t dividor) {
  64. dividor = (dividor < 2) ? 2 : dividor;
  65. NOR_FLASH->CTRL0_b.DIV = dividor / 2 - 1;
  66. }
  67. static void flash_cleanOperation() {
  68. NOR_FLASH->TRIGGER_b.OP_CLEAN = TRUE;
  69. while (NOR_FLASH->STATUS_b.BUSY);
  70. NOR_FLASH->TRIGGER_b.OP_CLEAN = FALSE;
  71. while (NOR_FLASH->STATUS_b.BUSY);
  72. }
  73. static uint8_t flash_ReadInnerStatusLow() {
  74. NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
  75. NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_LOW;
  76. NOR_FLASH->TRIGGER_b.OP_START = TRUE;
  77. while (NOR_FLASH->STATUS_b.BUSY);
  78. return (uint8_t)NOR_FLASH->DATA;
  79. }
  80. static uint8_t flash_ReadInnerStatusHigh() {
  81. NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
  82. NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_HIGH;
  83. NOR_FLASH->TRIGGER_b.OP_START = TRUE;
  84. while (NOR_FLASH->STATUS_b.BUSY);
  85. return (uint8_t)NOR_FLASH->DATA;
  86. }
  87. //static void flash_WaitInWritting() {
  88. void flash_WaitInWritting(void) {
  89. FLASH_INNER_STATUS s;
  90. while (NOR_FLASH->STATUS_b.BUSY);
  91. do {
  92. s.INNER.STATUS = flash_ReadInnerStatusLow();
  93. if (!s.INNER.STATUS_b.WIP) {
  94. break;
  95. }
  96. if (wait) {
  97. (*wait)();
  98. }
  99. } while (1);
  100. }
  101. static void flash_WriteWriteEnable(BOOL enable) {
  102. NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
  103. NOR_FLASH->CTRL1_b.CMD =
  104. enable ? FLASH_CMD_WR_WRITE_ENABLE : FLASH_CMD_WR_WRITE_DISABLE;
  105. NOR_FLASH->TRIGGER_b.OP_START = TRUE;
  106. flash_WaitInWritting();
  107. }
  108. static void flash_WriteStatusReg(FLASH_INNER_STATUS *s) {
  109. uint16_t tmp = s->INNER.STATUS;
  110. NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 2;
  111. NOR_FLASH->CTRL1_b.CMD = FLASH_CME_WR_STATUS_REG;
  112. NOR_FLASH->DATA = ((tmp << 8) | (tmp >> 8)) << 16;
  113. NOR_FLASH->TRIGGER_b.OP_START = TRUE;
  114. flash_WaitInWritting();
  115. }
  116. static void flash_Erase(uint8_t cmd, uint32_t addr) {
  117. NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
  118. NOR_FLASH->CTRL1_b.CMD = cmd;
  119. NOR_FLASH->CTRL1_b.ADDRESS = addr;
  120. NOR_FLASH->TRIGGER_b.OP_START = TRUE;
  121. flash_WaitInWritting();
  122. }
  123. static void flash_WriteDeepPowerDownEnable(BOOL enable) {
  124. NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
  125. NOR_FLASH->CTRL1_b.CMD =
  126. enable ? FLASH_CME_WR_ENTER_DEEP_PD : FLASH_CME_WR_EXIT_DEEP_PD;
  127. NOR_FLASH->TRIGGER_b.OP_START = TRUE;
  128. flash_WaitInWritting();
  129. }
  130. static void flash_RwReq(uint8_t cmd, uint32_t addr, uint16_t size) {
  131. NOR_FLASH->CTRL0_b.RW_BYTE_CNT = size;
  132. NOR_FLASH->CTRL1_b.CMD = cmd;
  133. NOR_FLASH->CTRL1_b.ADDRESS = addr;
  134. NOR_FLASH->TRIGGER_b.OP_START = TRUE;
  135. }
  136. //static void flash_WaitReadFifoNotEmpty() {
  137. void flash_WaitReadFifoNotEmpty(void) {
  138. while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) {
  139. if (wait) {
  140. (*wait)();
  141. }
  142. }
  143. }
  144. //static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
  145. uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
  146. uint16_t count = 0;
  147. while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) {
  148. uint32_t d = NOR_FLASH->DATA;
  149. if (size > 3) {
  150. *(data + count++) = d >> 24;
  151. *(data + count++) = (d & 0x00FF0000) >> 16;
  152. *(data + count++) = (d & 0x0000FF00) >> 8;
  153. *(data + count++) = (d & 0x000000FF);
  154. size -= 4;
  155. } else if (size == 3) {
  156. *(data + count++) = (d & 0x00FF0000) >> 16;
  157. *(data + count++) = (d & 0x0000FF00) >> 8;
  158. *(data + count++) = (d & 0x000000FF);
  159. size -= 3;
  160. } else if (size == 2) {
  161. *(data + count++) = (d & 0x0000FF00) >> 8;
  162. *(data + count++) = (d & 0x000000FF);
  163. size -= 2;
  164. } else if (size == 1) {
  165. *(data + count++) = (d & 0x000000FF);
  166. size -= 1;
  167. }
  168. }
  169. return count;
  170. }
  171. static uint16_t flash_WriteFifo(uint16_t size, uint8_t* data) {
  172. uint16_t count = 0;
  173. while (!NOR_FLASH->STATUS_b.WR_FIFO_FULL && size != 0) {
  174. uint32_t d = 0;
  175. if (size > 3) {
  176. d = *(data + count++) << 24;
  177. d |= *(data + count++) << 16;
  178. d |= *(data + count++) << 8;
  179. d |= *(data + count++);
  180. size -= 4;
  181. } else if (size == 3) {
  182. d = *(data + count++) << 24;
  183. d |= *(data + count++) << 16;
  184. d |= *(data + count++) << 8;
  185. size -= 3;
  186. } else if (size == 2) {
  187. d = *(data + count++) << 24;
  188. d |= *(data + count++) << 16;
  189. size -= 2;
  190. } else if (size == 1) {
  191. d = *(data + count++) << 24;
  192. size -= 1;
  193. }
  194. NOR_FLASH->DATA = d;
  195. }
  196. return count;
  197. }
  198. static uint16_t flash_WritePage(uint32_t addr, uint16_t size, uint8_t* data) {
  199. uint16_t actualSize, retSize;
  200. flash_WriteWriteEnable(TRUE);
  201. actualSize = FLASH_PAGE_SIZE - (addr & (FLASH_PAGE_SIZE - 1));
  202. actualSize = (size > actualSize) ? actualSize : size;
  203. retSize = actualSize;
  204. flash_RwReq(FLASH_CME_WR, addr, actualSize);
  205. while (actualSize != 0) {
  206. uint8_t count = flash_WriteFifo(actualSize, data);
  207. actualSize -= count;
  208. data += count;
  209. }
  210. flash_WaitInWritting();
  211. return retSize;
  212. }
  213. void FLASH_Init(FLASH_InitTypeDef* init) {
  214. FLASH_INNER_STATUS s;
  215. assert_param(init);
  216. assert_param(IS_FLASH_PROTECT_MODE(init->FLASH_ProtectMode));
  217. assert_param(IS_FLASH_PROTECT_REGION(init->FLASH_ProtectRegion));
  218. wait = init->FLASH_Wait;
  219. flash_setClock(init->FLASH_ClockDividor);
  220. flash_cleanOperation();
  221. flash_WaitInWritting();
  222. s.INNER.STATUS = flash_ReadInnerStatusLow();
  223. s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
  224. s.INNER.STATUS_b.BP = init->FLASH_ProtectRegion;
  225. s.INNER.STATUS_b.SRP = init->FLASH_ProtectMode;
  226. s.INNER.STATUS_b.QE = init->FLASH_QuadEnable;
  227. flash_WriteWriteEnable(TRUE);
  228. flash_WriteStatusReg(&s);
  229. }
  230. void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable) {
  231. FLASH_INNER_STATUS s;
  232. assert_param(ProtectMode);
  233. assert_param(ProtectRegion);
  234. assert_param(QuadEnable);
  235. flash_WaitInWritting();
  236. s.INNER.STATUS = flash_ReadInnerStatusLow();
  237. s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
  238. *ProtectRegion = s.INNER.STATUS_b.BP;
  239. *ProtectMode = s.INNER.STATUS_b.SRP;
  240. *QuadEnable = (s.INNER.STATUS_b.QE == 1) ? TRUE : FALSE;
  241. }
  242. void FLASH_EraseSector(uint32_t addr) {
  243. flash_WaitInWritting();
  244. flash_WriteWriteEnable(TRUE);
  245. addr = (addr << 8) >> 8;
  246. addr = addr / FLASH_SECTOR_SIZE * FLASH_SECTOR_SIZE;
  247. flash_Erase(FLASH_CME_ERASE_SECTOR, addr);
  248. }
  249. void FLASH_Erase32kBlock(uint32_t addr) {
  250. flash_WaitInWritting();
  251. flash_WriteWriteEnable(TRUE);
  252. addr = (addr << 8) >> 8;
  253. addr = addr / FLASH_BLOCK_32K_SIZE * FLASH_BLOCK_32K_SIZE;
  254. flash_Erase(FLASH_CME_ERASE_BLOCK_32K, addr);
  255. }
  256. void FLASH_Erase64kBlock(uint32_t addr) {
  257. flash_WaitInWritting();
  258. flash_WriteWriteEnable(TRUE);
  259. addr = (addr << 8) >> 8;
  260. addr = addr / FLASH_BLOCK_64K_SIZE * FLASH_BLOCK_64K_SIZE;
  261. flash_Erase(FLASH_CME_ERASE_BLOCK_64K, addr);
  262. }
  263. void FLASH_EraseChip(void) {
  264. flash_WaitInWritting();
  265. flash_WriteWriteEnable(TRUE);
  266. flash_Erase(FLASH_CME_ERASE_CHIP, 0x0);
  267. }
  268. void FLASH_EnableDeepPowerDown(BOOL enable) {
  269. flash_WaitInWritting();
  270. flash_WriteWriteEnable(TRUE);
  271. flash_WriteDeepPowerDownEnable(enable);
  272. }
  273. void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data) {
  274. uint8_t cmd;
  275. assert_param(IS_FLASH_READ_MODE(ReadMode));
  276. assert_param(addr + size <= FLASH_MAX_SIZE);
  277. assert_param(data);
  278. if (size == 0) {
  279. return ;
  280. }
  281. flash_WaitInWritting();
  282. if (ReadMode == FLASH_READ_MODE_NORMAL) {
  283. cmd = FLASH_CME_RD_NORMAL;
  284. } else if (ReadMode == FLASH_READ_MODE_FAST) {
  285. cmd = FLASH_CME_RD_FAST;
  286. } else if (ReadMode == FLASH_READ_MODE_FAST_DUAL) {
  287. cmd = FLASH_CME_RD_FAST_DUAL;
  288. } else {
  289. cmd = FLASH_CME_RD_FAST_QUAD;
  290. }
  291. flash_RwReq(cmd, addr, size);
  292. while (size > 0) {
  293. uint16_t count = 0;
  294. flash_WaitReadFifoNotEmpty();
  295. count = flash_ReadFifo(size, data);
  296. size -= count;
  297. data += count;
  298. }
  299. }
  300. void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data) {
  301. assert_param(addr + size <= FLASH_MAX_SIZE);
  302. assert_param(data);
  303. flash_WaitInWritting();
  304. while (size > 0) {
  305. uint16_t count = flash_WritePage(addr, size, data);
  306. addr += count;
  307. size -= count;
  308. data += count;
  309. }
  310. }